ALSC ASM3P2508AF-08-SR Peak emi reducing solution Datasheet

ASM3P2508A
February 2005
rev 1.3
Peak EMI Reducing Solution
Features
The ASM3P2508A allows significant system cost savings
by reducing the number of circuit board layers and
Generates an EMI optimized clocking signal at
shielding that are required to pass EMI regulations. The
output.
ASM3P2508A modulates the output of PLL in order to
Input frequency – 14.31818 MHz.
spread the bandwidth of a synthesized clock, thereby
Frequency outputs:
decreasing the peak amplitudes of its harmonics. This
o
120 MHz (modulated) - default.
o
72
MHz
(modulated) or
results in significantly lower system EMI compared to the
48
typical narrow band signal produced by oscillators and
MHz
most clock generators. Lowering EMI by increasing a
(modulated) selectable via I2C
± 1% Centre spread.
signal’s bandwidth is called spread spectrum clock
Modulation rate: 40 KHz.
generation.
Byte Write via I2C
Supply voltage range 3.3V ± 0.3V.
The ASM3P2508A has a feature to power down the
Available in 8-pin SOIC Package.
72MHz/48MHz output by writing data into specific
Available
in
Commercial
and
registers in the device via I2C. By writing a ‘0’ into bit 1 of
Industrial
Byte 0, the PLL block generating 72 MHz / 48MHz can be
Temperature ranges.
powered down. Writing ‘0’ into bit ‘7’ of Byte 1 selects an
output of 72 MHz on FOUT2CLK while a ‘1’ at the same
location selects a 48 MHz clock output. However, the I2C
Product Description
block, crystal oscillator, and the PLL block generating
120MHz would be always running.
The ASM3P2508A is a versatile spread spectrum
frequency
modulator.
The
ASM3P2508A
reduces
electromagnetic interference (EMI) at the clock source.
Block Diagram
VDD
XIN
XOUT
Crystal
Oscillator
PLL 1
FOUT1CLK
(120 MHz)
SCL
SDA
I2C
Interface
PLL 2
FOUT2CLK
(72 MHz / 48 MHz)
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara CA • Tel: 408-855-4900 • Fax: 408-855-4999 • www.alsc.com
ASM3P2508A
February 2005
rev 1.3
Pin Configuration
XIN
1
8
VSS
XOUT
2
7
SCL
3
6
SDA
4
5
FOUT2CLK
ASM3P2508A
VDD
FOUT1CLK
Pin Description
Pin Name
Type
Description
XIN
I
Connection to crystal
XOUT
O
Connection to crystal
VDD
P
Power supply for the analog and digital blocks
FOUT1CLK
O
Clock output-1 (120 MHz) - default
FOUT2CLK
O
Clock output-2 ( 72 MHz / 48 MHz)
SDA
I/O
I2C Data
SCL
I
I2C Clock
VSS
P
Ground to entire chip
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ASM3P2508A
February 2005
rev 1.3
Absolute Maximum Ratings
Symbol
Parameter
VDD, VIN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
Storage temperature
-65 to +125
°C
TSTG
Rating
Unit
TA
Operating temperature
0 to 70
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
Supply Voltage
Ambient Operating
Temperature Range
Crystal Resonator
Frequency
Serial Data Transfer
Rate
Output Driver Load
Capacitance
Symbol
Condition /
Description
Min
Typ
Max
Unit
VDD
3.3V ± 10%
3
3.3
3.6
V
+70
°C
TA
-10
FXIN
14.31818
Standard Mode
10
CL
Peak EMI Reducing Solution
MHz
100
Kb/s
15
pF
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ASM3P2508A
February 2005
rev 1.3
DC Electrical Characteristics
(Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated)
Parameter
Symbol
Conditions / Description
Min
Typ
Max
Unit
Overall
Supply Current,
Dynamic
Supply Current,
Static
All input pins
Icc
VDD =3.3V, FCLK =14.31818MHz,
CL=15pF
40
49
60
mA
IDD
VDD = 3.3V, Software Power Down*
27
35
43
mA
2.0
-
VDD+0.3
V
VSS-0.3
-
0.8
V
-1
-
1
µA
-20
-36
-80
µA
High-Level Input
VDD=3.3V
VIH
Voltage
Low-Level Input
VDD=3.3V
VIL
Voltage
High-Level Input
IIH
Current
Low-Level Input
IIL
Current (pull-up)
Clock Outputs (FOUT1CLK, FOUT2CLK)
High-Level Output
Voltage
Low-Level Output
Voltage
Output Impedance
VOH
VDD= 3.3V, IOH = 20mA
2.5
-
3.3
V
VOL
VDD= 3.3V, IOL = 20mA
0
-
0.4
V
ZOH
VO=0.5VDD; output driving high
-
29
-
ZOL
Vo=0.5VDD; output driving low
-
27
-
* FOUT1CLK (120MHz) is functional and not loaded
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ASM3P2508A
February 2005
rev 1.3
AC Electrical Characteristics
Parameter
Symbol
Rise Time
tr
Fall Time
tf
Clock Duty
Cycle
tD
Frequency
Deviation
fD
Jitter, Long
Term
Tj (LT)
Jitter, peak to
peak
Tj (OT)
Clock
Stabilization
Time
tSTB
Conditions/ Description
Min
Typ
Max
FOUT1CLK
FOUT2CLK
FOUT1CLK
VO = 2.0V to 0.8V; CL = 15pF
FOUT2CLK
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
640
440
660
460
680
480
720
520
750
600
800
570
45
-
55
Output Frequency =120MHz
-
±2.73
-
Output Frequency =72MHz /48 MHz
-
±1.78
-
-
45
-
-
165
-
-
110
-
-
390
-
-
125
-
VO = 0.8V to 2.0V; CL = 15pF
On rising edges 500 uS apart at 2.5 V relative to an
ideal clock, PLL B inactive *
On rising edges 500 uS apart at 2.5 V relative to an
ideal clock, PLL B active *
From rising edge to next rising edge at 2.5 V,
PLL B inactive *
From rising edge to next rising edge at 2.5 V,
PLL B active *
Output active from power up, RUN Mode via
Software Power Down
Unit
pS
pS
%
%
pS
pS
PS
* CL = 15 pF, Fxin = 14.31818 MHz
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ASM3P2508A
February 2005
rev 1.3
Typical Crystal Oscillator Circuit
Crystal
C1 = 27 pF
R1 = 510Q
C2 = 27 pF
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal Frequency
14.31818 MHz
Frequency Tolerance
+/- 50 ppm or better at 25°C
Operating temperature range
-20°C to +85°C
Storage Temperature
-40°C to +85°C
Load Capacitance
18pF
Shunt capacitance
7 pF maximum
ESR
25 Q
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ASM3P2508A
February 2005
rev 1.3
I2C Serial Interface Information
The information in this section assumes familiarity with I2C programming.
How to program ASM3P2508A through I2C:
How to Read from ASM3P2508A through I2C:
•
Master (host) sends a start bit.
•
Master (host) will send start bit.
•
Master (host) sends the write address D4 (H).
•
Master (host) sends the write address D4 (H).
•
ASM3P2508A device will acknowledge.
•
ASM3P2508A device will acknowledge.
•
Master (host) sends the beginning byte location
•
Master (host) sends the beginning byte location
(N = 0, 1).
(N = 0, 1).
•
ASM3P2508A device will acknowledge.
•
ASM3P2508A device will acknowledge.
•
Master (host) sends a byte count (X = 1,2)
•
Master (host) will send a separate start bit.
•
ASM3P2508A device will acknowledge.
•
Master (host) sends the read address D5 (H).
•
Master (host) starts sending byte N through byte
•
ASM3P2508A device will acknowledge.
(N+X – 1)
•
ASM3P2508A device will send the byte count
•
•
ASM3P2508A device will acknowledge each byte one
(X = 1, 2).
at a time.
•
Master (host) acknowledges.
Master (host) sends a Stop bit.
•
ASM3P2508A device sends byte N through byte
(N+X – 1).
Controller (Host)
ASM3P2508A
(slave/receiver)
•
Master (host) will need to acknowledge each byte.
•
Master (host) will send a stop bit.
Start Bit
Controller (Host)
Slave Address D4(H)
ACK
ASM3P2508A
(slave/receiver)
Start Bit
Beginning byte location (=N)
ACK
Slave Address D4(H)
ACK
Byte count (=X)
ACK
Beginning Byte = N
ACK
Repeat start
ACK
Beginning byte (Byte N)
Slave address D5(H)
Next Byte (Byte N+1)
ACK
ACK
Byte Count (= X)
----------
ACK
Beginning byte N
Last Byte (Byte N+X-1)
ACK
ACK
Next Byte N+1
Stop Bit
ACK
---------Last Byte (Byte N+X-1)
Not Acknowledge
Stop Bit
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ASM3P2508A
February 2005
rev 1.3
57 (H). To put ASM3P2508A in ‘power down’ mode, the
An example of a Byte Write via I2C to partially ‘power
bit 1 of Byte 0 is to be changed to logic ‘0’. Hence writing a
down’ the device:
55 (H) via I2C into Byte 0 would put the device in partial
‘power down’ mode where the PLL block generating
ASM3P2508A can be partially ‘powered down’ using bit 1
72 MHz / 48 MHz would be powered down while I2C block,
of Byte 0. The organization of the register bits for Byte ‘0’ is
crystal oscillator, and the PLL block generating 120 MHz
given with default values below:
would still be active. The organization of the register bits is
as below:
7
6
5
4
Bit
3
2
Resv Resv Resv Resv Resv Resv
0
1
0
1
0
1
0
PLL2
PLL1
Enable Enable
1
1
1
Bit
3
7
6
5
4
2
1
Resv
Resv
Resv
Resv
Resv
Resv
0
1
0
1
0
1
0
PLL2
PLL1
Enable
Enable
0
1
The function of partial power down of the device is of
interest to us - that is bit 1 of Byte 0. In the default mode
this bit is logic ‘1’. As such, the Byte 0 default value is
Byte 0
Byte 1
FOUT1CLK (MHz)
FOUT2CLK(MHz)
Power up default
6F(H)
3F(H)
120
72
48_MHz Mode
6F(H)
BF(H)
120
48
Power down PLL with 72MHz
6D(H)
3F(H)
120
-
Power down PLL with 48MHz
6D(H)
BF(H)
120
-
Figure showing a complete data transfer:
.
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ASM3P2508A
February 2005
rev 1.3
Package Information
8-Pin SOIC Package
H
E
D
A2
A
A1
D
C
e
L
B
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
S
0°
8°
0°
8°
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ASM3P2508A
February 2005
rev 1.3
Ordering Codes
Part number
Marking
ASM3P2508A-08-ST
3P2508A
8-PIN SOIC, TUBE
Commercial
ASM3P2508A-08-SR
3P2508A
8-PIN SOIC, TAPE AND REEL
Commercial
ASM3I2508A-08-ST
3I2508A
8-PIN SOIC, TUBE
Industrial
ASM3I2508A-08-SR
3I2508A
8-PIN SOIC, TAPE AND REEL
Industrial
ASM3P2508AF-08-ST
3P2508AF
8-PIN SOIC, TUBE, Pb Free
Commercial
ASM3P2508AF-08-SR
3P2508AF
8-PIN SOIC, TAPE AND REEL, Pb Free
Commercial
ASM3I2508AF-08-ST
3I2508AF
8-PIN SOIC, TUBE, Pb Free
Industrial
ASM3I2508AF-08-SR
3I2508AF
8-PIN SOIC, TAPE AND REEL, Pb Free
Industrial
Package Configuration
Temperature
Device Ordering Information
A S M 3 P 2 5 0 8 A F - 0 8 S R
OR - TSOT23 -6,T/R
TT – TSSOP, TUBE
TR - TSSOP, T/R
VT – TVSOP, TUBE
VR – TVSOP, T/R
ST – SOIC, TUBE
SR - SOIC, T/R
QR – QFN, T/R
QT - QFN, TRAY
BT - BGA, TRAY
BR – BGA, T/R
UR - SOT-23,T/R
PIN COUNT
LEAD FREE PART
PART NUMBER
X = Automotive
(-40C to +125C)
I = Industrial
(-40C to +85C)
1 – reserved
2 - Non PLL based
3 – EMI Reduction
4 – DDR support products
5 – STD Zero Delay Buffer
P or n/c = Commercial
(0C to +70C)
6 – power management
7 – power management
8 – power management
9 – Hi performance
0 - reserved
Alliance Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Peak EMI Reducing Solution
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ASM3P2508A
February 2005
rev 1.3
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM3P2508A
Document Version: v1.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
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