ETC GLT5160L16P-7FJ 16m (2-bank x 524288-word x 16-bit) synchronous dram Datasheet

GLT5160L16
ADVANCED
16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
FEATURES
u Single 3.3 V ±0.3 V power supply
u Clock frequency 100 MHz / 125 MHz / 143 MHz/
166 MHz
u Fully synchronous operation referenced to clock rising edge
u Dual bank operation controlled by BA (Bank Address)
u CAS latency- 2 / 3 (programmable)
u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable)
u Burst type- sequential / interleave (programmable)
u Industrial grade available
u
u
u•
u•
u
u
u
Byte control by DQMU and DQML
Column access - random
Auto precharge / All bank precharge controlled by A[10]
Auto refresh and Self refresh
4096 refresh cycles / 64 ms
LVTTL Interface
400-mil, 50-Pin Thin Small Outline Package (TSOP II) with
0.8 mm lead pitch
u• 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball
pitch & 0.35mm Ball diameter.
GENERAL DESCRIPTION
The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The GLT5160L16 achieves
very high speed data rate up to 166 MHz, and is suitable for main
memory or graphic memory in computer systems.
DEC. 2003 (Rev.2.4)
1
FUNCTIONAL BLOCK DIAGRAM
A[10:0]
BA
Mode
Register
CLK
Clock Buffer
CKE
CS
RAS
CAS
WE
Control
Signal Buffer
Control Circuitry
Address Buffer
Memory Array
Bank #0
I/O Buffer
DQ[15:0]
Memory Array
Bank #1
DQML
DQMU
Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Signal Description
Signal
Type
Description
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased.
CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
CS
Input
Chip Select: When CS is high, any command means No Operation.
RAS, CAS, WE
Input
Combination of RAS, CAS, WE defines basic commands.
A[10:0]
Input
A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0].
The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is
high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command,
both banks are precharged.
BA
Input
Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set
with ACT, PRE, READ, WRITE commands.
DQ[15:0]
Input / Output
Data In and Data out are referenced to the rising edge of CLK.
DQML
Input
Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the
current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one
cycle.
DQMU
Input
Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for
the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but
one cycle.
VDD, VSS
Power Supply
Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ
Power Supply
VDDQ and VSSQ are supplied to the Output Buffers only.
2
G-LINK Technology
DEC. 2003 (Rev. 2.4)
FUNCTIONAL DESCRIPTION
The GLT5160L16 provides basic functions, bank (row) activate,
burst read / write, bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of RAS, CAS and WE
at CLK rising edge. In addition to 3 signals, CS, CKE and A[10] are
used as chip select, refresh option, and precharge option,
respectively.
Read (READ) [RAS = H, CAS = L, WE = H]
To know the detailed definition of commands, please see the command truth table.
Write (WRITE) [RAS = H, CAS =WE = L]
READ command starts burst read from the active bank indicated by
BA. First output data appears after CAS latency. When A[10] = H at
this command, the bank is deactivated after the burst read (auto-precharge, READA).
WRITE command starts burst write to the active bank indicated by
BA. Total data length to be written is set by burst length. When
A[10] = H at this command, the bank is deactivated after the burst
write (auto-precharge, WRITEA).
CLK
CS
Chip Select: L=select, h=deselect
RAS
Com-
CAS
Com-
WE
Com-
Precharge (PRE)
[RAS = L, CAS = H, WE = L]
Define Basic Com-
PRE command deactivates the active bank indicated by BA. This
command also terminates burst read / write operation. When A[10]
= H at this command, both banks are deactivated (precharge all,
PREA).
Refresh option @refresh command
CKE
Precharge Option @ precharge or read/write
command
A[10]
Auto-Refresh (REFA)
[RAS = CAS = L, WE = CKE = H]
Activate (ACT) [RAS = L, CAS = WE = H]
ACT command activates a row in an idle bank indicated by BA.
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the
banks are precharged automatically. Any other command should
not be asserted until tRC is met.
Command Truth Table [1]
Command
Mnemonic
CKE n1
CKE n
CS
RAS
CAS
WE
BA
A[10
]
A[9:
0]
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry & Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
V
H
X
Column Address Entry & Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry & Write with Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry & Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry & Read with Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
X
L
V
1. H = High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number
G-LINK Technology
DEC. 2003 (Rev.2.4)
3
Function Truth Table [1] [2]
Current State
IDLE
ROW ACTIVE
READ
WRITE
4
CS
RAS
CAS
Address [3]
WE
Action [4]
Command
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL [5]
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL [5]
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A[10]
PRE / PREA
NOP [6]
L
L
L
H
X
REFA
Auto-Refresh [7]
L
L
L
L
Op-Code, Mode-Add
MRS
Mode Register Set [7]
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA, CA, A[10]
READ / READA
Begin Read, Latch CA, Determine AutoPrecharge
L
H
L
L
BA, CA, A[10]
WRITE / WRITEA
Begin Write, Latch CA, Determine AutoPrecharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
L
H
L
H
BA, CA, A[10]
READ / READA
Terminate Burst, Latch CA, Begin New
Read, Determine Auto-Precharge [8]
L
H
L
L
BA, CA, A[10]
WRITE / WRITEA
Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge [8]
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
L
H
L
H
BA, CA, A[10]
READ / READA
Terminate Burst, Latch CA, Begin Read,
Determine Auto-Precharge [8]
L
H
L
L
BA, CA, A[10]
WRITE / WRITEA
Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge [8]
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Function Truth Table [1] [2] (Continued)
Address [3]
Action [4]
Current State
CS
RAS
CAS
WE
READ with AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A[10]
READ / READA
ILLEGAL
L
H
L
L
BA, CA, A[10]
WRITE / WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL [5]
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
WRITE with AUTO
PRECHARGE
PRE -CHARGING
ROW ACTIVATING
WRITE RECOVERING
Command
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A[10]
READ / READA
ILLEGAL
L
H
L
L
BA, CA, A[10]
WRITE / WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL [5]
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL [5]
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL [5]
L
L
H
H
BA, RA
ACT
ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
NOP [6] (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Row Active after tRCD )
L
H
H
H
X
NOP
NOP (Row Active after tRCD )
L
H
H
L
X
TBST
ILLEGAL [5]
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL [5]
L
L
H
H
BA, RA
ACT
ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL [5]
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL [5]
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL [5]
L
L
H
H
BA, RA
ACT
ILLEGAL [5]
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL [5]
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
G-LINK Technology
DEC. 2003 (Rev.2.4)
5
Function Truth Table [1] [2] (Continued)
Current State
REFRESHING
MODE REGISTER
SETTING
1.
2.
3.
4.
5.
6.
7.
8.
6
Address [3]
Action [4]
CS
RAS
CAS
WE
Command
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A[10]
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A[10]
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
H = High Level, L= Low Level, X = Don't Care.
All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
NOP to bank precharging or in idle state. May precharge bank indicated by BA.
ILLEGAL if any bank is not idle.
Must satisfy bus contention, bus turn around, write recovery requirements.
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Function Truth Table for CKE [1]
Current State
SELF-REFRESH [2]
POWER DOWN
ALL BANKS IDLE [3]
ANY STATE other than
listed above
1.
2.
3.
4.
CKE n1
CKE n
CS
RAS
CAS
WE
Add
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC )
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC )
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
Action
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle [4]
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle [4]
L
L
X
X
X
X
X
Maintain CLK Suspend
H = High Level, L= Low Level, X = Don't Care.
CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.
Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
Must be legal command.
G-LINK Technology
DEC. 2003 (Rev.2.4)
7
Power On Sequence
3. Issue precharge commands for all banks. (PRE or PREA)
Before starting normal operation, the following power on sequence
is necessary to prevent damage or malfunction.
4. After all banks become idle state (after t RP), issue 2 or more
auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
1. Apply power and start clock. Attempt to maintain CKE high,
DQMU / DQML high and NOP condition at the inputs.
After this sequence, the SDRAM is idle state and ready for normal
operation.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200 µs.
SELF
REFRESH
REF
REFS
MODE
REGISTER
SET
MRS
IDLE
REF
AUTO
REFRESH
CKE
CKE
CLK
SUSPEND
POWER
DOWN
ACT
CKE
CKE
ROW
TBST
TBST
WRIT
REA
WRITE
WRITE
SUSPEND
CKE
CKE
READE
READ
WRITE
WRITE
READ
WRITE
CKE
CKE
READ
SUSPEND
CKE
CKE
READ A
SUSPEND
READE
WRITE
WRITE A
SUSPEND
CKE
CKE
READE
WRITE A
READ A
PRE
PRE
POWER
APPLIED
POWER ON
PRE
PRE
PRECHARGE
Automatic Sequence
Command Sequence
Figure 2. Simplified State Diagram
8
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Mode Register
Burst Length, Burst Type and CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these
data until the next MRS command, which may be issued when both
banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
BA
A10
A9
A8
A7
0
0
WBL
0
Ø
CL
LATENC
Y MODE
A6
A5
A4
A3
LTMODE
A2
A1
BT
A0
CLK
BL
CAS
CS
BL
0 0
BT = 0
1
BT = 1
1
RAS
0
0
0
0 1
1 0
2
4
2
4
CAS
0
1
1 1
0 0
8
R
8
R
WE
R
R
R
R
BA, A[10:0]
0
0
0 0
0 1
R
R
0
0
1 0
1 1
2
3
1
1
0 0
0 1
R
R
1
1
0 1
1 0
1
1
1 0
1 1
R
R
1
1 1 Full Page
BURST
LENGT
BURST
TYPE
Write Burst Length (WBL)
A9
ø
Length
= BL specified
1
Single bit (BL =
0
1
R
SEQUENTIAL
INTERLEAVED
CLK
CAS
Command
Address
Burst Length
Burst Length
READ
WRITE
Y
Y
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
Burst Type
Initial
Address
B
L
A2
A1
A0
0
0
0
0
0
0
Column Addressing
Sequential
8
Interleaved
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
–
0
0
0
1
2
3
0
1
2
3
–
0
1
1
2
3
0
1
0
3
2
–
1
0
2
3
0
1
2
3
0
1
–
1
1
3
0
1
2
3
2
1
0
–
–
0
0
1
0
1
–
–
1
1
0
1
0
4
2
G-LINK Technology
DEC. 2003 (Rev.2.4)
9
OPERATIONAL DESCRIPTION
Bank Activate
Precharge
The SDRAM has two independent banks. Each bank is activated by
the ACT command with the bank address (BA). A row is indicated
by the row address A[10:0] The minimum activation interval
between one bank and the other bank is tRRD.
The PRE command deactivates the bank indicated by BA. When
both banks are active, the precharge all command (PREA, PRE +
A[10] = H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command can be issued.
CLK
Command
ACT
ACT
REA
tRRD
A[9:0]
Xa
Xb
Ya
A[10]
Xa
Xb
0
0
1
0
BA
DQ
PRE
ACT
tRAS
tRP
Xb
1
Xb
1
Qa0
Qa1
Qa2
Qa3
Precharge All
Figure 3. Bank Activation and Precharge All (BL=4, CL=3)
10
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Read
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the CAS Latency from the
READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous output data (in case of BL =
4) by interleaving the dual banks. When A[10] is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge start timing depends on CAS Latency. The next ACT command can be
issued after tRP from the internal precharge timing.
CLK
Command
ACT
REA
ACT
REA
PRE
tRCD
A[9:0]
Xa
Ya
Xb
Yb
A[10]
Xa
0
Xb
0
0
0
0
1
1
0
BA
DQ
Qa0
Burst Length
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
CAS Latency
Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)
CLK
Command
ACT
READ A
ACT
tRCD
tRP
A[9:0]
Xa
Y
Xa
A[10]
Xa
1
Xa
0
0
0
BA
DQ
Qa0
Qa1
Qa2
Qa3
Internal Precharge begins
Figure 5. READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
ACT
READ A
CL=3 DQ
CL=2 DQ
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal Precharge Start Timing
Figure 6. READ Auto-Precharge Timing (BL=4)
G-LINK Technology
DEC. 2003 (Rev.2.4)
11
Write
by interleaving the dual banks. From the last input data to the PRE
command, the write recovery time (t RDL) is required. When A[10]
is high at a WRITE command, the auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data cycle. The
next ACT command can be issued after tRP from the internal precharge timing.
After tRCD from the bank activation, a WRITE command can be
issued. 1st input data is set at the same cycle as the WRITE. Following (BL-1) data are written into the RAM, when the Burst Length is
BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data (in case of BL = 4)
CLK
Command
ACT
WRITE
ACT
WRITE
tRCD
A[9:0]
A[10]
BA
Xa
PRE
tRCD
Y
Xb
Y
0
Xa
0
Xb
tRDL (1
0
0
0
1
1
0
Db0
Db1
DQ
Da0
Burst Length
Da1
Da2
Da3
Db2
Db3
Figure 7. Dual Bank Interleaving WRITE (BL=4)
CLK
Command
ACT
WRITE
ACT
tRCD
tRP
A[9:0]
Xa
Y
Xa
A[10]
Xa
1
Xa
0
0
BA
0
tRDL
DQ
Da0
Da1
Da2
Da3
Internal Precharge Begins
Figure 8. WRITE with Auto-Precharge (BL=4)
12
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Burst Interruption
[Read Interrupted by Read]
The burst read operation can be interrupted by a new read of the
same or the other bank. GLT5160L16 allows random column
access. READ to READ interval is 1 CLK minimum.
CLK
Command
REA
REA
READ
READ
A[9:0]
Yi
Yj
Yk
Yl
A[10]
0
0
0
0
BA
0
0
1
0
DQ
Qi0
Qj0
Qj1
Qk0
Qk1
Qk2
Ql0
Ql1
Ql2
Ql3
Internal Precharge Start Timing
Figure 9. READ Interrupted by READ (BL=4, CL=3)
[Read Interrupted by Write]
Burst read operation can be interrupted by write of the same or the
other bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQMU / DQML to
prevent the bus contention. The output is disabled automatically 2
cycles after WRITE assertion.
CLK
Command
REA
WRITE
A[9:0]
Yi
Yj
A[10]
0
0
BA
0
0
DQMU,
Q
D
Qi0
DQM U/ DQML control
Dj0
Dj1
Dj2
Write control
Dj3
Figure 10. READ Interrupted by WRITE (BL=4, CL=3)
G-LINK Technology
DEC. 2003 (Rev.2.4)
13
[Read Interrupted by Precharge]
Burst read operation can be interrupted by precharge of the same
bank. READ to PRE interval is minimum 1 CLK. A PRE command
disables the data output, depending on the CAS Latency. The figure
below shows examples, when the data-out is terminated.
CLK
Command
REA
PRE
DQ
CL=3
Command
Q0
REA
Q0
REA
Command
REA
PRE
Q0
REA
DQ
Q0
REA
Q1
Q2
Q3
PRE
DQ
Command
Q2
Q0
DQ
CL=2
Q1
Q3
PRE
DQ
Command
Q2
PRE
DQ
Command
Q1
Q1
Q2
PRE
Q0
Figure 11. READ Interrupted by Precharge (BL=4)
14
G-LINK Technology
DEC. 2003 (Rev. 2.4)
[Read Interrupted by Burst Terminate]
Similarly to the precharge, burst terminate command can interrupt
burst read operation and disable the data output. READ to TBST
interval is minimum 1 CLK. The figure below shows examples,
when the data-out is terminated.
CLK
Command
REA
TBST
DQ
CL=3
Q0
Command
REA
Q0
REA
Q2
Q0
Command
REA
TBST
DQ
Q0
Command
REA
Q0
Command
REA
Q1
Q2
Q3
TBST
DQ
DQ
Q1
Q3
TBST
DQ
CL=2
Q2
TBST
DQ
Command
Q1
Q1
Q2
TBST
Q0
Figure 12. READ Interrupted by Burst Terminate (BL=4)
G-LINK Technology
DEC. 2003 (Rev.2.4)
15
[Write Interrupted by Write]
Burst write operation can be interrupted by new write of the same or
the other bank. Random column access is allowed. WRITE to
WRITE interval is minimum 1 CLK.
CLK
Command
WRIT
WRIT
WRITE
WRITE
A[9:0]
Yi
Yj
Yk
Yl
A[10]
0
0
0
0
BA
0
0
1
0
DQ
Di0
Dj0
Dj1
Dk0
Dk1
Dk2
Dl0
Dl1
Dl2
Dl3
Figure 13. WRITE Interrupted by WRITE (BL=4)
interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is “don't care”. Using the DQMU / DQML to
prevent the bus contention is optional.
[Write Interrupted by Read]
Burst write operation can be interrupted by read of the same or the
other bank. Random column access is allowed. WRITE to READ
CLK
Command
WRITE
READ
WRITE
READ
A[9:0]
Yi
Yj
Yk
Yl
A[10]
0
0
0
0
BA
0
0
0
1
DQMU,
DQ
Di0
Qj0
Qj1
Dk0
Dk1
Figure 14. WRITE interrupted by READ (BL=4, CL=3)
16
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Ql0
[Write Interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same
bank. Random column access is allowed. Because the write recovery time (tRDL) is required between the last input data and the next
PRE, 3rd data should be masked with DQMU / DQML shown as
below.
CLK
Command
WRITE
PRE
ACT
A[9:0]
Ya
Xb
A[10]
0
0
Xb
BA
0
0
0
DQMU,
DQ
Di0
Di1
This data should be masked to satisfy tRDL requirement.
Figure 15. WRITE Interrupted by Precharge (BL=4)
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation. In
this case, the write recovery time is not required and the bank
remains active. The figure below shows the case 3 words of data are
written. Random column access is allowed. WRITE to TBST interval is minimum 1 CLK.
CLK
Command
WRITE
A[9:0]
Ya
A[10]
0
BA
0
TBST
DQMU,
DQ
Da0
Da1
Da2
Figure 16. WRITE Interrupted by Burst Terminate (BL=4)
G-LINK Technology
DEC. 2003 (Rev.2.4)
17
Auto Refresh
Single cycle of auto-refresh is initiated with a REFA (CS = RAS =
CAS = L, WE = CKE = H) command. The refresh address is generated internally. 4096 REFA cycles within 64 ms refresh 16 Mbit
memory cells. The auto-refresh is performed on each bank alternately (ping-pong refresh). Before performing an auto-refresh, both
banks must be in the idle state. Additional commands must not be
supplied to the device before tRC from the REFA command.
CLK
CS
NOP or Deselect
RAS
CAS
WE
CKE
Minimum t RC
A[10:0]
BA
Auto Refresh on Bank 0
Auto Refresh on Bank 1
Figure 17. Auto Refresh
Self Refresh
Self-refresh mode is entered by issuing a REFS command (CS =
RAS = CAS = L, WE = H, CKE = L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enabled input (but
asynchronous), all other inputs including CLK are disabled and
ignored, and power consumption due to synchronous inputs is
saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX).
After tRC from REFSX both banks are in the idle state and a new
command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
CLK
Stable CLK
CS
NOP
RAS
CAS
WE
CKE
new command
A[10:0]
X
minimum tRC for recovery
BA
0
Self Refresh Entry
Self Refresh Exit
Figure 18. Self-Refresh
18
G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK Suspend
down, output suspend or input suspend. CKE is a synchronous input
except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at
the following cycle is ignored.
CKE controls the internal CLK at the following cycle. Figure 19
and Figure 20 show how CKE works. By negating CKE, the next
internal CLK is suspended. The purpose of CLK suspend is power
ext. CLK
CKE
int. CLK
CLK
CKE
Command
Standby Power Down
PRE
NOP
NOP
CKE
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Active Power Down
ACT
NOP
NOP
NOP
NOP
NOP
Figure 19. Power Down by CKE
CLK
CKE
Command
DQ
WRITE
D0
REA
D1
D2
D3
Q0
Q1
Q2
Q3
Figure 20. DQ Suspend by CKE
G-LINK Technology
DEC. 2003 (Rev.2.4)
19
DQMU / DQML Control
DQML to write mask latency is 0. During reads, DQMU / DQML
forces upper / lower output to Hi-Z word by word. DQMU / DQML
to output Hi-Z latency is 2.
DQMU / DQML is a dual function signal defined as the data mask
for writes and the output disable for reads. During writes, DQMU /
DQML masks upper / lower input data word by word. DQMU /
CLK
Command
WRITE
REA
DQML
DQ[7:0]
DQMU
DQ[15:8]
D0
D2
D3
Q0
Masked by DQML =
D0
D1
Masked by DQMU =
D3
Q0
Disabled by DQMU
Figure 21. DQMU / DQML Function
20
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Q1
Q3
Disabled by DQML =
Q2
Q3
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Ratings
Unit
VDD
Symbol
Supply Voltage
Parameter
with respect to VSS
Conditions
-1.0 to 4.6
V
VDDQ
Supply Voltage for Output
with respect to VSSQ
-1.0 to 4.6
V
VI
Input Voltage
with respect to VSS
-1.0 to 4.6
V
VO
Output Voltage
with respect to VSSQ
-1.0 to 4.6
V
IO
Output Current
50
mA
PD
Power Dissipation
TA = 25 °C
1000
mW
TOPR
Operating Temperature
comsumer
0 to 70
°C
-40 to 85
°C
TSTG
Storage Temperature
-65 to 150
°C
Industrial
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Recommended Operating Conditions (T A = 0 to +70°C, unless otherwise noted)
Min
Typ
Max
Unit
VDD
Symbol
Supply Voltage
Parameter
3.0
3.3
3.6
V
VDDQ
Supply Voltage for Output
3.0
3.3
3.6
V
VIH [1]
High-Level Input Voltage all inputs
2.0
VDDQ + 0.3
V
VIL [2]
Low-Level Input Voltage all inputs
-0.3
0.8
V
1. VIH (max) = 5.6 V for pulse width less than 3 ns.
2. VIL (min) = -2.0 V for pulse width less than 3 ns.
DC Characteristics (TA = 0 to +70°C, VDD = VDDQ = 3.3 ±0.3V, VSS = VSSQ = 0 V, unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Max
2.4
Unit
VOH
High-Level Output Voltage
IOH = -2 mA
V
VOL
Low-Level Output Voltage
IOL = 2 mA
0.4
V
IOZ
Off-state Output Current
Q floating VO = 0 to VDDQ
-10
10
µA
II
Input Current
VIH = 0 to V DDQ + 0.3 V
-10
10
µA
Capacitance (TA = 0 to +70°C, V DD = VDDQ = 3.3 ±0.3 V, VSS = VSSQ = 0 V, unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Max
Unit
CI(A)
Input Capacitance, address pin
VI = VSS
2.5
5
pF
CI(C)
Input Capacitance, control pin
f = 1 MHz
2.5
5
pF
CI(K)
Input Capacitance, CLK pin
VI = 25 mVrms
2.5
5
pF
CI/O
Input Capacitance, I/O pin
4
7
pF
G-LINK Technology
DEC. 2003 (Rev.2.4)
21
Average Supply Current from VDD
(TA = 0 to +70°C, VDD = VDDQ = 3.3 ±0.3 V, VSS = VSSQ = 0 V, unless otherwise noted)
Rating (Max)
-6
-7
-8
-10
Unit
ICC1S
Symbol
Operating Current, Single Bank
Parameter
tRC = min, tCLK = min, BL = 1, CL = 3
Test Conditions
120
110
100
90
mA
ICC1D
Operating Current, Dual Bank
tRC = min, tCLK = min, BL = 1, CL = 3
170
150
140
120
mA
ICC2H
Standby Current, CKE = H
both banks idle, t CLK = min, CKE = H
20
20
20
20
mA
ICC2L
Standby Current, CKE = L
both banks idle, t CLK = min, CKE = L
2
2
2
2
mA
ICC3H
Active Standby Current, CKE = H
both banks active, tCLK = min, CKE = H
35
35
35
35
mA
ICC3L
Active Standby Current, CKE = L
both banks active, tCLK = min, CKE = L
4
4
4
4
mA
ICC4
Burst Current
tCLK = min, BL = 4, CL = 3, both banks
active
180
170
160
140
mA
ICC5
Auto-Refresh Current
tRC = min, tCLK = min
110
100
90
80
mA
ICC6
Self-Refresh Current
CKE < 0.2 V
Low Power
1
1
1
1
mA
500
500
500
500
µA
AC Characteristics (TA = 0 to +70°C, VDD = VDDQ = 3.3 ±0.3 V, VSS = VSSQ = 0 V, unless otherwise noted) [1]
-6
Symbol
tCLK
Parameter
CLK Cycle Time
Min
-7
Max
Min
-8
Max
Min
-10
Max
Min
Max
Unit
CL=2
-
9
10
13
ns
CL=3
6
7
8
10
ns
tCH
CLK High Pulse Width
2.5
3
3
3.5
ns
tCL
CLK Low Pulse Width
2.5
3
3
3.5
ns
tT
Transition Time of CLK
1
tIS
Input Setup Time (all inputs)
2
tIH
Input Hold Time (all inputs)
1
1
tRC
Row Cycle Time
60
63
tRCD
Row to Column Delay
18
tRAS
Row Active Time
42
tRP
Row Precharge Time
18
21
24
30
ns
tCCD
Column Address to Column Adress Delay
1
1
1
1
CLK
tRRD
Act to Act Delay Time
2
2
2
2
CLK
tRSC
Mode Register Set Cycle Time
1
1
1
1
CLK
tRDL
Last Data-In to Row Precharge Delay
1
tREF
Refresh Interval Time
10
1
10
2.5
21
100k
42
10
1
1
ns
90
ns
48
30
100k
1.4
22
G-LINK Technology
DEC. 2003 (Rev. 2.4)
1.4
60
ns
100k
1
65.6
Any AC timing is
referenced to the
input signal crossing
Signal
ns
72
1. Input Pulse Levels: 0.4 V to 2.4 V with tr/tf = +1/+1 ns. Input Timing Measurement Level: 1.4 V.
CLK
10
ns
1
65.6
1
2.5
24
100k
1
65.6
1
2.5
ns
CLK
65.6
ms
Switching Characteristics (TA = 0 to +70°C, VDD = VDDQ = 3.3 ±0.3 V, VSS = VSSQ = 0 V unless otherwise
noted)
-6
Symbol
Parameter
Min
tAC
Access Time from
CL=2
tOH
Output Hold Time from CLK
tOLZ
Delay Time, Output Low Impedance from
CLK
tOHZ
Delay Time, Output High Impedance from CLK
-7
Max
Min
-
CL=3
-8
Max
Min
7
5.5
-10
Max
Min
Max
Unit
10
ns
7
ns
9
6
6
2.5
2.5
3
3
ns
1
1
1
1
ns
CL=2
-
7
7
9
ns
CL=3
5.5
6
6
7
ns
CLK
1.4
VTT = 1.4V
tAC
50 Ω
VREF =
-
DQ
tOHZ
1.4
tOLZ
+
VOUT
tOH
50 pF (1)
CLK
1.4
Output Timing Measurement Reference Point
1. For GLT5160L16-6/7, the Output Load is 30
DQ
1.4
Figure 22. Output Load Condition
G-LINK Technology
DEC. 2003 (Rev.2.4)
23
CLK
tRCD
tRDL
tRAS
tRP
CS
tRC
RAS
CAS
WE
HIG
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
BA
B0
DQ
Yi
Xb
B0
Di0
ACT
Xb
WRITE
Di1
Di2
B0
B0
PRE
ACT
Di3
Figure 23. WRITE Cycle (single bank) BL=4
24
G-LINK Technology
DEC. 2003 (Rev. 2.4)
tRDL
tRDL
CLK
tRCD
tRCD
tRAS
CS
tRRD
tRAS
RAS
CAS
WE
HIG
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
BA
B0
DQ
ACT
Ya
Xb
Yb
Xb
B0
B1
Da0
Da1
WRIT
ACT
Da2
Da3
B
B0
Db0
Db1
WRIT
PRE
B1
Db2
Db3
PRE
Figure 24. WRITE Cycle (Dual Bank) BL=4
G-LINK Technology
DEC. 2003 (Rev.2.4)
25
CLK
tRCD
tRAS
tRP
CS
tRC
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
A[10]
Xa
Xb
BA
B0
B0
DQ
Xb
Qa0
ACT
READ
Qa1
Qa2
Qa3
PRE
Figure 25. READ Cycle (Single Bank) BL=4, CL=3
26
G-LINK Technology
DEC. 2003 (Rev. 2.4)
ACT
tRCD
tRCD
CLK
tRRD
tRAS
tRAS
tRP
CS
tRC
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Xb
Yb
Xc
Xb
Xc
BA
DQ
Qa0
ACT
READ
ACT
Qa1
Qa2
READ
PRE
Qa3
Qb0
Qb1
Qb2
PRE
ACT
Qb3
Figure 26. READ Cycle (Dual Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
27
CLK
tRCD
tRAS
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Yb
BA
DQ
Da0
ACT
WRITE
Da1
Da2
Da3
Qb0
READ
Figure 27. WRITE to READ (Single Bank) BL=4, CL=3
28
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Qb1
Qb2
PRE
Qb3
tRCD
tRCD
CLK
tRRD
tRAS
tRAS
tRP
CS
tWR
tRC
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Xb
Yb
Xc
Xb
Xc
BA
DQ
ACT
Da0
Da1
WRITE
ACT
Da2
Da3
REA
PRE
Qb0
Qb1
PRE
ACT
Qb2
Qb3
Figure 28. WRITE to READ (Dual Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
29
CLK
tRCD
tRAS
CS
RAS
CAS
WE
CKE
DQML
DQMU
A[9:0]
Xa
A[10]
Xa
Ya
Yb
BA
DQ[7:0]
Da0
DQ[15:8]
Da0
ACT
WRITE
Da2
Da1
Da3
Qb0
Qb1
Da3
Qb0
Qb1
READ
Qb3
Qb2
PRE
Figure 29. DQM Byte Control for WRITE to READ (Single Bank) BL=4, CL=3
30
G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK
tRCD
tRDL
tRAS
CS
RAS
CAS
WE
CKE
for output disable
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Yb
BA
DQ
Qa0
PRE
READ
Qa1
Db0
Db1
WRITE
Db2
Db3
PRE
Figure 30. READ to WRITE (Single Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
31
tRCD
tRCD
CLK
tRRD
tRAS
tRP
tRAS
CS
tRC
tRDL
RAS
CAS
WE
CKE
for output disable
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Xb
Yb
Xc
Xb
Xc
BA
DQ
Qa0
ACT
READ
ACT
Qa1
Db0
PRE
WRITE
Db1
Db2
ACT
Figure 31. READ to WRITE (Dual Bank) BL=4, CL=3
32
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Db3
PRE
CLK
tRCD
tRDL+ t RP
tRC
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Xb
Xb
BA
DQ
Da0
ACT
WRITE
Da1
Da2
Da3
Internal Precharge starts
this timing depends on BL
ACT
Figure 32. Write with Auto-Precharge BL=4
G-LINK Technology
DEC. 2003 (Rev.2.4)
33
CLK
tRCD
tRP
tRC
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
A[10]
Xa
Ya
Xb
Xb
BA
DQ
Qa0
ACT
READ
Qa1
Qa2
Internal Precharge start s @ CL=3, BL=4
this timing depends on CL and BL
Qa3
ACT
Figure 33. Read with Auto-Precharge BL=4, CL=3
34
G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK
tRP
tRC
CS
RAS
CAS
WE
DC High
CKE
DQMU,
A[9:0]
A[10]
BA
DQ
PRE
If any bank is active, it
must be precharged
REF S
REF
Figure 34. Auto-Refresh
G-LINK Technology
DEC. 2003 (Rev.2.4)
35
CLK
tRP
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
A[10]
BA
DQ
If any bank is active, it
PRE must be precharged
REF S
Figure 35. Self-Refresh Entry
36
G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK
tRC
NOP or desel
CS
RAS
CAS
WE
CKE
tSRX
DQMU,
A[9:0]
Xa
A[10]
Xa
BA
DQ
Internal CLK Re-start
ACT
Figure 36. Self-Refresh Exit
G-LINK Technology
DEC. 2003 (Rev.2.4)
37
CLK
tRP
tRSC
tRCD
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Mode
A[10]
Xa
Ya
Xa
BA
DQ
Qa0
PRE
If any bank is
active, it must be
precharged
MRS
ACT
READ
Figure 37. Mode Register Set BL=4, CL=3
38
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Qa1
Qa2
PACKAGING INFORMATION
VDD
DQ0
1
2
50
49
VSS
DQ15
DQ1
VSSQ
3
4
48
47
DQ14
VSSQ
DQ2
DQ3
5
6
46
45
DQ13
DQ12
VDDQ
DQ4
7
8
44
43
VDDQ
DQ11
DQ5
VSSQ
9
10
42
41
DQ10
VSSQ
DQ6
DQ7
11
12
40
39
DQ9
DQ8
VDDQ
DQML
13
14
38
37
VDDQ
NC
WE
CAS
15
16
36
35
DQMU
CLK
RAS
CS
17
18
34
33
CKE
NC
BA
A10
19
20
32
31
A9
A8
A0
A1
21
22
30
29
A7
A6
A2
A3
23
24
28
27
A5
A4
VDD
25
26
VSS
Top View
Figure 38. 50-Pin 400 mil TSOP II Pin Assignment
1
2
A
VSS
B
3
4
5
6
7
DQ15
DQ0
VDD
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ
DQ5
F
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
NC
NC
DQ7
H
NC
NC
NC
NC
J
NC
UDQM
LDQM
WE#
K
NC
CLK
RAS#
CAS#
L
CKE
NC
NC
CS#
M
A11
A9
NC
NC
N
A8
A7
A0
A10
P
A6
A5
A2
A1
R
VSS
A4
A3
VDD
Figure 38-1. 60-Ball VFBGA Ball
G-LINK Technology
DEC. 2003 (Rev.2.4)
39
unit : mm
Figure 39. 50-Pin 400 mil Plastic TSOP II Package Dimensions
40
G-LINK Technology
DEC. 2003 (Rev. 2.4)
0.08 M
C
0.15 M
C
A1 CORNER
A
B
0.35~0.40(60X)
7
6
5
4
3
2
1
A
B
C
D
E
F
9.10
10.10 ± 0.10
G
H
J
K
L
M
0.65
N
P
R
0.65
B
0.20 C
3.90
A
6.40 ± 0.10
0.15(4X) C
1.00 MAX
0.45 ± 0.03
0.21 ± 0.04
C 0.20
SEATING PLANE
C
0.27 ± 0.05
60-Ball VFBGA ( BOTTOM VIEW )
G-LINK Technology
DEC. 2003 (Rev.2.4)
41
ORDERING INFO
GLT5160L16
Part Number
Mode
Cycle Time
Max Frequency
Interface
GLT5160L16-10TC
Synchronous
10
100 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16-8TC
Synchronous
8
125 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16-7TC
Synchronous
7
143 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16-6TC
Synchronous
6
166 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16-10FJ
Synchronous
10
100 MHz
LVTTL
60-Ball VFBGA
GLT5160L16-8FJ
Synchronous
8
125 MHz
LVTTL
60-Ball VFBGA
GLT5160L16-7FJ
Synchronous
7
143 MHz
LVTTL
60-Ball VFBGA
GLT5160L16-6FJ
Synchronous
6
166 MHz
LVTTL
60-Ball VFBGA
GLT5160L16I-10TC
Synchronous
10
100 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16I-8TC
Synchronous
8
125 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16I-7TC
Synchronous
7
143 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16I-6TC
Synchronous
6
166 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16I-10FJ
Synchronous
10
100 MHz
LVTTL
60-Ball VFBGA
GLT5160L16I-8FJ
Synchronous
8
125 MHz
LVTTL
60-Ball VFBGA
GLT5160L16I-7FJ
Synchronous
7
143 MHz
LVTTL
60-Ball VFBGA
GLT5160L16I-6FJ
Synchronous
6
166 MHz
LVTTL
60-Ball VFBGA
GLT5160L16P-10TC
Synchronous
10
100 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16P-8TC
Synchronous
8
125 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16P-7TC
Synchronous
7
143 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16P-6TC
Synchronous
6
166 MHz
LVTTL
50-Pin 400 mil Plastic TSOP II
GLT5160L16P-10FJ
Synchronous
10
100 MHz
LVTTL
60-Ball VFBGA
GLT5160L16P-8FJ
Synchronous
8
125 MHz
LVTTL
60-Ball VFBGA
GLT5160L16P-7FJ
Synchronous
7
143 MHz
LVTTL
60-Ball VFBGA
GLT5160L16P-6FJ
Synchronous
6
166 MHz
LVTTL
60-Ball VFBGA
42
G-LINK Technology
DEC. 2003 (Rev. 2.4)
Package
Parts Numbers (Top Mark) Definition :
GLT 5 160 L 16
4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM
-SRAM
CONFIG.
064 : 8K
256 : 256K
512 : 512K
100 : 1M
200 : 2M
400 : 4M
04 : x04
08 : x08
16 : x16
32 : x32
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)
P
- 7 TC
PACKAGE
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
55 : 55ns
70 : 70ns
85 : 85ns
120 : 120ns
-DRAM
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.0V
-SDRAM
POWER
40 : 4M
160 : 16M
320 : 32M,4Bank
640 : 64M
Blank : Standard
L : Low Power
LL : Low Low Power
SL : Super Low Power
25 : 25ns
28 : 28ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
70 : 70ns
80 : 80ns
100 : 100ns
SDRAM :
5 : 5ns/200 MHZ
5.5 : 5.5ns/182 MHZ
6 : 6ns/166 MHZ
7 : 7ns/143 MHZ
8 : 8ns/125 MHZ
10 : 10ns/100 MHZ
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll (40/44)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8
FJ : 60Ball VFBGA
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
P : Pb – free part
G-LINK Technology
DEC. 2003 (Rev.2.4)
43
44
G-LINK Technology
DEC. 2003 (Rev. 2.4)
www.glinktech.com
G-LINK Technology
1759 S. Main St., Suite 128
Milpitas, CA 95035 U.S.A.
TEL: 408-240-1380 • FAX: 408-240-1385
G-LINK Technology Corporation, Taiwan
6F, No.24-2, Industry E.RD.IV,
Science Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
TEL: 03-578-2833 • FAX: 03-578-5820
© 1998 G-LINK Technology
All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology.
Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given.
G-LINK Technology reserves the right to change products or specifications without notice.
The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for
G-LINK applications assistance, customer’s product design, or infringement of patents arising from use of semiconductor devices in such systems’ designs. Nor does G-LINK warrant or represent that any
patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used.
G-LINK Technology’s products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for surgical implant into the human
body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause significant injury to the user in the event of failure.
The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies.
Printed in USA
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