ON CS51220ED16 Feed forward voltage mode pwm controller with programmable synchronization Datasheet

CS51220
Feed Forward Voltage
Mode PWM Controller
with Programmable
Synchronization
CS51220 is a single output PWM Controller with switching
frequency up to 500 kHz. The feed forward voltage mode control
provides excellent line regulation for wide input range. This PWM
controller has a synchronization output allowing programmable phase
delay. For overcurrent protection, the “soft hiccup” technique
effectively limits the output current with maximum flexibility. In
addition, this device includes such features as: soft start,
pulse−by−pulse current limit, programmable foldback current limit,
volt−second clamping, maximum duty cycle, overvoltage and
undervoltage protection, and synchronization input. The CS51220 is
available in 16 SO narrow surface mount package.
16
1
SO−16
D SUFFIX
CASE 751B
PIN CONNECTIONS AND
MARKING DIAGRAM
VO
GND
VCC
VREF
ISET
ISENSE
OV
UV
A
WL, L
YY, Y
WW, W
1
16
CS51220
AWLYWW
Features
Constant Frequency Feed Forward Voltage Mode Control
Programmable Pulse by Pulse Overcurrent Limit
Programmable Foldback Overcurrent Limit with Delay
Soft Hiccup Overcurrent Protection with Programmable Foldback
Frequency Synchronization Output with Programmable Phase Delay
Synchronization Input to Higher or Lower Frequency
Direct Connection to External Opto Isolators
Logic Gate Output Signal
Accurate Volt−Second Clamping
Programmable Soft Start
Logic Input to Disable IC
Line Overvoltage and Undervoltage Monitoring
3.3 V 3% Reference Voltage Output
•
•
•
•
•
•
•
•
•
•
•
•
•
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SYNCO
VSD
SS
COMP
FF
DISABLE
SYNCI
CT
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2006
July, 2006− Rev. 7
1
Package
Shipping
CS51220ED16
SO−16
48 Units/Rail
CS51220EDR16
SO−16
2500 Tape & Reel
Publication Order Number:
CS51220/D
2
Figure 1. Application Diagram, 48 V to 3.3 V Converter
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C9
1000 pF
C6
0.1 μF
GND
R10
15 k
C4
470 pF
R2
174 k
R12
11.8 k
2.0 k
R14
C8
390 pF
C3
1.5 μF
100 V
36−72 V
C7
1000 pF
R7
150 k
R9
R11
510 k 510 k
R8
64.9 k
R6
7.5 k
R5
10 k
C2
0.1 μF
500 V
C1
0.2 μF
100 V
1.0 μH
L2
VCC
SS
SYNCI
VO
GND
ISENSE
SYNCO
U1
0.1 μF
C5
R23
220
C11
1.0 μF
ENABLE
SYNC OUT
SYNC IN
COMP DISABLE
OV
ISET
UV
CT
VSD
VREF
FF
D1 9.1 V
MMSZ5239B
D2 15 V
MMSZ5245B
Q2
MMFT1N10E
R1
100 k
R3
10
R24
3.3 k
100 pF
C12
R13
100
C10
0.1 μF
NC
GND
INA
VDD
R14 R15
36
10 k
D4
MMSD4148T1
U4
U2
MOC213
R17
182
OUT
GND
OUT
VDD
70:1
T1
MMSD4148T1
NCP4414
VIN
CS51220
D3
R18
1.0 K
R19
3.92 k
Q1
MTB20N20E
20:5
T2
R16
10
C15
U3
TLV431ASNT1
100 pF
0.022 μF
C14
2.21 k
R20
6.8 μH
L1
D5A
MBRB2535CTL
C13
100 pF
200 V
C12
680 pF
R23
10
D5B
MBRB2535CTL
10
R4
R22
24.3 k
R21
40.2 k
C18
330 μF
C17
330 μF
VORTN
VOUT
3.3 V @
5.0 A
CS51220
CS51220
MAXIMUM RATINGS*
Rating
Value
Unit
150
°C
−65 to +150
°C
ESD Susceptibility (Human Body Model)
2.0
kV
Thermal Resistance, Junction−to−Case, RΘJC
28
°C/W
Thermal Resistance, Junction−to−Ambient, RΘJA
115
°C/W
230 peak
°C
Operating Junction Temperature, TJ
Storage Temperature Range, TS
Lead Temperature Soldering:
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Reflow: (SMD styles only) (Note 1)
MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
Gate Logic Output
VO
20 V
−0.3 V
100 mA
100 mA
Current Sense Input
ISENSE
6.0 V
−0.3 V
10 mA
10 mA
Timing Capacitor
CT
6.0 V
−0.3 V
10 mA
10 mA
Feed Forward
FF
6.0 V
−0.3 V
10 mA
100 mA
Error Amp Output
COMP
6.0 V
−0.3 V
10 mA
10 mA
Feedback Voltage
VFB
6.0 V
−0.3 V
10 mA
10 mA
Sync Input
SYNCI
20 V
−0.3 V
10 mA
10 mA
Power Down Input
DISABLE
20 V
−0.3 V
10 mA
10 mA
Undervoltage
UV
6.0 V
−0.3 V
10 mA
10 mA
Overvoltage
OV
6.0 V
−0.3 V
10 mA
10 mA
Current Set
ISET
6.0 V
−0.3 V
10 mA
10 mA
Soft Start
SS
6.0 V
−0.3 V
10 mA
10 mA
Power Supply
VCC
20 V
−0.3 V
10 mA
50 mA
Sync Output
SYNCO
20 V
−0.3 V
100 mA
100 mA
Reference Voltage
VREF
6.0 V
−0.3 V
Internally Limited
10 mA
Sync Delay
VSD
6.0 V
−0.3 V
1.0 mA
1.0 mA
Ground
GND
N/A
N/A
50 mA
N/A
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CS51220
ELECTRICAL CHARACTERISTICS (−40°C < TA < 85°C; −40°C < TJ < 125°C; 4.7 V < VCC < 16 V; CT = 390 pF; unless
otherwise specified.)
Test Conditions
Min
Typ
Max
Unit
Start Threshold
−
4.0
4.4
4.7
V
Stop Threshold
−
3.3
3.8
4.1
V
400
600
1000
mV
Characteristic
Supply Voltage/Current
Hysteresis
Start − Stop
ICC @ Startup
VCC < UVL Start Threshold
−
−
500
μA
ICC Operating, Low VCC
4.7 V < VCC < 10 V
−
−
7.5
mA
ICC Operating, High VCC
10 V < VCC < 16 V
−
−
9.0
mA
3.2
3.3
3.4
V
Reference Voltage
Total Accuracy
0 mA < IREF < 2.0 mA
Line Regulation
IREF = 2.0 mA
−
6.0
20
mV
Load Regulation
0 mA < IREF < 2.0 mA, VCC = 8.0 V
−
6.0
15
mV
Operating Life Shift
T = 1000 Hrs., Note 2
−
4.0
20
mV
Fault Voltage
−
2.8
2.95
3.1
V
VREF OK Voltage
−
2.9
3.05
3.2
V
VREF OK Hysteresis
−
50
100
150
mV
2.0
25
65
mA
223
266
309
kHz
Current Limit
VREF = 2.5 V
Oscillator
Frequency Accuracy
−
Temperature Stability
Note 2
−
8.0
−
%
Max Frequency
Note 2
500
−
−
kHz
80
85
90
%
Duty Cycle
−
Peak Voltage
Note 2
1.9
2.0
2.1
V
Valley Voltage
Note 2
0.85
0.90
0.98
V
Discharge Current
VCT = 1.5 V
0.70
0.85
1.05
mA
Charge Current
VCT = 1.5 V
127
150
183
μA
Synchronization
SYNCI Input Threshold
fSYNC = 500 kHz
1.0
2.0
3.0
V
SYNCI Input Resistance
VSYNC = 0.5
50
150
250
kΩ
Minimum Sync Frequency
Reduction of nominal frequency.
25
−
−
%
−
−
200
ns
5.0
6.5
7.5
V
Minimum Input Sync Pulse Width
−
SYNCO Output High
RSYNCO = 5.0 k, VCC = 8.0 V
SYNCO Output Low
Sink 1.0 mA, VSD = 2.5 V
−
0.2
0.4
V
SYNCO Delay Time
VCT = 1.5 V, Toggle VSD
100
200
300
ns
2. Guaranteed by design. Not tested in production.
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CS51220
ELECTRICAL CHARACTERISTICS (continued) (−40°C < TA < 85°C; −40°C < TJ < 125°C; 4.7 V < VCC < 16 V; CT = 390 pF; unless
otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output (continued)
High Saturation Voltage
VCC − VO, VCC = 10 V, ISOURCE = 100 μA
−
1.4
2.0
V
Low Saturation Voltage
VO − GND, ISINK = 100 μA
−
0.7
1.0
V
Pull Down Resistance
ISINK = 100 μA
25
50
75
kΩ
Rise Time
VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load
−
35
80
ns
Fall Time
VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load
−
25
50
ns
Feed Forward
Discharge Voltage
IFF = 2.0 mA
0.25
0.35
0.45
V
Discharge Current
FF = 1.0 V
2.0
10
30
mA
FF to VO Delay
Connect VO to FF, Measure min. pulse width.
50
75
150
ns
−
1.15
1.3
1.45
V
0.8
1.4
1.4
1.6
1.7
1.7
V
V
180
200
215
mV
FF Clamp Voltage
COMP Switch Off Voltage
VFF = 0.2 V, Ramp down VCOMP
VFF = 0.2 V, Ramp down VCOMP −40°C
Overcurrent Protection
−
Overcurrent Comparator DC Offset
ISENSE Attenuation
ΔVISET/ΔVISENSE
0.9
0.94
0.98
V/V
ISENSE Input Resistance
ΔVISENSE = 0 V
40
82
150
kΩ
ISENSE to GATE Delay
VISET = 0.5 V
50
100
175
ns
ISET Foldback Sink Current
ISET = 0.5 V, SS = 1.5 V and ISENSE = 0.5 V
12
15
18
μA
Overvoltage Threshold
OV pin increasing
1.9
2.0
2.1
V
OV Hysteresis Current
OV = 2.15 V
10
12.5
15
μA
Undervoltage Threshold
UV pin decreasing
0.95
1.00
1.05
V
25
75
125
mV
External Voltage Monitors
UV Hysteresis
−
Soft Start
Charge Current
SS = 1.5 V
35
50
65
μA
Discharge Current
SS = 1.5 V, UV = 1.5 V
4.0
5.0
7.0
μA
OC Delay Discharge Current
SS = 2.85 V, ISET = 0.5, ISENSE = 0.5 V
35
50
65
μA
SS Clamp Voltage
−
2.7
2.9
3.1
V
Discharge Voltage
−
0.25
0.3
0.35
V
−
0.1
0.2
V
−
0.08
0.1
0.12
V
−
1.0
2.0
3.0
V
Soft Start Fault Voltage
OV = 2.5 V or UV = 0.85 V
Hiccup Delay Discharge Voltage
Disable
DISABLE Input Threshold
DISABLE Input Resistance
VDISABLE = 0.5 V
50
150
250
kΩ
DISABLE Operation Current, Low VCC
4.7 V < VCC < 10 V
−
−
800
μA
DISABLE Operation Current, High VCC
10 V < VCC < 16 V
−
−
1600
μA
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CS51220
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
16 Lead SO Narrow
PIN SYMBOL
1
VO
2
GND
Ground.
3
VCC
Supply Voltage.
4
VREF
3.3 V reference voltage output.
5
ISET
Voltage at this pin sets pulse−by−pulse overcurrent threshold. When the ISENSE exceeds ISET for a sustained period of
time, a sink current is generated at this pin. Along with external resistors, this current provides a foldback overcurrent
threshold. The sink current is disabled periodically for restart.
6
ISENSE
7
OV
Overvoltage protection monitor.
8
UV
Undervoltage protection monitor.
9
CT
Timing capacitor CT determines oscillator frequency.
10
SYNCI
11
DISABLE
12
FF
13
COMP
14
SS
A capacitor is connected to this pin for Soft Start and soft
hiccup timing.
15
VSD
The voltage at this pin programs the delay of the SYNCO
output in reference to the internal oscillator.
16
SYNCO
FUNCTION
Logic output connecting to external gate driver.
Current sense input for overcurrent protection.
By applying sync pulses to this pin, the IC can be synchronized to frequencies ranging from 25% slower to several
times faster than the internal oscillator frequency.
Disable mode input pin. A voltage greater than 3.0 V turns off
the whole IC.
Feed forward input for PWM ramp. This pin allows external
connection to make the ramp adjustable to the input line.
This pin carries feedback error signal from an external amplifier. Internally, it connects to the PWM controller.
Sync output.
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CS51220
+
−
VCC
UVL Comparator
VREF = 3.3 V
VREF
+
−
+
VREF COMP
DISABLE
X0.94
ISENSE
+
ILIM
−
−+
200 mV
ISET
Ifoldback
COMP
Charge
−
SS
Discharge
OC
Soft
Hiccup
SS low
1.3 V SS
CLK
SS
SS
SS
Clamp
Discharge
SS low
R Q
Fault
Latch
Q
S
SET DOMINANT
−
+
FF
Off
SS
GND
MIN
3.1 V
PWM COMP
−
+
0.3 V
SS
COMP
2.0 V
−
OV
+
OV COMP
−
+
SYNCO
UV COMP
VSD
SYNCI
CT
UV
1.0 V
S
Q
OSC
R
RESET DOMINANT
Figure 2. Block Diagram
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VO
CS51220
APPLICATIONS INFORMATION
THEORY OF OPERATION
VOUT
Feed Forward Voltage Mode Control
COMP
Conventional voltage mode control uses a fixed ramp
signal for pulse width modulation, typically utilizing the
oscillator output as the ramp signal. Since the only feedback
signal comes from the output, this results in inferior line
regulation and audio susceptibility. A significant
improvement in line regulation and line transient response
can be achieved using Feed Forward Voltage Mode Control,
implemented using the CS51220 controller.
The enhancement comes from generating the ramp signal
using a pull−up resistor from the FF pin to the line voltage
and a capacitor to ground. The slope of the ramp then
depends on the line voltage. At the start of each switch cycle,
the capacitor connected to the FF pin is charged through the
resistor connected to the input voltage. Meanwhile, the VO
pin goes high to turn on a power mosfet through an external
gate driver. When the rising FF pin exceeds the COMP input
pin, as driven through the regulation feedback loop, VO goes
low and turns off the external switch. Simultaneously, the FF
capacitor is quickly discharged and set for the next switching
cycle.
Overall, both input and output voltages control the
dynamics of the duty cycle. As illustrated in Figure 3, with
a fixed input voltage the output voltage is regulated solely
by the error amplifier. For example, an elevated output
voltage pulls down the COMP pin through an external error
amplifier. This in turn causes duty cycle to decrease. On the
another hand, if the input voltage varies, the slope of the FF
pin ramp reacts correspondingly and immediately. As an
example shown in Figure 4, when the input voltage goes up,
the slope of the ramp signal increases, which reduces duty
cycle and counteracts the change. For line variations, feed
forward control requires less response from the error
amplifier, which improves the transient speed and DC
regulation.
FF
VIN
CT
VO
Figure 3. Pulse Width Modulated by the Output
Voltage with a Constant Input Voltage
VIN
COMP
FF
VOUT
CT
VO
Figure 4. Pulse Width Modulated by the Input Voltage
with a Constant Output Voltage
The feed forward feature can also be employed for
volt−second clamp, which limits the maximum product of
input voltage and switch on time. This clamp is used in
circuits, such as forward and flyback converters, to prevent
the transformer from saturating. Calculations used in the
design of the volt−second clamp are presented in the Design
Guidelines section on page 12.
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CS51220
VCC Power Up and Fault Conditions
resistance to the ISET pin. However with normal
pulse−by−pulse current limit, the secondary currents during
short circuits may be several times the maximum output
current.
Soft hiccup limit can be obtained by setting the ISET
resistor values for a higher thevenin resistance. During
overcurrent conditions, the ISET level will fold back, after a
short delay, to reduce the pulse by pulse threshold. If desired,
the short circuit current can be chosen to be equal to or even
less than the maximum output current. During soft hiccup
the circuit will periodically disable the foldback and attempt
to restart.
Hard hiccup limit can be obtained by setting the ISET
resistor values so that the ISET pin is held below 200 mV
during foldback. During overcurrent conditions, the ISET
level will fold back, after a short delay, preventing any gate
pulses. When the SS capacitor is completely discharged, the
circuit will attempt restart. This configuration provides the
lowest power dissipation during short outputs.
The circuit functions can be best described by discussing
the block diagram and illustrations of expected waveforms.
Actual waveforms, values and circuit configurations from a
design will be used. The design is from the 5.0 V supply of
a dual synchronized converter.
The current is monitored with a voltage at the ISENSE pin.
The ISENSE signal is slightly attenuated DC shifted by 200 mV,
and is compared with the threshold voltage programmed by the
voltage at the ISET pin. If the current signal reaches the
threshold voltage, the overcurrent comparator resets the VO
latch and terminates the VO pulse. The overcurrent comparator
has a maximum common mode input voltage of 1.8 V.
However, an ISET voltage below 1.0 V is desirable for reducing
the comparator’s propagation delay. During initial turnon of
the power supply, normal pulse−by−pulse overcurrent control
is used to protect the power supply switches. This is
accomplished by comparing the voltage at the ISENSE input to
the voltage at the ISET pin and using this to limit the duty factor
of VO, the gate drive signal. This current limit control is
maintained until the SS voltage reaches 2.9 V.
During power up, an undervoltage lockout comparator
monitors VCC and disables VREF, (which in turn disables the
entire IC), until the VCC voltage reaches its start threshold.
Hysteresis prevents “chattering” caused by the source
impedance of the VCC supply. VREF can also be disabled
using the Disable input pin, which is active high. An internal
pull−down resistor ensures the IC will start up if the Disable
pin is allowed to float. In VCC or Disable lockout mode, the
output stage is held low by the output pull−down resistance.
After VREF turns on, there are three conditions that can
cause fault mode:
1. The 3.3 V VREF is below regulation,
2. The OV pin rises above overvoltage threshold, or
3. The UV pin falls below undervoltage threshold.
Fault detection will cause the VO output to go low and the
SS pin to discharge. The UV and OV inputs are typically
used to monitor the input line voltage. The undervoltage
comparator has a built−in hysteresis voltage, while the
hysteresis for the OV comparator is programmable through
a current sourced from the pin when above the threshold, and
the equivalent external resistance. The fault condition can
only be reset after the SS pin has been completely discharged
and all faults have been removed.
After a fault is removed or upon initial startup, the SS pin
charges at a rate determined by an internal charge current
and an external capacitor. The rising voltage on the SS pin
will override the regulation feedback voltage on the COMP
pin and clamp the duty cycle, helping to reduce any in−rush
current during startup. The duration of the Soft Start is
typically set with a capacitor from 0.01 μF to 0.1 μF.
Overcurrent Protection
The CS51220 uses the “soft hiccup” technique to provide
an adjustable and predictable overcurrent limit. By choosing
external component values the designer can select
pulse−by−pulse current limit, soft hiccup current limit or
hard hiccup limit.
Normal pulse−by−pulse current limit can be obtained by
selecting the ISET resistor values for a low Thevenin
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CS51220
The block diagram of the soft hiccup circuit is shown in
Figure 5. When overcurrent occurs and the SS is above 2.9 V,
the OC pulses set the OC latch. The output of the OC latch
turns on the OC delay discharge current to ramp down the SS
voltage. This SS discharge ramp down is at a rate of 50 μA
while the SS voltage is above 2.8 V. The level between 2.9 V
and 2.8 V is called the hiccup delay discharge voltage. The
time to cross this voltage creates a short delay. This delay is
useful so that a quick transient overcurrent condition can be
controlled and still allow the supply to return immediately to
normal operation. After reaching the hiccup delay discharge
voltage, the SS current is reduced to 5.0 μA and the ISET
foldback current is turned on at 15 μA. It is the ISET
foldback current that adjusts the ISET level to establish a
new lower ISENSE current limit level. See Figure 6 for
details.
The NOOC or SS low (VSS < 0.3 V) signal can reset OC
latch at any time. This event turns off ISET foldback and
allows the recharging of the SS capacitor. Therefore, the IC
allows the power supply to restart periodically or after the
overcurrent condition is cleared. The OC latch can not be set
until the SS capacitor is fully charged.
To implement “hard hiccup” which disables the VO
completely when the SS voltage is ramping down, select a
resistor value greater than 3.3 V/ISET for R1 in Figure 6, and
saturate the internal ISET current source. Since the saturation
voltage is less than the DC shift applied to the ISENSE signal,
the OC comparator output is always high and in turn keeps
the VO low. Figure 7 demonstrates the interactions among
the voltage of SS, ISET and internal signal OC. Figure 8
further describes the specifications associated with the soft
hiccup. The ratio among the charge time, delay time and
discharge time is given at the bottom of Figure 8.
SS
+
2.9 V
−
Peak COMP
OC
S
CLK
Reset
Trig
SS low
N00C
Q
0.3 V
R
OC Latch
One Shot
Foldback
ON
−
2.8 V
2.9 V
2.8 V
SS
SS
Discharge
ISET
+
Delay COMP
Figure 5. The Block Diagram of the Soft
Hiccup Operation
OC
A circuit monitors the OC pulses. If the OC pulses cease
for 50 μs, the NOt−OverCurrent (NOOC) signal is
generated. This NOOC signal resets the OC Latch and
allows the SS capacitor to charge back up allowing the
output to reestablish regulation.
For an equivalent circuit shown in Figure 6, the ISET
current reduces the overcurrent threshold and sets the new
threshold at
VI(SET) + (3.3 * ISET
R1)
50μs
Figure 7. Illustrative Waveforms of the
Soft Hiccup Operation
Charge Voltage
Charge
Current
R2
(R1 ) R2)
Hiccup Delay
Discharge Voltage
OC Delay
Dischage
Current
Dischage
Current
VREF
Discharge Voltage
R1
ISET Pin
26
1
250
Figure 8. The SS Pin Voltage Under Ramp
Up and Overcurrent Condition and
Associated Specifications.
R2
ISET
Figure 6. The Voltage Divider Used at the ISET
Pin Allows the ISET Foldback Current to
Reduce the Overcurrent Threshold
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CS51220
The effect of the soft hiccup can be observed in Figure 9,
which shows the output voltage as load increases. The output
is maintained at the regulation value of 5.0 V until it goes into
current limit. At the point of overcurrent inception (A), the
current limit level changes to a lower level (B). The
switchback to a lower current limit level can be seen as the
bottom curve in Figure 9.
The middle trace is a digitizing ‘scope trace of the current
sense line. The scope interprets the voltages as an average
voltage. This voltage is actually a narrow duty cycle peak
voltage representing the peak current level in the switching
transistor. The actual peak voltages can be seen in the Figure
11. The peaks are 0.85 V at full load, reducing to 0.6 V peak
at the reduced short circuit level. The 1.1 V peak is the full
short circuit current while SS ramps back up. The 0.32 V level
is the normal load resistance, while ISET is still on. The 1.0 V
surge is created by ramp up into a normal 5.0 A load and
followed by the 0.85 V at normal load.
6
A
Output Voltage (V)
5
Peak Detect Setting
4
3
2
1
0
B
0
2
4
6
Load Current (A)
Figure 9. Overcurrent In a 5.0 V Output
Converter Using Soft Hiccup
A typical overload scenario is shown in Figure 10. The top
trace is the voltage on the Soft Start (SS) pin. The initial high
discharge rate can be seen transitioning to a 40 ms discharge
period. During this period the ISET establishes a lower
current limit level. The bottom trace shows the output
current. The initial current spike is the output capacitors
discharging. The next level around 4.0 A is the short circuit
current level set by the ISET current. The output then turns
off allowing the current to reduce to a level that does not
cause overcurrent pulses. This releases the SS pin to ramp
back up. During ramp up, the output is still shorted as noted
by the 8.0 A current level. When SS reaches the 2.9 V level,
the short is again recognized and ISET is turned back on
shifting the short circuit current level.
Figure 11. Over−Load Current and
ISENSE Voltage
Oscillator and Synchronization
The switching frequency is programmable through a
capacitor connected to the CT pin. When the CT pin voltage
reaches peak voltage (2.0 V), the internal discharge current
discharges the CT capacitor and VO stays low. When the CT
voltage declines to valley voltage (0.9 V), the current source
toggles to charge current and ramps up the CT pin. This starts
a new switching cycle. The duty cycle of the oscillator
determines the maximum PWM duty cycle.
The switching frequency of the IC can be synchronized to
an external frequency presented to the SYNCI pin. When
pulses with amplitude over SYNCI input threshold are
detected, the CT pin immediately ramps down the external
capacitor and the VO pin is forced low. A new switching
cycle begins when the CT pin reaches valley voltage. During
synchronization, the oscillator charge current is reduced by
80 μA, while discharge current is increased by 80 μA. This
effectively slows down the internal oscillator to avoid any
race condition with the sync frequency. As a result, the sync
frequency can be either higher or lower than the internal
oscillator frequency. CS51220 is able to synchronize up to
500 kHz and down to 25% below CT frequency. The
maximum duty cycle clamp is raised to 92% in
synchronization mode. The original oscillator frequency is
restored upon the removal of sync pulses.
Figure 10. Over−Load Current and
Soft Start Waveforms
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11
CS51220
The desired effect on the input ripple is illustrated in
Figure 14. This is the input current for two power converters
operating from a 36 V line.
Figure 12. Synchronization Input Timing
Figure 12 shows the sync input from one CS51220 into
another. The delay between receiving the sync input and the
start of the next switching cycle is 423 ns. This delay must
be taken into account when establishing the total delay
between two regulators.
The SYNCO pin provides outgoing synchronization pulses
whose delay can be programmed by setting the voltage on the
VSD pin. The feature allows two converters to run at
interleaved phases. This implementation significantly
reduces the input ripple, and thus the number of input
capacitors. The phase delay is achieved by turning on
SYNCO output only after the CT pin voltage reaches the VSD
voltage. Therefore, the phase delay varies linearly with the
VSD voltage. The SYNCO output is reset during the falling
edge of the CT pin. For minimum phase delay (~ 240 ns), tie
the VSD pin to the ground. To entirely disable the SYNCO
output, connect the VSD pin to VREF.
The waveform in Figure 13 shows the CT ramp crossing
the VSD voltage set at 1.41 V.
Figure 14. Input Current Ripple with
Different Overlap Conditions
The top waveform in Figure 14 is the input current with
the two supplies operating out of phase. The next down
shows the same supplies but with both conduction times
occurring simultaneously. The greatly increased ripple
current can be observed. The last two waveforms are the two
converters shown individually when operating out of phase.
DESIGN GUIDELINES
Program Volt−Second Clamp
Feed forward voltage mode control provides the
volt−second clamp which clamps the product of the line
voltage and switch on time. For the circuit shown in Figure 15,
the charging current of the CFF can be considered as a constant
current equal to VIN/RFF , provided VIN is much greater than
the FF pin voltage. Then the volt−second clamp provided by
CS51220 is given by
VINTON(MAX) + 1.0RFFCFF
VIN
RFF
FF Pin
CFF
Figure 13. Synchronization Output Timing
Figure 15. An RC Network Provides Both
Volt−Second Clamp and Feed Forward Control
The delay from the point of crossing to the output of the
sync signal is 240 ns. The time for the sync out voltage is
measured at the +2.0 V level, which is the level that triggers
the next CS51220.
Select the time constant of the FF pin RC network to
provide desirable volt−second clamp.
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12
CS51220
Program Oscillator Frequency
Synchronized Dual Converters with Soft Hiccup and
Feed Forward
CS51220 requires an external capacitor to program the
oscillator
frequency.
The
internally
trimmed
charge/discharge current determines the maximum duty
cycle. The capacitor for a required switching frequency fS
can be calculated by:
The circuits shown in Figures 17 and 18 illustrate typical
applications for a dual output supply using independent but
synchronized converters. These circuits demonstrate the use
of the soft hiccup, feed forward, volt−second control and
synchronization features of the CS51220.
In Figure 17, the feed forward circuit has a volt−second
constant of 82 V/μs. This would limit the duty factor to 0.51
at 48 V input. With a turns ratio of 4:1 on the power
transformer and 48 V input, a duty factor of 0.46 is required
for 5.0 V output. This converter serves as the master
synchronization generator. The voltage on the VSD pin
establishes the delay as it is compared to the ramp generated
on the CT pin.
Adjustable synchronization allows the conduction time
for the two converters to be adjusted so that they are not on
at the same time. This greatly reduces the ripple current from
the 48 V source.
In Figure 18, the feed forward circuit has a volt−second
constant of 63 V/μs. This would limit the duty factor to 0.39
at 48 V input. With a turns ratio of 4:1 on the power
transformer and 48 V input, a duty factor of 0.33 is required
for 3.3V output.
CT + 13400 * 95
fS
where:
CT = Timing capacitance is in pF
fS = Switching frequency is in kHz
Figure 16 shows the relationship of CT and fS.
600
550
Frequency (kHz)
500
450
400
350
300
250
200
150
100
100
200
300
400
500
600
CT (pF)
Figure 16. Operating Frequency
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13
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14
C3
0.1 μF
VIN
GND
R21
511 k
R9
11.8 k
R8
15 k
C4
390 pF
Figure 17. Additional Application Diagram, 5.0 V Output Converter
Used As Sync Master for the Dual Converter
2.0 k
R14
C35
1000 pF
C5
470 pF
R6
174 k
C1
1.5 μF
100 V
36−72 V
C38
1000 pF
R4
150 k
R7
511 k
R5
64.9 k
R3
7.5 k
R2
10 k
C37
0.1 μF
500 V
C16
0.2 μF
100 V
1.0 μH
L2
VCC
SS
VO
GND
ISENSE
SYNCI
SYNCO
U1
0.1 μF
C2
R22
10
C18
1000 pF
SYNC IN
SYNC
ENABLE1
COMP DISABLE
UV
OV
ISET
CT
VSD
VREF
FF
D4 9.1 V
MMSZ5239BT1
D3 15 V
MMSZ5245BT1
Q1
MMFT1N10E
R1
100 k
BST1
CS51220
C7
0.1 μF
TP4
100 pF
C6
R11
100
D2
NC
GND
INA
VDD
R12 R10
36
10 k
D1
U4
U2
MOC213
R16
182
OUT
GND
OUT
VDD
TP2
70:1
T1
MMSD4148T1
MMSD4148T1
VIN
NCP4414
TP1
R17
1.0 K
R48
3.92 k
TP3
Q2
IRF634S
20:5
T2
R13
10
U3
TLV431ASNT1
1.25 V
0.022 μF
C13
C14
100 pF
10 k
R18
6.8 μH
L1
D5A
MBRB2535CTL
C10
100 pF
200 V
C12
680 pF
R15
10
D5B
MBRB2535CTL
10
R23
R20
13.3 k
1000 pF
C36
R19
40.2 k
C9
330 μF
C11
330 μF
VORTN
VOUT
5.0 V @
5.0 A
CS51220
15
GND
VIN
C19
0.1 μF
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R31
511 k
R32
11.8 k
R30
15 k
C39
1000 pF
R27
150 k
R29
511 k
R28
64.9 k
R26
5.11 k
R25
10 k
C31
470 pF
R24
137 k
Figure 18. Additional Application Diagram, 3.3 V Output
Converter Synchronized to the 5.0 V Converter
2.0 k
R33
C33
1000 pF
C20
390 pF
36−72 V
C32
1.5 μF
100 V
SYNCI
GND
SS
VO
VCC
ISENSE
0.1 μF
C22
R37
10
TP8
R49
3.3 k
SYNC
SYNC OUT
ENABLE2
OV
SYNCO
COMP DISABLE
UV
VSD
ISET
CT
FF
VREF
U5
CS51220
BST1
R48
220
C24
1.0 μF
100 pF
C23
R34
100
C21
0.1 μF
GND
NC
VDD
INA
R35 R36
36
10 k
D7
MMSD4148T1
U4
U6
MOC213
R41
182
GND
OUT
VDD
OUT
TP6
70:1
T3
MMSD4148T1
D6
NCP4414
TP5
R42
1.0 K
R47
2.21 k
TP7
Q3
MTB20N20E
20:5
T4
R40
10
C29
U7
TLV431ASNT1
100 pF
0.022 μF
C30
2.21 k
R43
6.8 μH
L3
D8A
MBRB2535CTL
C28
100 pF
200 V
C25
680 pF
R39
10
D8B
MBRB2535CTL
10
R38
R45
24.3 k
R44
40.2 k
C27
330 μF
C26
330 μF
VORTN
VOUT
3.3 V @
5.0 A
CS51220
CS51220
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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