IDT IDT74FST163232PV 16-bit synchronous 2:1 mux/demux switch Datasheet

16-BIT SYNCHRONOUS
2:1 MUX/DEMUX SWITCH
IDT74FST163232
ADVANCE INFORMATION
Integrated Device Technology, Inc.
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163232 provides three 16-bit TTL- compatible
ports that support 2:1 multiplexing. The S0,1 pins control mux
select and switch enable/disable. The S0,1 inputs are synchronous and clocked on the rising edge of CLK when CLKEN
is low.
Port A can be connected to port B1 or port B2 or both ports
B1 and B2.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 4Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163232 belong to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
their own while providing a low resistance path for an external
FUNCTIONAL BLOCK DIAGRAM
CLKEN
CLK
D
S0
CE
CLK
D
S1
1 of 16 Channels
CE
1A
CLK
1 B1
1 B2
PIN DESCRIPTION
3511 drw 01
Pin Names
A
I/O
I/O
Description
Bus A
B1, B2
I/O
Buses B1, B2
S0,1
I
Control Pins
CLK
I
CLKEN
I
Clock Input. Clocks S0,1 on
Rising Edge
Clock Enable Input
3511 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 1997
1997 Integrated Device Technology, Inc.
DSC-3511/2
1
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2) Terminal Voltage with Respect
to GND
TSTG
Storage Temperature
1A
1
56
1B1
2B1
2
55
1B2
2B2
3
54
2A
3A
4
53
3B1
4B1
5
52
3B2
4B2
6
51
4A
5A
7
50
5B1
6B1
8
49
5B2
6B2
9
48
6A
7A
10
47
7B1
8B1
11
46
7B2
CAPACITANCE(1)
8B2
12
45
8A
Symbol
GND
13
44
GND
Vcc
14
SO56-1
SO56-2
SO56-3
43
VCC
I OUT
CIN
Control Input Capacitance
CI/O
Switch Input/Output
Capacitance
16
41
9B2
10 B2
17
40
10A
11A
18
39
11B1
12 B1
19
38
11B2
S1
X
S0
X
CLK
X
12 B2
20
37
12A
L
L
L
H
H
H
22
35
13B2
14 B2
23
34
14A
15A
24
33
15 B1
16 B1
25
32
15B2
16 B2
26
31
16A
CLK
27
30
S0
CLKEN
28
29
S1
mA
4
pF
Switch Off
pF
3511 tbl 03
NOTES:
1. Capacitance is characterized but not tested
2. TA = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V
10 B1
14 B1
128
Conditions(2) Typ. Unit
Parameter
9B1
13B1
°C
2. VCC, Control and Switch terminals.
42
36
–65 to +150
3511 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condiitions for extended
periods may affect reliability.
15
21
Unit
V
Maximum Continuous Channel
Current
9A
13A
Max.
–0.5 to +7.0
FUNCTION TABLE
CLKEN
H
Description
Last state
↑
L
Disconnect
↑
L
A to B1 and A to B2
L
↑
L
A to B1 or B1 to A
H
↑
L
A to B2 or B2 to A
3511 tbl 04
SSOP/
TSSOP/TVSOP
TOP VIEW
3511 drw 02
2
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Parameter
Input HIGH Voltage
Test Conditions(1)
Guaranteed Logic HIGH for Control Inputs
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Voltage
Guaranteed Logic LOW for Control Inputs
—
—
0.8
V
II H
Input HIGH Current
VCC = Max.
VI = VCC
—
—
±1
µA
II L
Input LOW Voltage
VI = GND
—
—
±1
IOZH
High Impedance Output Current
VO = VCC
—
—
±1
IOZL
(3-State Output pins)
VO = GND
—
—
±1
IOS
Short Circuit Current
VCC = Max., VO = GND(3)
—
300
—
mA
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
VCC = Min. VIN = 0.0V
—
4
7
Ω
—
4
7
Ω
—
6
15
Ω
µA
Symbol
VIH
RON
Switch On
Resistance(4)
VCC = Max.
µA
ION = 64mA
VCC = Min. VIN = 0.0V
ION = 32mA
VCC = Min. VIN = 2.4V
ION = 15mA
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 4.5V
—
—
±1
ICC
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
0.1
3
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Measured by voltage drop between ports at indicated current through the switch.
3
µA
3511 tbl 05
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
Enable Pin Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
CLK Pin Toggling
(16 Switches Toggling)
fi = 10MHz
50% Duty Cycle
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
VIN = VCC
VIN = GND
—
30
40
µA/
MHz/
Switch
VIN = VCC
VIN = GND
—
4.8
6.4
mA
VIN = 3.4
VIN = GND
—
5.1
7.2
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fiN)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
N = Number of Switches Toggling at fi
All currents are in milliamps and all frequencies are in megahertz.
3511 tbl 06
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
tPLH
tPHL
tCEWS
tPZH
tPZL
tPHZ
tPLZ
|QCI|
Description
Data Propagation Delay
A to B, B to A(3,4)
Clock Enable Set-Up Time
CLKEN to CLK Low-to-High
Clock Enable Hold Time
CLKEN to CLK Low-to-High
Switch Multiplex Delay
CLK to A, B
Switch Turn on Delay
CLK to A, B
Switch Turn off Delay
CLK to A, B
Charge Injection, Typical(5,7)
|QDCI|
Differential Charge Injection, Typical (6,7)
tCENH
tBX
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
—
Typ.
—
Max.
0.25
Unit
ns
—
—
ns
—
—
ns
1.5
—
6.5
ns
1.5
—
6.5
ns
1.5
—
7
ns
—
1.5
—
pC
—
0.5
—
3511 tbl 07
NOTES:
1. See test circuit and waveforms.
2. Minimum limits guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant
for the switch alone is of the order of 2.5ns for 50pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals,
it adds very little propagation delay to the system. Propagation delay on the bus switch when used in a system is determined by the driving circuit on the
driving side of the switch and its interaction with the load on the driven side.
5. Measured at switch turn off, load = 50 pF in parallel with 10 MΩ scope probe, VIN = 0.0 volts.
6. Measured at switch turn off through bus multiplexer, (e.g.- A to B1 = >A to B2), load = 50 pF in parallel with 10 MΩ scope probe, VIN at A = 0.0 volts. Charge
injection is reduced because the injection from the turn off of the A to B1 switch is compensated by the turn on of the A to B2 switch.
7. Characterized parameter. Not 100% tested.
4
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
SWITCH POSITION
500Ω
Pulse
Generator
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Test
7.0V
Open
All Other Tests
D.U.T.
50pF
RT
3511 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
3511 lnk 03
PULSE WIDTH
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
3511 lnk 05
3511 lnk 04
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
3511 lnk 06
SWITCH
OPEN
0V
tPLZ
tPZL
VOH
1.5V
VOL
3.5V
0.3V
VOL
tPHZ
0.3V
VOH
1.5V
0V
0V
3511 lnk 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
FST 16 XX
Temp. Range
Device Type
X
Package
PV
PA
PF
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
163232
16-Bit Synchronous 2:1 Mux
74
–40°C to +85°C
3511 ldrw 08
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090
Telephone: (408) 727-6116
6
FAX 408-492-8674
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