IDT IDT70V07S High-speed 3.3v 32k x 8 dual-port static ram Datasheet

HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industral: 25ns (max.)
Low-power operation
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
Standby: 660µW (typ.)
Interrupt Flag
◆
◆
◆
◆
◆
◆
◆
IDT70V07S/L
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
,
(1,2)
(1,2)
BUSYL
A14L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
15
CEL
OEL
R/WL
SEML
(2)
INTL
Address
Decoder
A14R
A0R
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR(2)
2943 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
OCTOBER 2004
1
©2004 Integrated Device Technology, Inc.
DSC 2943/6
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 300mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA and PLCC and
a 80-pin thin quad flatpack (TQFP).
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bitor-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
A14L
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
Pin Configurations(1,2,3)
10/25/01
INDEX
10
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
9
8
7
6
5
4
15
16
17
18
19
3
2
IDT70V07J
J68-1(4)
55
54
53
68-Pin PLCC
Top View(5)
52
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O7R
N/C
OER
R/WR
SEMR
CER
A 14R
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
2943 drw 02
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
10/25/01
INDEX
N/C
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
N/C
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
N/C
A14L
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
N/C
N/C
Pin Configurations(1,2,3) (con't.)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
53
8
IDT70V07PF
(4)
9
PN80-1
52
10
51
11
50
12
49
80-Pin TQFP
(5)
13
48
Top View
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
I/O7R
N/C
OER
R/WR
SEMR
CER
N/C
A14R
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
N/C
N/C
2943 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
10/25/01
51
11
A5L
50
A4L
48
A2L
46
44
42
A0L BUSYL M/S
40
38
INTR A1R
36
A3R
49
A3L
47
A1L
45
43
41
39
37
INTL GND BUSYR A0R A2R
35
A4R
34
A5R
53
A7L
52
10
55
A9L
54
09
A8L
32
A7R
33
A6R
08
57
56
A11L A10L
30
A9R
31
A8R
07
59
58
VCC A12L
28
A11R
29
A10R
26
GND
27
A12R
61
06
A6L
IDT70V07G
G68-1(4)
60
A14L
68-Pin PGA
Top View(5)
A13L
05
63
62
SEML CEL
04
65
64
OEL R/WL
22
23
SEMR CER
03
67
66
I/O0L N/C
20
OER
02
1
3
68
I/O1L I/O2L I/O4L
2
4
I/O3L I/O5L
01
A
B
C
24
25
A14R A13R
21
R/WR
5
7
9
11
13
15
GND I/O7L GND I/O1R VCC I/O 4R
18
19
I/O7R
N/C
6
17
I/O6R
8
I/O 6L
D
10
12
14
16
VCC I/O0R I/O2R I/O3R I/O 5R
E
F
G
H
J
K
,
L
INDEX
2943 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power (3.3V)
GND
Ground (0V)
2943 tbl 01
4
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
Mode
Read Memory
Outputs Disabled
2943 tbl 02
NOTE:
1. A0L — A14L ≠ A0R — A14R
Truth Table II: Semaphore Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
H
H
L
L
DATAOUT
Read Data in Semaphore Flag
H
↑
X
L
DATAIN
Write I/O0 into Semaphore Flag
L
____
L
X
X
Mode
Not Allowed
2943 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
Maximum Operating Temperature
and Supply Voltage(1)
Grade
VTERM(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
StorageTemperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT
DC Output Current
50
Commercial
Industrial
COUT(2)
Output Capacitance
0V
3.3V + 0.3
-40OC to +85OC
0V
3.3V + 0.3
Recommended DC Operating
Conditions(2)
Symbol
(TA = +25°C, f = 1.0MHz) TQFP Only
Input Capacitance
0OC to +70OC
mA
Capacitance(1)
CIN
Vcc
2943 tbl 05
2943 tbl 04
Parameter
GND
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Symbol
Ambient Temperature
Conditions
Max.
Unit
V IN = 0V
9
pF
VOUT = 0V
10
Parameter
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
V
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
2.0
____
V CC+0.3(2)
VIL
Input Low Voltage
-0.3(1)
____
0.8
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
pF
2943 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
5
V
2943 tbl 06
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V07S
Symbol
Parameter
Max.
Min.
Max.
Unit
VCC = 3.6V, VIN = 0V to V CC
___
10
___
5
µA
Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
|ILI|
(1)
Input Leakage Current
|ILO|
Test Conditions
Min.
70V07L
V
2943 tbl 08
NOTE:
1. At VCC < 2.0V, input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V07X25
Com'l
& Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
CE = VIL, Outputs Disabled
SEM = VIL
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
Version
70V07X35
Com'l Only
70V07X55
Com'l Only
Typ.(2)
Max.
Typ. (2)
Max.
Typ.(2)
Max.
Unit
170
140
90
90
140
120
90
90
140
120
mA
COM'L
S
L
100
100
IND
S
L
____
____
____
____
____
____
100
185
____
____
____
____
COM'L
S
L
14
12
30
24
12
10
30
24
12
10
30
24
IND
S
L
____
____
____
____
____
____
12
50
____
____
____
____
COM'L
S
L
50
50
95
85
45
45
87
75
45
45
87
75
IND
S
L
____
____
____
____
____
____
50
105
____
____
____
____
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
IND
S
L
____
____
____
____
____
____
0.2
3
____
____
____
____
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
S
L
60
60
90
80
55
55
85
74
55
55
85
74
IND
S
L
____
____
____
____
____
____
60
90
____
____
____
____
mA
mA
mA
mA
2943 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
3.3V
Input Pulse Levels
3.3V
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
590Ω
DATAOUT
BUSY
INT
DATAOUT
30pF
435Ω
5pF*
435Ω
Figures 1 and 2
2943 tbl 10
2943 drw 06
2943 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ , tHZ, tWZ, tOW)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V07X25
Com'l
& Ind
Symbol
Parameter
70V07X35
Com'l Only
70V07X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
25
____
35
____
55
____
ns
Address Access Time
____
READ CYCLE
tRC
25
____
35
____
55
ns
tACE
Chip Enable Access Time
(3)
____
25
____
35
____
55
ns
tAOE
Output Enable Access Time
____
15
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time (1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time (1,2)
____
15
____
20
____
25
ns
tPU
Chip Enable to Power Up Time (2)
0
____
0
____
0
____
ns
____
25
____
35
____
50
ns
____
15
____
15
____
ns
35
____
45
____
65
tAA
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
Semaphore Address Access Time
____
tSAA
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
ISB
2943 drw 07
7
ns
2943 tbl 11
,
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
tAA(4)
(4)
tACE
CE
tAOE
(4)
OE
R/W
tLZ
(1)
tOH
(4)
DATAOUT
VALID DATA
tHZ
(2)
BUSYOUT
(3,4)
2943 drw 08
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE , tAA or tBDD .
5. SEM = VIH.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V07X25
Com'l
& Ind
Symbol
Parameter
70V07X35
Com'l Only
70V07X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
25
____
35
____
55
____
ns
20
____
30
____
45
____
ns
20
____
30
____
45
____
ns
0
____
0
____
0
____
ns
20
____
25
____
40
____
ns
0
____
0
____
0
____
ns
15
____
20
____
30
____
ns
____
15
____
20
____
25
ns
0
____
0
____
0
____
ns
____
15
____
20
____
25
ns
0
____
0
____
0
____
ns
5
____
5
____
5
____
ns
5
____
5
____
5
____
ns
WRITE CYCLE
tWC
tEW
tAW
tAS
tWP
tWR
tDW
tHZ
tDH
tWZ
Write Cycle Time
Chip Enable to End-of-Write
(3)
Address Valid to End-of-Write
Address Set-up Time
(3)
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
(1,2)
(4)
(1,2)
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
tSPS
SEM Flag Contention Window
(1,2,4)
2943 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
8
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ (7)
OE
tAW
(9)
tHZ (7)
CE or SEM
tAS (6)
tWR(3)
tWP (2)
R/W
tLZ
DATAOUT
tWZ (7)
tOW
(4)
(4)
tDW
tDH
DATAIN
,
2943 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
CE or SEM
tAS (6)
(3)
tEW (2)
tWR
R/W
tDW
tDH
DATAIN
2943 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or t WP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
9
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tWR
tACE
tEW
SEM
tDW
DATA0
tSOP
DATAOUT
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
2943 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
2943 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
10
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V07X25
Com'l
& Ind
Symbol
Parameter
70V07X35
Com'l Only
70V07X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address
____
25
____
35
____
45
ns
tBDA
BUSY Disable Time from Address
____
25
____
35
____
45
ns
tBAC
BUSY Access Time from Chip Enable
____
25
____
35
____
45
ns
tBDC
BUSY Disable Time from Chip Enable
____
25
____
35
____
45
ns
5
____
5
____
5
____
ns
____
35
____
40
____
50
ns
0
____
0
____
0
____
ns
20
____
25
____
25
____
ns
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data
(2)
(3)
BUSY TIMING (M/S - VIL)
tWB
BUSY Input to Write (4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
55
____
65
____
85
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
50
____
60
____
80
ns
2943 tbl 13
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
DATAIN "A"
tDH
VALID
tAPS
(1)
ADDR"B"
MATCH
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
11
2943 drw 13
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB
BUSY"B"
tWH
R/W"B"
(1)
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on Port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
2943 drw 14
Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
2943 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1)
ADDR"A"
ADDRESS "N"
tAPS
ADDR"B"
(2)
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2943 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from Port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
12
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V07X25
Com'l
& Ind
Symbol
Parameter
70V07X35
Com'l Only
70V07X55
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
25
____
30
____
40
ns
tINR
Interrupt Reset Time
____
30
____
35
____
45
ns
2043 tbl 14
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS
ADDR"A"
tAS
(3)
(2)
tWR
(4)
CE"A"
R/W"A"
tINS (3)
INT"B"
2943 drw 17
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
(2)
tAS (3)
CE"B"
OE"B"
tINR (3)
INT"B"
2943 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
13
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
CEL
R/WL
L
OEL
L
X
X
7FFF
X
X
X
X
X
L
INTL
A14L-A0L
X
X
X
Right Port
L
X
A14R-A0R
X
INTR
Function
(2)
Set Right INTR Flag
(3)
X
L
X
L
L
7FFF
H
Reset Right INTR Flag
L
L
X
7FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
L
7FFE
X
OER
(3)
X
X
CER
R/WR
H
2943 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
A0L -A14L
A0R-A14R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2943 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V07 are pushpull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSY L or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
2943 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
14
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V07 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
The IDT70V07 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V07 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Width Expansion with BUSY Logic
Master/Slave Arrays
Interrupts
When expanding an IDT70V07 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V07 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
MASTER
Dual Port
RAM
BUSYL
BUSYL
MASTER
Dual Port
RAM
BUSYL
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
DECODER
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFE (HEX), where a write is defined as CER = R/WR = VIL per Truth
Table III. The left port clears the interrupt through access of address
location 7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 7FFF (HEX) and to clear the interrupt flag (INTR),
the right port must read the memory 7FFF location 7FFF. The
message (8 bits) at 7FFE or 7FFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 7FFE and 7FFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the
interrupt operation.
CE
BUSYR
Semaphores
BUSYR
,
2943 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V07 RAMs.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The busy pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
15
The IDT70V07 is an extremely fast Dual-Port 32K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port SRAM or any other
shared resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic powerdown feature controlled by CE, the Dual-Port SRAM enable, and SEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
I where CE and SEM are both HIGH.
Systems which can best use the IDT70V07 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V07's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V07 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
WRITE
D
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
Figure 4. IDT70V07 Semaphore Logic
How the Semaphore Flags Work
2943 drw 20
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side's semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V07 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same side,
the flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
16
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Semaphore 1. If it succeeded in gaining control, it would lock out the
left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 16K blocks of Dual-Port SRAM with each
other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V07’s Dual-Port SRAM. Say the
32K x 8 SRAM was to be divided into two 16K x 8 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 16K of Dual-Port
SRAM, the processor on the left port could write and then read a zero
in to Semaphore 0. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 16K. Meanwhile the right processor was attempting
to gain control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try and gain
control of the second 16K section by writing, then reading a zero into
17
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
25
35
55
Commercial & Industrial
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
,
Speed in nanoseconds
70V07 256K (32K x 8) 3.3V Dual-Port RAM
2943 drw 21
NOTE:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
Datasheet Document History:
3/24/99:
6/9/99:
10/14/04:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changed drawing formatt
Removed Preliminary status
Page 1 Added I-temp offering
Page 4 Updated Capacitance table
Increased Storage Temp parameter in Absolute Maximum Rating table
Added Junction Temp to Absolute Maximum Rating table
Page 4, 5, 6, 7 & 10 Removed I-temp footnote from tables
Page 5 Added I-temp 25ns power numbers to the DC Electrical Characteristics table
DC Electrical parameters–changed wording from "open" to "disabled"
Page 5 & 6 Changed transition measurement from ±200mV to 0mV in footnotes
Page 6, 7, 10, & 12 Added I-temp to all AC Electrical Characteristics table
Page 8 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Page 1 & 17 Replaced old IDTTM logo with new IDTTM logo
Page 17 Added I-temp to 25ns speed grade in ordering information
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18
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