Maxim MAX1514ETP Tft-lcd power-supply controller Datasheet

19-3047; Rev 0; 10/03
KIT
ATION
EVALU
E
L
B
A
AVAIL
TFT-LCD Power-Supply Controllers
Features
The MAX1513/MAX1514 provide complete power-supply solutions for active-matrix thin-film transistor (TFT)
liquid-crystal displays (LCDs). Both devices include a
high-performance step-up regulator controller, three linear-regulator controllers, and an adjustable delay block
for startup sequencing. The MAX1513 includes an
additional linear-regulator controller and a high-performance buffer amplifier. The MAX1513/MAX1514 can
operate from 2.7V to 5.5V input supplies and provide
overload protection with timer delay latch on all the regulated outputs.
The step-up regulator controller drives an external Nchannel MOSFET to generate the regulated supply voltage for the panel source-driver ICs. Its current-mode
control architecture provides fast transient response to
pulsed loads. The high switching frequency (up to
1.5MHz) allows the use of ultra-small inductors and
ceramic capacitors while achieving efficiencies over 85%
using lossless current sensing. The internal soft-start limits the input surge current during startup.
♦ 2.7V to 5.5V Input Supply Range
♦ Input-Supply Undervoltage Lockout
♦ Current-Mode Step-Up Controller
Fast Transient Response to Pulsed Load
High Efficiency
Lossless Current Sensing
430kHz/750kHz/1.5MHz Switching Frequency
♦ Linear-Regulator Controllers for VGON, VGOFF
♦ Linear-Regulator Controller for Logic Supply
♦ High-Performance Buffer Amplifier (MAX1513 Only)
♦ Additional Linear-Regulator Controller
(MAX1513 Only)
♦ Power-Up Sequence and VGON Delay Control
♦ VMAIN, VGON, VGOFF, VGAMMA Shutdown Control
♦ Timer-Delay Fault Latch for All Outputs
♦ Thermal-Overload Protection
The gate-on and gate-off linear-regulator controllers of
the MAX1513/MAX1514 provide regulated TFT gate-on
and gate-off supplies. The gate-on supply is activated
after an adjustable delay following the step-up regulator.
The logic linear-regulator controller can be used to create a low-voltage logic supply. The gamma linear-regulator controller of the MAX1513 can be used to generate a
gamma-correction reference supply or another generalpurpose supply rail. The MAX1513’s high-performance
buffer amplifier can drive the LCD backplane (VCOM)
or the gamma-correction divider string.
The MAX1513/MAX1514 are available in 4mm ✕ 4mm
20-pin thin QFN packages with a maximum thickness of
0.8mm, suitable for ultra-thin LCD panel design.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1513ETP
-40°C to +85°C
20 Thin QFN 4mm x 4mm
MAX1514ETP
-40°C to +85°C
20 Thin QFN 4mm x 4mm
Minimal Operating Circuit
VIN
CS+
IN
VMAIN
CSSDFR
GATE
GND
DEL
FB
Applications
MAX1513
MAX1514
Notebook Computer Displays
DRVL
VLOGIC
LCD Monitors and TVs
FBL
DRVP
Automotive Displays
FBP
VMAIN
VGON
DRVG
VGAMMA
FBG
SUPB
DRVN
Pin Configuration appears at end of data sheet.
TO VCOM
FBPB
FBN
OUTB
REF
VGOFF
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1513/MAX1514
General Description
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
ABSOLUTE MAXIMUM RATINGS
FB, FBP, FBN, FBG, FBL, IN, CS+,
CS-, SDFR to GND ...............................................-0.3V to +6V
DEL, GATE, REF to GND .............................-0.3V to (VIN + 0.3V)
SUPB to GND .........................................................-0.3V to +14V
OUTB, FBPB to GND ..............................-0.3V to (VSUPB + 0.3V)
DRVP, DRVG, DRVL to GND ..................................-0.3V to +30V
DRVN to GND .....................................(VIN - 28V) to (VIN + 0.3V)
OUTB Continuous Output Current ....................................±75mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TQFN (derate 16.9mW/°C above +70°C) .......1349mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 3V, VSUPB = 10V, SDFR = IN, CREF = 0.22µF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless
otherwise noted.)
PARAMETER
IN Supply Range
IN Undervoltage-Lockout
Threshold
IN Quiescent Current
SYMBOL
CONDITIONS
VIN
VUVLO
IIN
MIN
TYP
2.7
350mV typical hysteresis
MAX
UNITS
5.5
V
VIN rising
2.5
2.7
2.9
VIN falling
2.2
2.35
2.5
V
VFB = VFBP = VFBL = VFBG = 1.5V, VFBN = 0
1.25
mA
IN Shutdown Current
VSDFR = 0, VFBL = 1.5V
150
µA
REF Output Voltage
-2µA < IREF < 100µA, 2.7V < VIN < 5.5V
1.269
V
1.231
Temperature rising
Thermal Shutdown
1.250
+160
Hysteresis
°C
15
Duration to Trigger Fault Latch
43.6
ms
MAIN STEP-UP CONTROLLER
Operating Frequency
fOSC
SDFR = IN
1.275
1.500
1.725
SDFR = REF
0.60
0.75
0.90
MHz
SDFR = unconnected
Oscillator Maximum Duty Cycle
FB Regulation Voltage
VFB
0.43
80
85
90
%
V
VCS+ - VCS- = 0
1.237
1.25
1.263
FB Fault Trip Level
VFB falling
0.96
1.00
1.04
FB Load Regulation
0 < (VCS+ - VCS-) < 50mV
FB Line Regulation
VIN = 2.7V to 5.5V
FB Input Bias Current
VFB = 1.5V
CS+ Input Current
2.2V < VCS+ < 6V
CS- Input Current
2.2V < VCS- < 6V
Current-Limit Threshold
VCS+ - VCS-, 2.2V < VCS+ < 6V
Gate-Drive Output
High or low
Soft-Start Period
-1
0.1
-100
-1
100
tSS
Soft-Start Step Size
V
%
0.2
%/V
+100
nA
90
µA
+1
µA
125
150
mV
3
5
Ω
2.7
ms
VREF / 128
V
GATE-ON LINEAR-REGULATOR CONTROLLER (REG P)
FBP Regulation Voltage
IDRVP = 50µA
1.225
1.250
1.275
FBP Fault Trip Level
VFBP falling
0.96
1.00
1.04
V
FBP Input Bias Current
VFBP = 1.5V
-250
+250
nA
2
VFBP
_______________________________________________________________________________________
V
TFT-LCD Power-Supply Controllers
(Circuit of Figure 1, VIN = 3V, VSUPB = 10V, SDFR = IN, CREF = 0.22µF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless
otherwise noted.)
PARAMETER
SYMBOL
FBP Effective Load-Regulation
Error (Transconductance)
DRVP Off-Leakage Current
VFBP = 1.1V, VDRVP = 10V
MAX
UNITS
-1.5
-2
%
8
1
VFBP = 1.5V, VDRVP = 28V
DEL Charge Current
During startup, VDEL = 1.0V
VTH(DEL)
DEL Discharge Switch
On-Resistance
Soft-Start Period
TYP
IDRVP = 50µA, 2.7V < VIN < 5.5V
IDRVP
DEL Turn-On Threshold
MIN
VDRVP = 10V, IDRVP = 25µA to 500µA
FBP Line (IN)-Regulation Error
DRVP Sink Current
CONDITIONS
mV
mA
0.15
10
µA
4
5
6
µA
1.19
1.25
1.31
V
VIN = 3.0V, VFB = 0.8V
tSS
Soft-Start Step Size
15
Ω
2.7
ms
VREF / 128
V
GAMMA LINEAR-REGULATOR CONTROLLER (REG G, MAX1513 ONLY)
FBG Regulation Voltage
VFBG
IDRVG = 0.35mA
1.235
FBG to FB Regulation Voltage
Matching
IDRVG = 0.5mA, VCS+ - VCS- = 0
FBG Fault Trip Level
VFBG falling
0.96
FBG Input Bias Current
VFBG = 1.5V
-250
FBG Effective Load-Regulation
Error (Transconductance)
VDRVG = 10V, IDRVG = 0.175mA to 3.5mA
FBG Line (IN)-Regulation Error
IDRVG = 0.5mA, 2.7V < VIN < 5.5V
DRVG Sink Current
IDRVG
DRVG Off-Leakage Current
Soft-Start Period
VFBG = 1.1V, VDRVG = 10V
1.250
-1.2
1.00
-1.5
1.265
V
+1.2
%
1.04
V
+250
nA
-2
%
5
mV
5
VFBG = 1.5V, VDRVG = 28V
mA
0.15
tSS
Soft-Start Step Size
10
µA
2.7
ms
VREF / 128
V
LOGIC LINEAR-REGULATOR CONTROLLER (REG L)
FBL Regulation Voltage
IDRVL = 0.8mA
1.225
1.250
1.275
FBL Fault Trip Level
VFBL falling
0.96
1.00
1.04
V
FBL Input Bias Current
VFBL = 1.5V
-250
+250
nA
FBL Effective Load-Regulation
Error (Transconductance)
VDRVL = 3V, IDRVL = 0.4mA to 8mA
-2
%
FBL Line (IN)-Regulation Error
IDRVL = 1mA, 2.7V < VIN < 5.5V
8
mV
DRVL Sink Current
VFBL
IFBL
DRVL Off-Leakage Current
Soft-Start Period
Soft-Start Step Size
VFBL = 1.1V, VDRVL = VIN
VFBL = 1.5V, VDRVL = 28V
tSS
-1.5
15
20
0.15
V
mA
10
µA
2.7
ms
VREF / 128
V
_______________________________________________________________________________________
3
MAX1513/MAX1514
ELECTRICAL CHARACTERISTICS (continued)
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 3V, VSUPB = 10V, SDFR = IN, CREF = 0.22µF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE-OFF LINEAR-REGULATOR CONTROLLER (REG N)
FBN Regulation Voltage
IDRVN = 0.2mA
220
250
280
mV
FBN Fault Trip Level
VFBN
VFBN rising
380
420
460
mV
FBN Input Bias Current
VFBN = 0V
-250
+250
nA
FBN Effective Load-Regulation
Error (Transconductance)
VDRVN = -10V, IDRVN = 0.1mA to 2mA
25
mV
FBN Line (IN)-Regulation Error
IDRVN = 0.2mA, 2.7V < VIN < 5.5V
5
mV
DRVN Source Current
IFBN
DRVN Off-Leakage Current
VFBN = 0.3V, VDRVN = -10V
18
5
mA
VFBN = -0.1V, VDRVN = -20V
Soft-Start Period
0.1
tSS
Soft-Start Step Size
10
µA
2.7
ms
VREF / 128
V
BUFFER AMPLIFIER
SUPB Supply Range
VSUPB
SUPB Supply Current
ISUPB
4.5
No load, VFBPB = 4V
FBPB Input Offset Voltage
VOS
VFBPB = VSUPB / 2
FBPB Input Bias Current
IBIAS
VFBPB = VSUPB / 2
FBPB Input Common-Mode
Range
VCM
Common-Mode Rejection Ratio
CMRR
0 < VFBPB < VSUPB
VOH
IOUTB = 5mA
Output-Voltage-Swing Low
VOL
IOUTB = -5mA
Short-Circuit Current
PSRR
0.75
1.1
mA
0
12
mV
50
nA
VSUPB
V
DC, 6V ≤ VSUPB ≤ 13V, VFBPB = 4V
50
dB
VSUPB 150
VSUPB 80
±50
±150
mA
60
80
dB
mV
80
Slew Rate
-3dB Bandwidth
V
0
Output-Voltage-Swing High
Power-Supply Rejection Ratio
13.0
RL = 10kΩ, CL = 10pF
150
mV
10
V/µs
12
MHz
CONTROL INPUTS AND OUTPUTS
SDFR Input Level
SDFR = IN (1.5MHz operation)
0.9 × VIN
SDFR = unconnected (430kHz operation)
0.69 × VIN
SDFR = REF (750kHz operation)
0.77 × VIN
1.00
SDFR = GND (LCD shutdown)
4
V
0.5
SDFR = IN
SDFR Input Current
1.35
+3.0
SDFR = REF
-3.0
SDFR = GND
-3.0
_______________________________________________________________________________________
µA
TFT-LCD Power-Supply Controllers
(Circuit of Figure 1, VIN = 3V, VSUPB = 10V, SDFR = IN, CREF = 0.22µF, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
IN Supply Range
SYMBOL
CONDITIONS
MAX
UNITS
2.7
5.5
V
VIN rising
2.5
2.9
VIN falling
2.2
2.5
VIN
IN Undervoltage-Lockout
Threshold
IN Quiescent Current
VUVLO
IIN
REF Output Voltage
350mV typical
hysteresis
MIN
VFB = VFBP = VFBL = VFBG = 1.5V,
VFBN = 0
TYP
V
1.25
mA
V
-2µA < IREF < 100µA, 2.7V < VIN < 5.5V
1.225
1.275
SDFR = IN
1.275
1.725
SDFR = REF
0.60
0.90
VCS+ - VCS- = 0
1.230
1.270
V
0.2
%/V
-100
+100
nA
90
µA
MAIN STEP-UP CONTROLLER
Operating Frequency
fOSC
FB Regulation Voltage
VFB
FB Line Regulation
VIN = 2.7V to 5.5V
FB Input Bias Current
VFB = 1.5V
CS+ Input Current
2.2V < VCS+ < 6V
CS- Input Current
2.2V < VCS- < 6V
Current-Limit Threshold
VCS+ - VCS-, 2.2V < VCS+ < 6V
Gate-Drive Output
High or low
MHz
-1
+1
µA
100
150
mV
5
Ω
GATE-ON LINEAR-REGULATOR CONTROLLER (REG P)
FBP Regulation Voltage
IDRVP = 0.1mA
1.225
1.275
V
FBP Input Bias Current
VFBP = 1.5V
-250
+250
nA
FBP Effective Load-Regulation
Error (Transconductance)
VDRVP = 10V, IDRVP = 0.05mA to 1mA
-2
%
DRVP Sink Current
VFBP
IDRVP
DEL Turn-On Threshold
VFBP = 1.1V, VDRVP = 10V
VTH(DEL)
2
mA
1.19
1.31
V
1.235
1.265
V
GAMMA LINEAR-REGULATOR CONTROLLER (REG G, MAX1513 ONLY)
FBG Regulation Voltage
VFBG
IDRVG = 0.5mA
FBG to FB Regulation Voltage
Matching
IDRVG = 0.5mA, VCS+ - VCS- = 0
-1.2
+1.2
%
FBG Input Bias Current
VFBG = 1.5V
-250
+250
nA
FBG Effective Load-Regulation
Error (Transconductance)
VDRVG = 10V, IDRVG = 0.25mA to 5mA
-2
%
DRVG Sink Current
IDRVG
VFBG = 1.1V, VDRVG = 10V
10
mA
_______________________________________________________________________________________
5
MAX1513/MAX1514
ELECTRICAL CHARACTERISTICS
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 3V, VSUPB = 10V, SDFR = IN, CREF = 0.22µF, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC LINEAR-REGULATOR CONTROLLER (REG L)
FBL Regulation Voltage
VFBL
IDRVL = 1mA
1.225
1.275
V
FBL Input Bias Current
VFBL = 1.5V
-250
+250
nA
FBL Effective Load-Regulation
Error (Transconductance)
VDRVL = 3V, IDRVL = 0.5mA to 10mA
-2
%
DRVL Sink Current
IFBL
VFBL = 1.1V, VDRVL = VIN
20
mA
GATE-OFF LINEAR-REGULATOR CONTROLLER (REG N)
FBN Regulation Voltage
VFBN
IDRVN = 0.2mA
220
280
mV
FBN Input Bias Current
VFBN = 0V
-250
+250
nA
FBN Effective Load-Regulation
Error (Transconductance)
VDRVN = -10V, IDRVN = 0.1mA to 2mA
25
mV
DRVN Source Current
IFBN
VFBN = 0.3V, VDRVN = -10V
5
mA
BUFFER AMPLIFIER
SUPB Supply Range
VSUPB
SUPB Supply Current
ISUPB
13.0
V
No load, VFBPB = 4V
4.5
1.1
mA
FBPB Input Offset Voltage
VOS
VFBPB = VSUPB / 2
12
mV
FBPB Input Bias Current
IBIAS
VFBPB = VSUPB / 2
50
nA
FBPB Input Common-Mode
Range
VCM
VSUPB
V
Output-Voltage-Swing High
VOH
IOUTB = 5mA
Output-Voltage-Swing Low
VOL
IOUTB = -5mA
0
VSUPB - 150
mV
150
mV
CONTROL INPUTS AND OUTPUTS
SDFR Input Level
SDFR = IN (1.5MHz operation)
0.9 × VIN
SDFR = unconnected (430kHz operation)
0.69 × VIN
SDFR = REF (750kHz operation)
0.77 × VIN
1.00
SDFR = GND (LCD shutdown)
+3.0
SDFR = REF
-3.0
SDFR = GND
-3.0
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
6
V
0.5
SDFR = IN
SDFR Input Current
1.35
_______________________________________________________________________________________
µA
TFT-LCD Power-Supply Controllers
OUTPUT VOLTAGE (V)
80
VIN = 2.7V
VIN = 3.3V
70
60
VIN = 5V
VIN = 15V
fOSC = 1.5MHz
15.0
50
VMAIN
100mV
AC-COUPLED
14.9
14.8
IMAIN
500mA/div
0.1A
14.7
IL
1A/div
0A
14.6
40
0
100 200 300 400 500 600 700 800
100
200
300
400
500
600
700
4µs/div
LOAD CURRENT (mA)
LOAD CURRENT (mA)
STEP-UP REGULATOR
PULSED-LOAD-TRANSIENT RESPONSE
POWER-UP SEQUENCE
STEP-UP REGULATOR SOFT-START
MAX1513/14 toc04
MAX1513/14 toc06
MAX1513/14 toc05
VMAIN
100mV/div
AC-COUPLED
VMAIN
5V/div
0V
0V
0V
VGOFF
10V/div
IL
1A/div
VGAMMA
20V/div
IL
2A/div
0A
0A
4µs/div
400µs/div
LINEAR REGULATOR REG L
LOAD-TRANSIENT RESPONSE
BUFFER-AMPLIFIER SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1513/14 toc07
0V
4ms/div
1.2
1.0
ILOGIC
500mA/div
0mA
VMAIN
0V 20V/div
VGON
20V/div
IMAIN
1A/div
0.1A
VLOGIC
50mV/div
AC-COUPLED
VLOGIC
5V/div
0V
BUFFER-AMPLIFIER SMALL-SIGNAL
STEP RESPONSE
MAX1513/14 toc09
MAX1513/14 toc08
0
SUPPLY CURRENT (mA)
EFFICIENCY (%)
90
MAX1513/14 toc03
15.1
MAX1513/14 toc02
VIN = 5.0V
MAX1513/14 toc01
100
STEP-UP REGULATOR
LOAD-TRANSIENT RESPONSE
STEP-UP OUTPUT VOLTAGE
vs. LOAD CURRENT
STEP-UP EFFICIENCY
vs. LOAD CURRENT (1.5MHz)
VFBPB
50mV/div
AC-COUPLED
0.8
0.6
0.4
VOUTB
50mV/div
AC-COUPLED
0.2
NO LOAD
VFBPB = VSUPB / 2
0
20µs/div
4
6
8
10
12
14
400ns/div
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX1513/MAX1514
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 5V, VMAIN = 15V, VGON = 25V, VGOFF = -10V, VLOGIC = 3.3V, VGAMMA = 14.7V, TA = +25°C, unless otherwise noted.)
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 5V, VMAIN = 15V, VGON = 25V, VGOFF = -10V, VLOGIC = 3.3V, VGAMMA = 14.7V, TA = +25°C, unless otherwise noted.)
BUFFER-AMPLIFIER
LOAD-TRANSIENT RESPONSE
BUFFER-AMPLIFIER LARGE-SIGNAL
STEP RESPONSE
MAX1513/14 toc11
MAX1513/14 toc10
VOUTB
1V/div
AC-COUPLED
VFBPB
5V/div
AC-COUPLED
VOUTB
5V/div
AC-COUPLED
IOUTB
50mA/div
0mA
1µs/div
1µs/div
Pin Description
PIN
1
MAX1513 MAX1514
REF
REF
FUNCTION
Internal Reference. Connect a 0.22µF ceramic capacitor from REF to the analog ground plane,
which is connected to GND. External load capability is at least 100µA.
3
FBPB
N.C.
LCD Shutdown and Frequency-Select Input.
SDFR = GND, LCD shutdown, REF, buffer amplifier and the logic regulator (REG L) output stay on
SDFR = IN, 1.5MHz switching frequency
SDRF = REF, 750kHz switching frequency
SDFR = unconnected, 430kHz switching frequency
Buffer-Amplifier Noninverting Input for the MAX1513. Not internally connected for the MAX1514.
4
OUTB
N.C.
Buffer-Amplifier Output for the MAX1513. Not internally connected for the MAX1514.
5
SUPB
N.C.
Buffer-Amplifier Supply Input for the MAX1513. Bypass to GND with a 0.1µF capacitor. Not internally
connected for the MAX1514.
6
FBN
FBN
Gate-Off Linear Regulator (REG N) Feedback Input. FBN regulates to 125mV nominal. Connect to
the center tap of a resistive voltage-divider between the REG N output and the reference voltage
(REF) to set the output voltage. Place the resistive-divider close to this pin.
7
DEL
DEL
Delay-Control Timing Capacitor. Connect a capacitor from DEL to GND to set the gate-on linearregulator startup delay. See the Power-Up Sequence and Delay Control Block section.
2
8
NAME
SDFR
SDFR
_______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
PIN
NAME
FUNCTION
MAX1513 MAX1514
8
DRVN
DRVN
REG N Base Drive. Open drain of an internal P-channel MOSFET. Connect to the base of an
external NPN linear-regulator pass transistor.
9
DRVL
DRVL
Logic Linear-Regulator (REG L) Base Drive. Open drain of an internal N-channel MOSFET. Connect
to the base of an external PNP linear-regulator pass transistor.
10
FBL
FBL
REG L Feedback Input. FBL regulates to 1.25V (typ). Connect to the center tap of a resistive
voltage-divider between the REG L output and the analog ground plane to set the output voltage.
Place the resistive voltage-divider close to this pin.
11
DRVG
N.C.
Gamma Linear-Regulator (REG G) Base Drive for the MAX1513. Open drain of an internal N-channel
MOSFET. Connect to the base of an external PNP linear-regulator pass transistor. Not internally
connected for the MAX1514.
12
FBG
N.C.
REG G Feedback Input for MAX1513. FBG regulates to 1.25V (typ). Connect to the center tap of a
resistive voltage-divider between the REG G output and the analog ground plane to set the output
voltage. Place the divider close to the FBG pin. Not internally connected for the MAX1514.
13
FBP
FBP
Gate-On Linear-Regulator (REG P) Feedback Input. FBP regulates to 1.25V (typ). Connect to the
center tap of a resistive voltage-divider between the REG P output and the analog ground plane to
set the output voltage. Place the resistive-divider close to this pin.
14
DRVP
DRVP
REG P Base Drive. Open drain of an internal N-channel MOSFET. Connect to the base of an
external PNP linear-regulator pass transistor.
15
GND
GND
Ground
16
GATE
GATE
External MOSFET Gate Drive. Drives the gate of the step-up switching regulator’s MOSFET.
17
IN
IN
Supply Input. IN powers all the internal circuitry of the MAX1513/MAX1514. The input voltage range
is from 2.7V to 5.5V. Bypass with a 0.1µF ceramic capacitor between IN and GND. Place the
capacitor within 5mm of IN.
18
CS+
CS+
Current-Sense-Comparator Noninverting Input. Connect CS+ and CS- to the lossless current-sense
network. See the Lossless Current Sense section.
19
CS-
CS-
Current-Sense-Comparator Inverting Input. Connect CS+ and CS- to the lossless current-sense
network. See the Lossless Current Sense section.
20
FB
FB
Main Step-Up Regulator Feedback Input. FB regulates to 1.25V (typ). Connect to the center tap of a
resistive voltage-divider between the main output (VMAIN) and the analog ground plane to set the
main step-up regulator output voltage. Place the resistive-divider close to this pin.
_______________________________________________________________________________________
9
MAX1513/MAX1514
Pin Description (continued)
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
VIN
4.5V TO 5.5V
L1
2.2µH
C1
22µF
6.3V
D1
OPEN
R1
110kΩ
17
CS+
470pF
19
CS-
IN
GATE
2
SDFR
GND
7
DEL
0.47µF
FB
16
N1
R2
10.0kΩ
15
20
1.5kΩ
680Ω
9
Q1
VLOGIC
3.3V/500mA
R7
16.5kΩ
10µF
10
DRVL
DRVG
0.1µF
11
Q4
R8
10.0kΩ
FBG
R9
107kΩ
12
0.47µF
R10
10.0kΩ
LX
0.1µF
SUPB
5
3.6kΩ
0.1µF
0.1µF
FBPB
8
Q2
VGOFF
-10V/30mA
VGAMMA
14.7V/30mA
FBL
MAX1513
D2
1MΩ
0.1µF
18
2.2µF
C2
10µF
16V
909Ω
R11
10Ω
C10
1µF
VMAIN
15V/400mA
LX
R3
102kΩ
6
DRVN
OUTB
3
4
TO VCOM
BACKPLANE
LX
0.1µF
FBN
6.8kΩ
D3
0.47µF
R4
10.0kΩ
0.1µF
1
DRVP
14
REF
0.22µF
FBP
13
Q3
VGON
25V/20mA
R5
191kΩ
R6
10.0kΩ
0.47µF
Figure 1. Typical Operating Circuit of the MAX1513
10
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
VIN
4.5V TO 5.5V
LX
L1
2.2µH
D1
C1
22µF
6.3V
C2
10µF
16V
909Ω
OPEN
R11
10Ω
R1
110kΩ
1MΩ
0.1µF
18
CS+
17
470pF
19
CS-
IN
GATE
C10
1µF
2
SDFR
GND
7
DEL
0.47µF
2.2µF
FB
16
N1
R2
10.0kΩ
15
20
LX
680Ω
0.1µF
9
Q1
VLOGIC
3.3V/500mA
R7
16.5kΩ
10µF
10
6.8kΩ
DRVL
0.1µF
FBL
DRVP
R8
10.0kΩ
MAX1514
LX
0.1µF
D2
D3
FBP
14
13
Q3
R5
191kΩ
R6
10.0kΩ
VGON
25V/20mA
0.47µF
3.6kΩ
0.1µF
8
Q2
VGOFF
-10V/30mA
R3
102kΩ
0.47µF
6
DRVN
FBN
R4
10.0kΩ
1
REF
0.22µF
Figure 2. Typical Operating Circuit of the MAX1514
______________________________________________________________________________________
11
MAX1513/MAX1514
VMAIN
15V/400mA
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
VIN
CS+
MAX1513
MAX1514
SDFR
CS-
MAIN STEP-UP
CONTROLLER
WITH SOFT-START
AND FAULT
COMPARATOR
DEL
VMAIN
GATE
GND
FB
VIN
DRVL
REG L
WITH SOFT-START
AND FAULT
COMPARATOR
VLOGIC
DRVP
FBL
REG P
WITH SOFT-START
AND FAULT
COMPARATOR
VGON
FBP
CONTROL
BLOCK
VMAIN
DRVG
VGAMMA
FBG
REG G
WITH SOFT-START
AND FAULT
COMPARATOR
DRVN
REG N
WITH SOFT-START
AND FAULT
COMPARATOR
SUPB
VGOFF
FBN
FBPB
REFERENCE
TO VCOM
REF
OUTB
OP-AMP
THERMAL
SHUTDOWN
MAX1513 ONLY
Figure 3. MAX1513/MAX1514 Functional Diagram
12
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
Detailed Description
The typical operating circuit of the MAX1513 (Figure 1) is
a complete power-supply system for TFT LCDs. The circuit generates a +15V source-driver supply, +25V and
-10V gate-driver supplies, a +3.3V logic supply for the
timing controller, a 14.7V gamma-correction string supply
and a VCOM buffer. The typical operating circuit of the
MAX1514 (Figure 2) is similar to that of the MAX1513
except the gamma-correction string supply and the
VCOM buffer have been eliminated. The input voltage
range for the IC is from +2.7V to +5.5V. The typical operating circuits’ listed load currents are available from a
+4.5V to +5.5V supply. Table 1 lists recommended component options, and Table 2 lists the component suppliers’ contact information.
The MAX1513 and MAX1514 contain a high-performance, step-up switching-regulator controller and three
linear-regulator controllers (two positive and one negative). The MAX1513 also includes an additional linear-regulator controller and a high-current buffer amplifier. Figure
3 shows the MAX1513/MAX1514 functional diagram.
Table 1. Component List
DESIGNATION
DESCRIPTION
C1
22µF ±20%, 6.3V X5R ceramic capacitor (1206)
Taiyo Yuden JMK316BJ226ML
C2
10µF ±20%, 16V POSCAP (D10)
Sanyo 16AQU10M
D1
1A, 30V Schottky diode (S-Flat)
Toshiba CRS02
D2, D3
Main Step-Up Regulator Controller
The main step-up regulator controller drives an external
N-channel power MOSFET to generate the TFT-LCD
source-driver supply. The controller employs a currentmode, fixed-frequency PWM architecture to maximize
loop bandwidth and provide fast transient response to
pulsed loads found in source-driver applications. The
multilevel control input SDFR sets the switching frequency to 430kHz, 750kHz, or 1.5MHz. The high
switching frequency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness
of LCD panel designs, while maintaining high efficiency
using a lossless current-sense method. The IC’s built-in
soft-start function reduces the inrush current during
startup.
The controller regulates the output voltage and the
power delivered to the output by modulating the duty
cycle (D) of the power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
200mA, 100V diodes (SOT23)
Fairchild MMBT4148SE
L1
2.2µH, 3.3A inductor
Sumida CLS7D16NP-2R2NC
N1
3A, 20V N-channel MOSFET (SOT23)
Fairchild FDN339AN
Q1
3A, 60V PNP bipolar transistor (SOT23)
Fairchild NZT660
Q2
200mA, 40V NPN bipolar transistor (SOT23)
Fairchild MMBT3904
Q3, Q4
200mA, 40V PNP bipolar transistors (SOT23)
Fairchild MMBT3906
D ≈
VMAIN - VIN
VMAIN
Figure 4 shows the functional diagram of the step-up
regulator controller. The core of the controller is a multiinput summing comparator that sums three signals: the
output-voltage error signal with respect to the reference
voltage, the current-sense signal, and the slope-compensation ramp. On the rising edge of the internal
clock, the controller sets a flip-flop, which turns on the
external N-channel MOSFET, applying the input voltage
across the inductor. The current through the inductor
ramps up linearly, storing energy in its magnetic field.
Once the sum of the feedback voltage error, slope
compensation, and current-sense signals trip the multi-
Table 2. Component Suppliers
PHONE
FAX
Fairchild Semiconductor
SUPPLIER
408-822-2000
408-822-2102
www.fairchildsemi.com
WEBSITE
Sumida
847-545-6700
847-545-6720
www.sumida.com
Taiyo Yuden
800-348-2496
847-925-0899
www.t-yuden.com
TDK
847-803-6100
847-390-4405
www.component.tdk.com
Toshiba
949-455-2000
949-859-3963
www.toshiba.com
______________________________________________________________________________________
13
MAX1513/MAX1514
Typical Operating Circuit
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
input PWM comparator, the flip-flop is reset and the
MOSFET turns off. Since the inductor current is continuous, a transverse potential develops across the inductor
that turns on the diode (D1). The voltage across the
inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The N-channel
MOSFET is kept off for the rest of the clock cycle.
Current Limiting and
Current-Sense Amplifier (CS+, CS-)
The internal current-limit circuit resets the PWM flip-flop
and turns off the external power MOSFET whenever the
voltage difference between CS+ and CS- exceeds
125mV (typ). The tolerance on this current limit is
±20%. Use the minimum value of the current limit to
select components of the current-sense network.
Lossless Current Sense
The lossless current-sense method uses the DC resistance (DCR) of the inductor as the sense element.
Figure 5 shows a simplified step-up regulator using the
basic lossless current-sensing method. An RC network
is connected in parallel with the step-up inductor (L).
The voltage across the sense capacitor (C S) is the
RESET DOMINANT
CLOCK
S
R
GATE
Q
ILIM
COMPARATOR
125mV
input to the current-sense amplifier. To prevent the
sense amplifier from seeing large common-mode
switching voltages, the sense capacitor should always
be connected to the nonswitching end of the inductor
(i.e., the input of the step-up regulator).
Lossless current sense can be easily understood using
complex frequency domain analysis. The voltage
across the inductor is given by:
VL = IL (sL + RL )
where L is the inductance, RL is the DCR of the inductor, and IL is the inductor current. The voltage across
the sense capacitor is given by:
1
VL
1 + sRSCS
VS =
where RS is the series resistor in the sense network and
CS is the sense capacitor. The above equation can be
rewritten as:
VS =
If
sL + RL
1 + sL / RL
IL =
RLIL
1 + sRSCS
1 + sRSCS
L
= RSCS , then the equation becomes :
RL
VS = RLIL
Therefore, the sense capacitor voltage is directly proportional to the inductor current if the time constant of
the RC sense network matches the time constant of the
inductor/DCR. The sense method is equivalent to using
a current-sense resistor that has the same value as the
inductor DCR.
INDUCTOR
RL
CS+
LEVEL
SHIFT
L
VIN
VMAIN
CS-
RS
CS
Σ
SLOPE_COMP
+
FB
VS
CS+
CSGATE
TO
FAULT LOGIC
SOFT-START
BLOCK
REF
1.0V
Figure 4. Step-Up Regulator-Controller Functional Diagram
14
MAX1513
MAX1514
GND
FB
Figure 5. Step-Up Regulator Using Lossless Current Sensing
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
Gate-Off Linear-Regulator Controller
The gate-off linear-regulator controller (REG N) is an analog gain block with an open-drain P-channel output. It drives an external NPN pass transistor with a 3.6kΩ
base-to-emitter resistor (Figure 1). Its guaranteed basedrive source current is at least 2mA. The regulator,
including Q2 in Figure 1, uses a 0.47µF ceramic output
capacitor and is designed to deliver 30mA at -10V. Other
output voltages and currents are possible by scaling the
pass transistor, input capacitor, and output capacitor.
See the Pass-Transistor Selection and Stability Requirements sections.
REG N is typically used to provide the TFT-LCD gate drivers’ gate-off voltage. A negative voltage can be produced using a charge-pump circuit as shown in Figure 1.
REG N is enabled after the logic linear-regulator REG L
soft-start has completed. Each time it is enabled, the
control goes through a soft-start routine that ramps
down its internal reference DAC from VREF to 250mV in
about 100 steps.
Gate-On Linear-Regulator Controller
The gate-on linear-regulator controller (REG P) is an
analog gain block with an open-drain N-channel output.
It drives an external PNP pass transistor with a 6.8kΩ
base-to-emitter resistor (Figure 1). Its guaranteed basedrive sink current is at least 1mA. The regulator including Q3 in Figure 1 uses a 0.47µF ceramic output
capacitor and is designed to deliver 20mA at 25V.
Other output voltages and currents are possible by
scaling the pass transistor, input capacitor, and output
capacitor. See the Pass-Transistor Selection and
Stability Requirements sections.
REG P is typically used to provide the TFT-LCD gate
drivers’ gate-on voltage. Use a charge pump with as
many stages as necessary to obtain a voltage exceeding the required gate-on voltage (see the Selecting the
Number of Charge-Pump Stages section). Note that the
voltage rating of the DRVP output is 28V. If the chargepump output voltage can exceed 28V, an external cascode-connected NPN transistor should be added
(Figure 6). Alternately, the linear regulator can control
an intermediate charge-pump state while regulating the
final charge-pump output (Figure 7).
REG P is enabled after the step-up regulator soft-start
has completed and the voltage on DEL exceeds 1.25V.
Each time it is enabled, the controller goes through a
soft-start routine that ramps up its internal reference DAC
in 128 steps.
LX
VMAIN
0.1µF
FROM CHARGEPUMP OUTPUT
VMAIN
13V
0.1µF
DRVP
NPN CASCODE
TRANSISTOR
PNP PASS
TRANSISTOR
6.8kΩ
DRVP
VGON
MAX1513
MAX1514
MAX1513
MAX1514
FBP
Q1
0.47µF
VGON
35V
267kΩ
1%
0.22µF
FBP
10.0kΩ
1%
Figure 6. Using an NPN Cascode for Charge-Pump Output
Voltages > 28V
Figure 7. Linear Regulator Controls Intermediate Charge-Pump
Stage
______________________________________________________________________________________
15
MAX1513/MAX1514
Logic Linear-Regulator Controller
The logic linear-regulator controller (REG L) is an analog
gain block with an open-drain N-channel output. It drives an external PNP pass transistor with a 680Ω baseto-emitter resistor (Figure 1). Its guaranteed base-drive
sink current is at least 10mA. The regulator, including
transistor Q1 in Figure 1, uses a 10µF ceramic output
capacitor and is designed to deliver 500mA at 3.3V.
Other output voltages and currents are possible by scaling the pass transistor, input capacitor, and output
capacitor. See the Pass-Transistor Selection and
Stability Requirements sections.
REG L is typically used to generate low-voltage logic
supplies for the timing controller and the digital sections of the TFT-LCD source/gate-drive ICs.
REG L is automatically enabled when the input voltage
is above the UVLO threshold. Each time it is enabled,
the controller goes through a soft-start routine that
ramps up its internal reference DAC in 128 steps.
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
Gamma Linear-Regulator Controller
(MAX1513 Only)
The gamma linear-regulator controller REG G is an analog gain block with an open-drain N-channel output. It
drives an external PNP pass transistor with a 1.5kΩ
base-to-emitter resistor (Figure 1). Its guaranteed basedrive sink current is at least 5mA. The regulator, including Q4 in Figure 1, uses a 0.47µF ceramic output
capacitor, and the controller is designed to deliver
40mA at 14.7V. Other output voltages and currents are
possible by scaling the pass transistor, input capacitor,
and output capacitor. See the Pass-Transistor Selection
and Stability Requirements sections.
REG G is typically used to provide the TFT-LCD gamma
reference voltage, which is usually 0.3V below the
source-drive supply voltage.
REG G is enabled 2.7ms after REG P’s soft-start has
completed. Each time it is enabled, the controller goes
through a soft-start routine that ramps up its internal reference DAC in 128 steps.
Buffer Amplifier (MAX1513 Only)
The MAX1513 includes a buffer amplifier that is typically used to drive the LCD backplane (VCOM) or the
gamma-correction divider string. The buffer amplifier
features ±150mA output short-circuit current, 10V/µs
slew rate, and 12MHz bandwidth. The Rail-to-Rail®
input and output capability maximizes its flexibility.
Short-Circuit Current Limit
The MAX1513’s buffer amplifier limits short-circuit current to approximately ±150mA if the output is directly
shorted to SUPB or to GND. If the short-circuit condition
persists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermalshutdown threshold, an internal thermal sensor immediately sets the thermal fault latch, shutting off all the IC’s
outputs. The device remains inactive until the input voltage is cycled below VUVLO.
Driving Pure Capacitive Load
The buffer amplifier is typically used to drive the LCD
backplane (VCOM) or the gamma-correction divider
string. The LCD backplane consists of a distributed
series capacitance and resistance, a load that can be
easily driven by the buffer amplifier. When driving a
pure capacitive load, the amplifier’s gain peaking
increases. A 5Ω to 50Ω resistor placed between OUTB
and the capacitive load reduces peaking.
Undervoltage Lockout
The undervoltage-lockout (UVLO) circuit compares the
voltage at the IN pin with the UVLO threshold (2.7V ris16
ing, 2.35V falling, typ) to ensure the input voltage is
high enough for reliable operation. The 350mV (typ)
hysteresis prevents supply transients from causing a
restart. Once the input voltage exceeds the UVLO rising threshold, the IC is allowed to start. When the input
voltage falls below the UVLO falling threshold, all the
regulator outputs (including REF) are disabled until the
input voltage exceeds the UVLO rising threshold.
Reference Voltage (REF)
The reference output is nominally 1.25V and can source
at least 100µA without degrading its accuracy (see the
Typical Operating Characteristics). Bypass REF with a
0.22µF ceramic capacitor connected between REF and
the analog ground plane (which connects to GND).
Shutdown and OscillatorFrequency Selection
The four-level logic input SDFR controls shutdown and
oscillator-frequency selection. Connecting SDFR to
ground shuts off all the regulator outputs except the logic
linear-regulator controller (REG L), buffer amplifier, and
REF. Connecting SDFR to IN sets the oscillator frequency to 1.5MHz. Connecting SDFR to REF sets the oscillator frequency to 750kHz. Leaving SDFR unconnected
sets the oscillator frequency to 430kHz. When SDFR is
left unconnected, bypass the pin to ground with a
1000pF to 0.1µF capacitor to prevent switching noise
from coupling into the pin’s high input impedance. Note
the soft-start period and the fault-timer period do not
change with the oscillator frequency.
Power-Up Sequence
and Delay Control Block
Once the voltage on IN exceeds the UVLO rising threshold (2.7V typ), the internal reference is enabled. With a
0.22µF REF bypass capacitor, the reference reaches its
regulation voltage of 1.25V in approximately 1ms. When
the reference voltage is ready, the MAX1513/MAX1514
enable the logic linear regulator. The MAX1513 also
enables the buffer amplifier at the same time. Once the
logic linear-regulator soft-start is completed, the
MAX1513/MAX1514 enable the step-up regulator and
REG N simultaneously. Once the soft-start of the step-up
regulator is completed, the MAX1513/MAX1514 enable
the delay control block. An internal 5µA current starts
charging the timing capacitor on DEL. When the voltage
on DEL reaches 1.25V, the MAX1513/MAX1514 enable
REG P. With a 0.1µF capacitor on DEL, the DEL voltage
reaches 1.25V in about 25ms. The MAX1513 enables the
gamma linear regulator 2.7ms after the soft-start of REG P
is completed.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
Fault Protection
During steady-state operation, if the step-up regulator
output or any of the linear-regulator outputs does not
exceed its respective fault detection threshold, the
MAX1513/MAX1514 activate an internal fault timer. If
any condition or the combination of conditions indicates a continuous fault for the fault-timer duration
(43.6ms typ), the MAX1513/MAX1514 set the fault
latch, shutting down all the outputs except the reference. Once the fault condition is removed, toggle SDFR
(below 0.4V) or cycle the input voltage (below 2.2V) to
clear the fault latch and reactivate the device. The faultdetection circuit is disabled during the soft-start time of
each regulator.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the MAX1513/
MAX1514. When the junction temperature exceeds
+160°C, a thermal sensor immediately activates the
fault-protection circuit, which shuts down all the outputs
except the reference, allowing the device to cool down.
Once the device cools down by approximately 15°C,
cycle the input voltage (below the UVLO falling threshold) to clear the fault latch and reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction
temperature rating of TJ = +150°C.
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating,
and DC series resistance (DCR) are factors to consider
when selecting the inductor. These factors influence the
converter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
The maximum output current, input voltage, output voltage, and switching frequency determine the inductor
value. Very high inductance values minimize the current ripple and therefore reduce the peak current,
which decreases core losses in the inductor and I 2R
losses in the entire power path. However, large inductor values also require more energy storage and more
turns of wire, which increases size and can increase
I 2 R losses in the inductor. Low inductance values
decrease the size but increase the current ripple and
peak current. Finding the best inductor involves choosing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant, LIR, which
is the ratio of the inductor peak-to-peak ripple current
to the average DC inductor current at the full load current. The best trade-off between inductor size and circuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and the
ratio of inductor resistance to other power-path resistances, the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be
accepted to reduce the number of turns required and
increase the wire diameter. If the inductor resistance is
relatively low, increasing inductance to lower the peak
current can decrease losses throughout the power
path. If extremely thin high-resistance inductors are
used, as is common for LCD panel applications, the
best LIR can increase to between 0.5 and 1.0.
Once an inductor is chosen, higher and lower values
for the inductor should be evaluated for efficiency
improvements in typical operating regions.
Determine the inductor value and peak current requirement as follows:
Since the current delivered by charge pumps connected to LX adds to the inductor current, calculate the
effective maximum output current, IMAIN(EFF):
IMAIN(EFF) = IMAIN(MAX) + nNEG × INEG
+ (nPOS + 1) × IPOS
where I MAIN(MAX) is the maximum output current
including any gamma-regulator current, n NEG is the
number of negative charge-pump stages, nPOS is the
number of positive charge-pump stages, INEG is the
negative charge-pump output current, and IPOS is the
positive charge-pump output current, assuming the
pump source for IPOS is VMAIN.
Calculate the approximate inductor value using the typical input voltage (VIN), the expected efficiency (ηTYP)
______________________________________________________________________________________
17
MAX1513/MAX1514
Soft-Start
Each positive regulator (step-up regulator, REG P, REG
L, and REG G) includes a 7-bit soft-start DAC whose
input is the reference, and whose output is stepped in
128 steps from zero up to the reference voltage. The
soft-start DAC of the negative regulator (REG N) steps
from the reference down to 250mV in about 100 steps.
The outputs of the soft-start DACs determine the set
points of each regulator. The soft-start duration is 2.7ms
(typ) for each positive regulator and about 2.2ms for the
negative regulator. The soft-start is independent of the
selected operating frequency.
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
taken from an appropriate curve in the Typical
Operating Characteristics, and an estimate of LIR
based on the above paragraphs:
2
⎛ V
⎞ ⎛
VMAIN - VIN ⎞ ⎛ ηTYP ⎞
L = ⎜ IN ⎟ ⎜
⎟
⎟⎜
⎝ VMAIN ⎠ ⎝ IMAIN(EFF) × fOSC ⎠ ⎝ LIR ⎠
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current at the minimum input voltage (VIN(MIN)) using the
following equation:
IIN(DC, MAX) =
IMAIN(EFF) × VMAIN
VIN(MIN) × ηMIN
The expected efficiency at that operating point (ηMIN)
can be taken from an appropriate curve in the Typical
Operating Characteristics.
Calculate the ripple current at that operating point and
the peak current required for the inductor:
IRIPPLE =
(
VIN(MIN) × VMAIN - VIN(MIN)
L × VMAIN × fOSC
I
IPEAK = IIN(DC, MAX) + RIPPLE
2
)
The inductor’s saturation current rating and the
MAX1513/MAX1514s’ current limit (ILIM) should exceed
I PEAK , and the inductor’s DC current rating should
exceed IIN(DC, MAX).
Considering the typical operating circuit, the maximum
load current (IMAIN(MAX)) is 400mA for IMAIN directly
and 30mA for REG G to provide V GAMMA. The onestage negative charge pump provides 30mA to REG N
for VGOFF, and the one-stage positive charge pump
provides 20mA to REG P for V GON . Altogether, the
effective maximum output current (IMAIN(EFF)) is 500mA
with a 15V output and a typical 5V input voltage. The
switching frequency is set to 1.5MHz. Choosing an
LIR of 0.6 and estimating efficiency of 85% at this
operating point:
2
15V - 5V
⎞ ⎛ 0.85 ⎞
⎛ 5V ⎞ ⎛
L = ⎜
⎟ ≈ 2.2µH
⎟ ⎜
⎟⎜
⎝ 15V ⎠ ⎝ 0.5A × 1.5MHz ⎠ ⎝ 0.6 ⎠
Using the circuit’s minimum input voltage (4.5V) and
estimating efficiency of 80% at that operating point:
IIN(DC, MAX) =
18
0.5A × 15V
≈ 2.1A
4.5V × 0.8
The ripple current and the peak current are:
IRIPPLE =
4.5V × (15V - 4.5V )
2.2µH × 15V × 1.5MHz
1.0A
≈ 2.6A
IPEAK = 2.1A +
2
≈ 1.0A
The inductor DCR should be low enough for reasonable
efficiency. As a rule of thumb, do not allow the voltage
drop across the inductor DCR to exceed a few percent
of the input voltage at IPEAK.
Many notebook panel designs have height constraints
on the components. If a thin inductor with the required
current rating is not available, use two thin inductors in
series or parallel.
Current-Sense Network Selection
After selecting the inductor, use the following steps to
design the current-sense network for lossless current
sensing.
1) Calculate the RC time constant of the sense network
using the typical inductance and typical DCR:
τ =
L
RL(TYP)
2) Determine the component values of the sense network. Select CS, and then calculate RS using:
RS =
τ
CS
3) Calculate the worst-case high sense voltage over
temperature using the maximum DCR value (RL(MAX))
found in the inductor technical specifications:
VSENSE = IPEAK × RL(MAX) × (1 + TC × ∆T)
where IPEAK is the peak inductor current calculated in
the Inductor Selection section, TC is the temperature
coefficient of copper (0.5%/°C) and ∆T is the difference
between the specified temperature for RL(MAX) and the
maximum expected inductor temperature.
4) Compare the calculated sense voltage with the minimum value of the current-limit threshold in the Electrical
Characteristics (100mV). If the sense voltage is between
80mV and 100mV, use the current-sense configuration
in Figure 8 with the calculated CS and RS above.
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
SF =
2.2µH
= 91.7µs
24mΩ
Select CS = 0.1µF and calculate RS:
100mV
VSENSE
91.7µs
= 917Ω
0.1µF
RS =
Assuming ∆T is 40°C and TC is 0.5%, the worst-case
high sense voltage over temperature is:
Calculate RS1 and RS2:
VSENSE = 2.6A × 30mΩ (1 + 0.005 × 40°C) = 93.6mV
RS
SF
R × SF
RS2 = S1
1 - SF
RS1 =
6) If VSENSE is less than 80mV, the current-feedback
signal is low relative to the current-limit threshold. Use
the Figure 8 configuration, or, if good current-limit
accuracy is desired, use the optional current-sense
configuration in Figure 10 to increase the amplitude of
the sense signal. Calculate RS3 and RS4:
RS3 =
τ =
VMAIN - VIN(MIN)
VMAIN - VIN(MIN) - 100mV + VSENSE
× RS
Because VSENSE would be between 80mV and 100mV,
the circuit in Figure 8 should be used. The closest 1%
standard value for RS is 909Ω.
If the 2.2µH inductor used in the typical operating circuit (Figures 1 and 2) has a typical DCR of 45mΩ and a
maximum DCR of 56mΩ, the RC time constant of the
sense network is:
τ =
Select CS = 0.1µF and calculate RS:
RS4 = RS - RS3
If the 2.2µH inductor used in the typical operating circuit (Figures 1 and 2) had a typical DCR of 24mΩ and a
maximum DCR of 30mΩ, the RC time constant of the
sense network would be:
2.2µH
= 48.9µs
45mΩ
RS =
48.9µs
= 489Ω
0.1µF
Assuming ∆T is 40°C and TC is 0.5%, the worst-case
high sense voltage over temperature is:
L
L
VMAIN
VIN
VMAIN
VIN
RS1
RS
RS2
CS
CS
CS+
CSGATE
MAX1513
MAX1514
CS+
CS-
GND
FB
GATE
MAX1513
MAX1514
GND
FB
Figure 8. Lossless Current Sensing with 80mV < VSENSE < 100mV
Figure 9. Lossless Current Sensing with VSENSE > 100mV
______________________________________________________________________________________
19
MAX1513/MAX1514
5) If VSENSE is greater than 100mV, the current-feedback signal is too high and can trip the current limit
before the full load current is delivered. Use the current-sense configuration in Figure 9 to attenuate the
sense signal. Define the scale factor (SF) as:
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
Select CS = 0.1µF, RS is:
L
VMAIN
VIN
RS =
RS3
CS
220µs
= 2200Ω
0.1µF
Assuming ∆T is 40°C and TC is 0.5%, the worst-case
high sense voltage over temperature is:
RS4
CS+
VSENSE = 2.6A × 14mΩ (1 + 0.005 × 40°C) = 44mV
CSGATE
MAX1513
MAX1514
Because VSENSE would be much less than 80mV, the
circuit in Figure 10 can be used to improve the currentlimit accuracy. Calculate RS3 and RS4:
GND
FB
RS3 =
Figure 10. Lossless Current Sensing with VSENSE < 80mV
15V - 4.5V
15V - 4.5V - 0.1V + 0.044 V
RS4 = 2614 Ω - 2600Ω = 14 Ω
× 2600Ω = 2614 Ω
The closest 1% standard values for RS3 and RS4 are
2.61kΩ and 14.0Ω, respectively.
(
VSENSE = 2.6A × 56mΩ 1 + 0.005 × 40°C
)
= 175mV
Because VSENSE would be greater than 100mV, the circuit in Figure 9 should be used and the scale factor is:
SF =
100mV
= 0.571
175mV
Calculate RS1 and RS2:
489Ω
= 856Ω
0.571
856 × 0.571
RS2 =
= 1139Ω
1 - 0.571
RS1 =
The closest 1% standard values for RS1 and RS2 are
866Ω and 1.13kΩ, respectively.
If the 2.2µH inductor used in the typical operating circuit (Figures 1 and 2) has a typical DCR of 10mΩ and a
maximum DCR of 14mΩ, the RC time constant of the
sense network is:
τ =
20
2.2µH
= 220µs
10mΩ
Output-Capacitor Selection
The output capacitor and its equivalent series resistance
(ESR) affect the circuit’s stability, output voltage ripple,
and transient response. The Output-Capacitor Stability
Requirement section discusses the output capacitance
requirement based on the loop stability. This section
deals with how to determine the output capacitance
according to the ripple voltage and load-transient
requirements.
The total output voltage ripple has two components: the
ohmic ripple due to the capacitor’s equivalent series
resistance (ESR), and the capacitive ripple caused by
the charging and discharging of the output capacitance:
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C)
VRIPPLE(ESR) ≈ IPEAK × RESR
VRIPPLE(C) ≈
⎛ V
IMAIN
- VIN ⎞
× ⎜ MAIN
⎟
COUT
⎝ VMAIN × fOSC ⎠
where VMAIN is the output voltage of the step-up regulator, IMAIN is the output current, COUT is the output
capacitance, RESR is the ESR of the output capacitor,
fOSC is the switching frequency, and IPEAK is the peak
inductor current (see the Inductor Selection section).
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
RESR(MAX) ≤
VRIPPLE(MAX)
2 × IPEAK
⎛ V
- VIN
2 × IMAIN
COUT(MIN) ≥
× ⎜ MAIN
VRIPPLE(MAX) ⎝ VMAIN × fOSC
where VRIPPLE(MAX) is the total peak-to-peak output ripple. Since the peak inductor current calculated in the
Inductor Selection section is 2.6A, the maximum ESR of
the output capacitor should be less than 29mΩ. On the
other hand, only 3.1µF capacitance is needed to meet
the capacitive ripple requirement based on the calculation. A 10µF AQU-series POSCAP with maximum ESR
of 20mΩ is selected for the typical operating circuits in
Figures 1 and 2, which meets both the voltage-ripple
and minimum capacitance requirements.
The typical load on the step-up regulator for sourcedriver applications is a large pulsed load, with a peak
current of approximately 1A and a pulse width of
approximately 2µs. The shape of the pulse is close to
triangular, so it is equivalent to a square pulse with 1A
height and 1µs pulse width. The total voltage dip during
the pulsed load transient also has two components: the
ohmic dip due to the output capacitor’s ESR and the
capacitive dip caused by discharging the output
capacitance:
VDIP = VDIP(ESR) + VDIP(C)
VDIP(ESR) = IPULSE × RESR
I
× tPULSE
VDIP(C) ≈ PULSE
COUT
where IPULSE is the height of the pulse load and tPULSE
is the pulse width. Higher capacitance and lower ESR
result in less voltage dip. Again, assume the ESR dip
and the capacitive dip each should not exceed 50% of
the total maximum allowed output-voltage dip caused
by a load pulse (VDIP(MAX)).
RESR(MAX) ≤
COUT(MIN) ≥
VDIP(MAX)
2 × IPULSE
2 × IPULSE × t PULSE
VDIP(MAX)
For the typical load pulse described above, assuming the
voltage dip must be limited to 200mV, the minimum output capacitor is 10µF, and the maximum ESR is 100mΩ.
The voltage rating and temperature characteristics of
the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection into the device. A 22µF ceramic capacitor is used
in the typical operating circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, CIN can be reduced below the values used in
the typical operating circuit. Ensure a low noise supply
at IN by using adequate CIN. Alternately, greater voltage variation can be tolerated on CIN if IN is decoupled
from CIN using an RC lowpass filter (see R11 and C10
in Figure 1).
Rectifier Diode
The MAX1513/MAX1514s’ high switching frequency
demands a high-speed rectifier. Schottky diodes are
recommended for most applications because of their
fast recovery time and low forward voltage. In general,
use a Schottky diode with a current rating exceeding
the peak inductor current calculated in the Inductor
Selection section.
Output-Voltage Selection
The output voltage of the main step-up regulator is
adjustable by connecting a resistive voltage-divider
from the output (VMAIN) to the analog ground plane
with the center tap connected to FB (see Figure 1).
Select R2 in the 10kΩ to 50kΩ range. Calculate R1 with
the following equations:
⎛V
⎞
R1 = R2 × ⎜ MAIN - 1⎟
⎝ VFB
⎠
where VFB, the step-up regulator’s feedback set point,
is 1.25V. Connect the divider close to the IC.
Output-Capacitor Stability Requirement
The step-up regulator controller of the MAX1513/
MAX1514 uses a peak current-mode control method.
The loop stability of a current-mode step-up regulator
can be analyzed using a small-signal model. In continuous-conduction mode, the loop-gain transfer function
consists of a DC loop gain, a dominant pole, a righthalf-plane (RHP) zero and an ESR zero.
______________________________________________________________________________________
21
MAX1513/MAX1514
In the circuits of Figures 1 and 2, the maximum total
voltage ripple is 1% (peak-to-peak) of the 15V output,
which corresponds to 150mV peak-to-peak ripple. A
conservative way to calculate the maximum ESR and
minimum capacitance is to assume the ESR ripple and
the capacitive ripple each should not exceed 50% of
the total ripple budget.
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
The DC loop gain (ADC) is approximately:
R2
1- D
VMAIN
ADC =
×
×
R1 + R2
0.554 × RCS
IMAIN(EFF)
where R1 and R2 are the feedback-divider resistors
(Figure 1), D is the duty cycle, IMAIN(EFF) is the effective maximum output current as described in the
Inductor Selection section, 0.554 is the gain of the current-sense amplifier, and RCS is the equivalent senseresistor value given by:
RCS = SF × RL(TYP)
where RL(TYP) is the typical value of the inductor DCR,
and SF is either 1 or the scale factor in step 5 of the
Current-Sense Network Selection section.
The frequency of the dominant pole is:
fZ(RHP) = (1 - D)
2
×
VMAIN
2π × L × IMAIN(EFF)
The frequency of the ESR zero is:
1
fZ(ESR) =
2π × RESR × COUT
The unity-gain crossover frequency is:
fCROSSOVER = ADC × fP(DOMINANT)
For stable operation, select an output capacitor with
enough capacitance and a low enough ESR to ensure
that the dominant pole is low enough so the loop gain
reaches unity well before either the ESR zero or the
RHP zero, the lower of which should preferably occur at
or above 5 times the unity-gain frequency as long as
the two zeros are well separated. Calculate the minimum output capacitance for stable operation using:
COUT(MIN) =
5 × ADC × IMAIN(EFF)
[
]
2π × min fZ(RHP) , fZ(ESR) × VMAIN
If the RHP zero and the ESR zero occur simultaneously,
place the dominant pole so that the unity-gain frequency is less than 1/10th the frequency of the zeros.
Calculate the minimum output capacitance for stable
operation using:
22
2π × fZ × VMAIN
Using the typical operating circuit in Figure 1 as an
example: the duty cycle is 0.67, the effective maximum
output current is 500mA, the inductor is 2.2µH with a
typical DCR of 24mΩ, and the output capacitor is 10µF
with a maximum ESR of 20mΩ. The scale factor for the
current-sense network is 1, so RCS is 24mΩ. The DC
loop gain ADC is 62, the RHP zero is at 236kHz, and the
ESR zero is at 796kHz. Since the frequency of the ESR
zero is higher than that of the RHP zero, the unity-gain
crossover frequency should be determined based on
the RHP zero. The minimum output capacitance for stable operation is:
2π × VMAIN × COUT
The frequency of the RHP zero is:
10 × ADC × IMAIN(EFF)
where f Z is the frequency of the RHP zero and the
ESR zero.
COUT(MIN) =
IMAIN(EFF)
fP(DOMINANT) =
COUT(MIN) =
5 × 62 × 500mA
≈ 6.97µF
2π × 236kHz × 15V
Lead or lag compensation can be useful to compensate for particular component choices or to optimize
the transient response for various output capacitor or
inductor values.
Adding lead compensation (the R3/C1 network from
VMAIN to FB in Figure 11) increases the loop bandwidth, which can increase the speed of response to
transients. Too much speed can destabilize the loop
and is not needed or recommended for Figure 1’s components. Lead compensation adds a zero-pole pair,
providing gain at higher frequencies and increasing
loop bandwidth. The frequencies of the zero and pole
for lead compensation depend on the feedback-divider
resistors and the RC network between VMAIN and FB.
The frequencies of the zero and pole for the lead compensation are:
fZ _ LEAD =
1
2π × (R1 + R3) × C1
fP _ LEAD =
1
R1 × R2 ⎞
⎛
2π × ⎜ R3 +
⎟ × C1
⎝
R1 + R2 ⎠
At high frequencies, R3 is effectively in parallel with R1,
determining the amount of added high-frequency gain.
If R3 is very large, there is no added gain and as R3
approaches zero, the added gain approaches the
inverse of the feedback-divider’s attenuation. A typical
value for R3 is greater than 1/2 of R1. The value of C1
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
1
R1 × R2 ⎞
⎛
2π × ⎜ R4 +
⎟ × C2
⎝
R1 + R2 ⎠
1
fZ _ LAG =
2π × R4 × C2
fP _ LAG =
At high frequencies, R4 is effectively in parallel with R2,
increasing the divider attenuation ratio. If R4 is very
large, the attenuation ratio remains unchanged and as
R4 approaches zero, the attenuation ratio approaches
infinity. A typical value for R4 is greater than 0.1 times
R2. If high-value divider-resistors are used, choose R4
< 1.5kΩ for FB noise immunity. The value of C2 deter-
L
mines the frequency placement of the pole and zero. A
typical value of C2 is between 100pF and 1000pF.
When adding lag compensation, always check the loop
stability by monitoring the transient response to a
pulsed output load.
Using Lead Compensation to Reduce
Startup Inrush Current
The digital soft-start of the main step-up regulator limits
the average input current during startup. If even
smoother startup is needed, add a low-frequency leadcompensation network (Figure 12). The improved softstart is active only during soft-start when the output
voltage rises. Positive changes in the output are instantaneously coupled to the FB pin through D1 and the
feed-forward capacitor C1. This arrangement generates a smoothly rising output voltage. When the output
voltage reaches regulation, capacitor C1 charges up
through R3 and diode D1 turns off. If desired, C1 and
R3 can be chosen to also provide some lead compensation in normal operation. In most applications, lead
compensation in normal operation is not needed and
can be avoided by making R3 large. With R3 much
greater than R1, the pole and the zero in the compensation network are very close to one another after startup and cancel out, eliminating the effect of the lead
compensation. With R2 at 10kΩ, an effective value for
C1 is approximately 1000pF.
Charge Pumps
L
D
VIN
VMAIN
D
VIN
VMAIN
R3
R3
D1
R1
R1
LX
LX
C1
C1
COUT
FB
COUT
FB
RLOAD
R4
R2
MAX1513
MAX1514
C2
GND
Figure 11. Feedback Compensation
R2
MAX1513
MAX1514
GND
Figure 12. Using Lead Compensation for Improved Soft-Start
______________________________________________________________________________________
23
MAX1513/MAX1514
determines the frequency placement of the zero and
pole. A typical value of C1 is between 100pF and 10nF.
When adding lead compensation, always check the
loop stability by monitoring the transient response to a
pulsed output load.
Adding lag compensation (the R4/C2 network from FB
to ground in Figure 11) decreases the loop bandwidth
and improves FB noise immunity. Lag compensation
slows the transient response but can increase the stability margin, which may be needed for particular component choice or high values of FB-divider resistors. Lag
compensation adds a pole-zero pair, attenuating gain at
higher frequencies and lowering loop bandwidth. The
frequencies of the pole and zero for lag compensation
depend on the feedback-divider resistors and the RC
network between FB and GND. The frequencies of the
pole and zero for the lag compensation are:
POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. VMAIN
-0
60
VD = 0.3V TO 1V
3-STAGE CHARGE-PUMP
1-STAGE
CHARGE-PUMP
-5
50
-10
-15
G_OFF (V)
40
G_ON (V)
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
2-STAGE CHARGE-PUMP
30
-20
2-STAGE
CHARGE-PUMP
-25
-30
20
3-STAGE
CHARGE-PUMP
-35
10
-40
1-STAGE CHARGE-PUMP
VD = 0.3V TO 1V
-45
0
2
4
6
8
10
12
14
2
4
6
8
10
12
14
VMAIN (V)
VMAIN (V)
Figure 13. Positive Charge-Pump Output Voltage vs. VMAIN
Figure 14. Negative Charge-Pump Output Voltage vs. VMAIN
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest number of charge-pump stages that meet the output voltage requirement. Figures 13 and 14 show the positive
and negative charge-pump output voltages for a given
VMAIN for one-, two-, and three-stage charge pumps.
The number of positive charge-pump stages is given by:
Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first
stage to VIN or another available supply. If the first
charge-pump stage is powered from V IN , then the
above equations become:
nPOS =
VGON + VDROPOUT - VMAIN
VMAIN - 2 × VD
where nPOS is the number of positive charge-pump
stages, VGON is the gate-on linear-regulator REG P output, VMAIN is the main step-up regulator output, VD is
the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V.
The number of negative charge-pump stages is given by:
nNEG =
-VGOFF + VDROPOUT
VMAIN - 2 × VD
where nNEG is the number of negative charge-pump
stages, VGOFF is the gate-off linear-regulator REG N
output, VMAIN is the main step-up regulator output, VD
is the forward-voltage drop of the charge-pump diode,
and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to VMAIN and the first stage of the
negative charge pump is connected to ground.
24
VGON + VDROPOUT - VIN
VMAIN - 2 × VD
-VGOFF + VDROPOUT + VIN
nNEG =
VMAIN - 2 × VD
nPOS =
Flying Capacitors
Increasing the flying capacitor (CX) value lowers the
effective source impedance and increases the outputcurrent capability. Increasing the capacitance indefinitely has a negligible effect on output-current capability
because the switch resistance and the diode impedance
place a lower limit on the source impedance. A 0.1µF
ceramic capacitor works well in most low-current applications. The flying capacitor’s voltage rating must
exceed the following:
VCX > n × VMAIN
where n is the stage number in which the flying capacitor appears, and VMAIN is the output voltage of the
main step-up regulator.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-topeak voltage during load transients. With ceramic
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
COUT _ CP ≥
ILOAD _ CP
2fOSCVRIPPLE _ CP
where COUT_CP is the output capacitor of the charge
pump, I LOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple.
The charge-pump output capacitor is typically also the
input capacitor for a linear regulator. Often, its value must
be increased to maintain the linear regulator’s stability.
Charge-Pump Rectifier Diodes
Use low-cost silicon switching diodes with a current rating
equal to or greater than twice the average charge-pump
input current. If their low forward voltage helps to avoid an
extra stage, some or all of the diodes can be replaced
with Schottky diodes with equivalent current ratings.
Linear-Regulator Controllers
Output-Voltage Selection
Adjust the positive linear-regulator (REG P, REG L, and
REG G) output voltages by connecting a resistive voltage-divider from their respective outputs to the analog
ground plane (which connects to GND) with the center
tap connected to FB_ (Figure 1). Select the lower resistor of the divider in the range of 10kΩ to 30kΩ. Calculate
the upper resistor with the following equation:
⎛ VOUT _
⎞
RUPPER = RLOWER × ⎜
- 1⎟
⎝ VFB _
⎠
where VOUT_ is the output voltage of the respective linear regulator, and VFB_ = 1.25V (typ).
Adjust the gate-off linear-regulator REG N output voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R4 between 20kΩ and 50kΩ.
Calculate R3 with the following equation:
⎛V
- VGOFF ⎞
R3 = R4 × ⎜ FBN
⎟
⎝ VREF - VFBN ⎠
where VFBN = 250mV, VREF = 1.25V. Note that REF can
only source up to 50µA; using a resistor less than 20kΩ
for R4 results in higher bias current than REF can supply without degrading REF accuracy.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (hFE), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output current to:
⎛
V ⎞
ILOAD(MAX) = ⎜ IDRV - BE ⎟ × hFE(MIN)
RBE ⎠
⎝
where IDRV is the minimum guaranteed base-drive current and RBE is the pullup resistor connected between
the transistor’s base and emitter. Furthermore, the transistor’s current gain increases the linear regulator’s DC
loop gain (see the Stability Requirements section), so
excessive gain destabilizes the output. Therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not
recommended unless needed to meet output-current
requirements.
The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Also, the package’s power dissipation limits the useable maximum power-dissipation capability of the transistor’s package, and mounting must exceed the actual
power dissipation in the device. The power dissipation
equals the maximum load current (ILOAD(MAX)_LR )
times the maximum input-to-output voltage differential:
(
P = ILOAD(MAX)_ LR × VIN(MAX)_ LR - VOUT_LR
)
where VIN(MAX)_LR is the maximum input voltage of the
linear regulator and VOUT_LR is the output voltage of
the linear regulator.
Stability Requirements
The MAX1513/MAX1514 linear-regulator controllers use
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifier, the pass transistor, the base-emitter resistor, and
the output capacitor determine the loop stability. The
following applies equally to all linear regulators in the
MAX1513 and MAX1514.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base current. The total DC loop gain is approximately:
______________________________________________________________________________________
25
MAX1513/MAX1514
capacitors, the output voltage ripple is dominated by
the capacitance value. Use the following equation to
approximate the required capacitor value:
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
⎡
⎛I
⎛ 4⎞
× hFE ⎞ ⎤
A V _ LR ≈ ⎜ ⎟ × ⎢1 + ⎜ BIAS
⎟ ⎥ × VREF
⎝ VT ⎠
⎢⎣
⎝ ILOAD _ LR ⎠ ⎥⎦
where CIN =
gm is the transconductance of the pass transistor,
and fT is the transition frequency. Both parameters
can be found in the transistor’s data sheet. Because
RBE is much greater than RIN, the above equation
can be simplified:
where VT is 26mV at room temperature and IBIAS is the
current through the base-to-emitter resistor (RBE). Each
of the four linear-regulator controllers is designed for a
different maximum output current, so they have different output drive currents and different bias currents
(IBIAS). Each controller’s bias current can be found in
the Electrical Characteristics table. The current listed in
the conditions column for the FB_ regulation voltage
specification is the individual controller’s bias current.
The base-to-emitter resistor for each controller should
be chosen to set the correct IBIAS:
RBE =
fPOLE _ IN =
4)
First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
fPOLE _ LR =
fPOLE _ FB =
5)
The unity-gain crossover of the linear regulator is:
2)
The pole created by the internal amplifier delay is
about 1MHz:
fPOLE _ AMP ≈ 1MHz
3)
Next, calculate the pole set by the transistor’s input
capacitance CIN, the transistor’s input resistance
RIN, and the base-to-emitter pullup resistor:
fPOLE _ IN =
26
1
(
2π × CIN × RBE || RIN
6)
(
1
2π × CFB × RUPPER || RLOWER
)
where CFB is the capacitance between FB_ and
ground, RUPPER is the upper resistor of the linear
regulator’s feedback divider, and RLOWER is the
lower resistor of the divider.
Next, calculate the zero caused by the output
capacitor’s ESR:
fPOLE _ ESR =
2π × COUT _ LR × VOUT _ LR
fT
hFE
Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and GND (including stray capacitance):
ILOAD(MAX)_ LR
fCROSSOVER = A V _ LR × fPOLE _ LR
2π × CIN × RIN
fPOLE _ IN =
VBE
IBIAS
1
The equation can be further simplified:
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, the pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system. The output capacitor’s
ESR generates a zero. For proper operation, use the
following equations to verify the linear regulator is properly compensated:
1)
gm
h
, RIN = FE ,
2πfT
gm
1
2π × COUT _ LR × RESR
where R ESR is the equivalent series resistance
of COUT_LR.
To ensure stability, choose COUT_LR large enough
so the crossover occurs well before the poles and
zero calculated in steps 2 to 5. The poles in steps 3
and 4 generally occur at several megahertz and
using ceramic capacitors ensures the ESR zero
occurs at several megahertz as well. Placing the
crossover below 500kHz is sufficient to avoid the
amplifier-delay pole and generally works well,
unless unusual component choices or extra capacitances move the other poles or zero below 1MHz.
)
______________________________________________________________________________________
TFT-LCD Power-Supply Controllers
1) Minimize the area of high-current loops. The highcurrent input loop goes from the positive terminals of
the input capacitors to the inductor, to the power
MOSFET, and to the negative terminals of the input
capacitors. The high-current output loop is from the
positive terminals of the input capacitors to the
inductor, to the output diode, and to the positive terminals of the output capacitors, reconnecting
between the output-capacitor and input-capacitor
ground terminals. Connect these loops with short,
wide connections. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in
parallel to reduce resistance and inductance.
2) Create a power ground plane consisting of the input
and output-capacitor ground terminals, the source of
the power MOSFET, and any ground terminals of the
charge-pump components. Connect all of these
together with short, wide traces or a small ground
plane. Maximizing the width of the power ground
traces improves efficiency and reduces output voltage ripple and noise spikes. Create an analog
ground plane consisting of the IC’s backside pad, all
the feedback-divider ground connections, the bufferamplifier-divider ground connection, the REF capacitor ground connection, and the DEL capacitor ground
connection. The power ground plane and the analog
ground plane should be connected at only one loca-
CS-
CS+
IN
GATE
TOP VIEW
FB
Pin Configuration
20
19
18
17
16
1
15
GND
SDFR
2
14
DRVP
*FBPB
3
13
FBP
*OUTB
4
12
*FBG
*SUPB
5
11
*DRVG
7
8
9
10
DEL
DRVN
DRVL
FBL
FBN
6
4) Place all feedback-voltage-divider resistors as close
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near the switching nodes in the step-up regulator and charge pumps.
5) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
6) Minimize the size of the switching node while keeping
it wide and short. Keep the switching node away from
feedback nodes (FB, FBP, FBL, FBG, and FBN) and
analog ground. Use DC traces to shield if necessary.
Refer to the MAX1513 evaluation kit for an example of
proper board layout.
Chip Information
TRANSISTOR COUNT: 4807
PROCESS: BiCMOS
REF
MAX1513
MAX1514
tion, which is the IC’s GND pin. All other ground connections, such as the IN pin bypass capacitor and
the linear-regulator output capacitors, should be starconnected directly to the backside pad of the IC
through a via with wide traces, not otherwise connecting to either the power ground plane or the analog
ground plane. Connect the IC’s backside pad to the
IC’s GND pin. Make no other connections between
the analog and power ground planes.
3) Place IN and REF bypass capacitors as close to the
device as possible.
THIN QFN
4mm x 4mm
*N.C. FOR MAX1514
______________________________________________________________________________________
27
MAX1513/MAX1514
PC Board Layout and Grounding
Careful PC board layout is important for proper operation.
Use the following guidelines for good PC board layout:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
1
2
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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