Infineon IPP50R380CE 500v superjunction mosfet for consumer and lighting application Datasheet

Application Note AN 2012-04
V1.0 April 2012
500V CoolMOSTM CE
500V Superjunction MOSFET for Consumer
and Lighting Applications
IFAT PMM APS SE SL
René Mente
Francesco Di Domenico
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Edition 2011-02-02
Published by
Infineon Technologies Austria AG
9500 Villach, Austria
© Infineon Technologies Austria AG 2012
All Rights Reserved.
Attention please!
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AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY
OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE
MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON
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(INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION
GIVEN IN THIS APPLICATION NOTE.
Information
For further information on technology, delivery terms and conditions and prices please contact your
nearest Infineon Technologies Office (www.infineon.com).
Warnings
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AN 2012-04
Revision History: date (12-04-20), V1.0
Previous Version: none
st
Subjects: 1 revision
Authors: IFAT PMM APS SE SL
René Mente
Francesco Di Domenico
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500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Table of contents
1 Introduction .................................................................................................................................................. 4
1.1
Features and Benefits ........................................................................................................................ 4
1.2
Applications (Target Market) .............................................................................................................. 5
2 Superjunction (SJ) Principle ...................................................................................................................... 5
2.1
General Description ........................................................................................................................... 5
2.2
Superjunction Benefit of 500V CE ..................................................................................................... 7
2.2.1 Switching Speed ............................................................................................................................ 7
2.2.2 BJT (Bipolar Junction Transistor)-Effect ........................................................................................ 9
3 Technology Parameters ............................................................................................................................11
3.1
Gate Charge (Qg) .............................................................................................................................11
3.2
Energy Stored in Output Capacitance (Eoss) ....................................................................................12
4 Measurement Results ...............................................................................................................................13
4.1
Efficiency in CCM PFC ....................................................................................................................13
4.2
Hard Commutation on Conducting Body Diode ...............................................................................15
5 Design Guideline for Using 500V CE .......................................................................................................16
5.1
Minimum External Gate Resistor (RG,ext) .........................................................................................16
5.2
Paralleling of 500V CE .....................................................................................................................16
5.3
Safe Operation after Protection Mode .............................................................................................17
6 Portfolio ......................................................................................................................................................19
7 References .................................................................................................................................................20
3
500V CoolMOSTM CE
1
Application Note AN 2012-04
V1.0 April 2012
Introduction
TM
The new CoolMOS CE is the fourth technology platform of Infineon’s market leading high voltage power
MOSFETs designed according to the revolutionary superjunction (SJ) principle in the 500V class. 500V CE
portfolio provides all benefits of a fast switching superjunction (SJ) MOSFET while keeping ease of use and
implementation. The complete CE series of MOSFETs achieve very low conduction and switching losses,
and can make applications more efficient, more compact, lighter and thermally cooler.
This application note will describe the fundamental differences between a SJ MOSFET and a standard
MOSFET. Additionally, all features and benefits impacting the target applications will be described.
Furthermore, these features will be illustrated from both a theoretical point of view and in hardware
TM
measurements. It will also be shown that CoolMOS CE is a cost effective alternative compared to standard
MOSFETs, which enables reaching higher efficiency levels while offering an attractive price/performance
ratio.
1.1
Features and Benefits
TM
The following table represents the features and benefits of CoolMOS CE in comparison to standard
MOSFETs, which will be discussed in depth in the main part of this application note.
Table 1: features and benefits
FEATURES
BENEFITS
Reduced energy stored in output
capacitance (Eoss)
Reduction of switching losses,
improvement of light load efficiency
High body diode ruggedness
Higher reliability under critical operating
conditions
Reduced reverse recovery charge (Qrr)
Lower possibility of hard commutation in
resonant topologies
Improvement in light load efficiency
Reduced gate charge (Qg)
Lower gate drive capability required
Easy control of switching behavior
Overall Features
Outstanding reliability with proven
TM
CoolMOS quality
4
500V CoolMOSTM CE
1.2
Application Note AN 2012-04
V1.0 April 2012
Applications (Target Market)
The following table represents the target applications and topologies for these new MOSFETs.
Table 2: target applications and topologies
APPLICATION
PFC
PC Silverbox
Boost-Stage
LCD/LED/PDP TV
Boost-Stage
Gaming
Boost-Stage
Lighting
Boost-Stage
PWM
TTF
LLC
LLC
TTF
LLC
LLC
All the features and benefits of the 500V CE in connection with the target applications and topologies will be
analyzed in section 4. The following section will describe the differences between SJ MOSFETs and
standard MOSFETs.
2
Superjunction (SJ) Principle
In the past the consumer market has been dominated by standard MOSFETs. Therefore this chapter is
included to show the difference to SJ MOSFETs.
2.1
General Description
TM
“All CoolMOS series are based on the Superjunction principle, which is a revolutionary technology for high
voltage power MOSFETs [1, 2], Infineon Technologies has been the first company worldwide to
commercialize this idea into the market [4]. Where conventional power MOSFETs just command on one
degree of freedom to master both on-state resistance and blocking voltage, the Superjunction principle
allows two degrees of freedom for this task. Therefore conventional MOSFETs are stuck with the limit of
silicon, a barrier which marks the optimum doping profile for a given voltage class. This limit line has been
theoretically derived by Chen and Hu in the late 80ies [3]. No commercial product has an on-state resistance
better than the limit line of silicon.” [5] Figure 1 represents the area-specific on-resistance versus breakdown
voltage.
5
Area specific resistance [Ω*mm2]
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
40.00
30.00
20.00
State-of the-art
conventional MOS
10.00
"Silicon limit"
CoolMOSTM
0.00
500
600
700
800
900
1000
Blocking voltage [V]
Figure 1: area-specific on-resistance versus breakdown voltage comparison of standard MOSFET
and CoolMOS
TM
technology [6]
“In contrast to that the Superjunction principle allows to reduce the on-state resistance of a high voltage
MOSFET virtually to zero, limited only by technology efforts and manufacturing capabilities.” [5]
“The basic idea is simple: instead of having electrons flowing through a relatively high resistive (high voltage
blocking) n-area, we allow them to flow in a very rich doped n-area, which gives naturally a very low on-state
resistance. The crucial point for the SJ technology is to make the device block its full voltage, which requires
a careful balancing of the additional n-charge by adjacently positioned deep p-columns, which go all the way
straight through the device close to the back side n+ contact. This is where manufacturing capability comes
in, as the charges within the device need to be compensated precisely under the constraints of a mass
market production line.” [5] Figure 2 shows the cross section of a standard MOSFET (left) and a SJ MOSFET
(right).
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500V CoolMOSTM CE
Application Note AN 2012-04
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Figure 2: cross section of standard MOSFET (left) and SJ MOSFET (right) [5]
“The SJ principle gives us the opportunity to create best-in-class types, which have not been possible before
such as a 100 mΩ/600V part in a TO-220 package. Furthermore it allows making parts with very low
capacitances for a given RDS(on) as the silicon chip is much smaller than for a conventional power MOSFET.
Both input and high voltage level of the output capacitance scale directly with the chip size, whereas reverse
capacitance and to some extent the low voltage level of the output capacitance is technology dependent.
Characteristic of all Superjunction devices is a strong non-linearity of the output capacitance with high values
at low voltage and low values at high voltage. This behavior can be easily understood if you take into
account that the output capacitance is proportional to the area of the blocking pn-junction and inverse
proportional to the width of the space charge layer (or the voltage sustaining area). At low voltage the pcolumns are not depleted and form a very big surface, furthermore the width of the space charge layer is
very narrow (the white area seen in” Figure 2). ” At high voltage however the p-columns are fully depleted
and the space charge layer has reached its full extension of roughly 45μm for a 600V device. Important is
that the non-linearity of the output capacitance allows a quasi zero-voltage-switching (ZVS) turn-off of the
device, lowering turn-off losses. Superjunction devices are by nature fast in switching. Very small
capacitances together with a low gate charge make rise and fall times of a few nanoseconds a reality.” [5]
For more information on Superjunction devices please read the article “Mastering the Art of Slowness” which
is available on www.infineon.com.
2.2
Superjunction Benefit of 500V CE
Chapter 2.1 illustrated the general characteristics of a SJ MOSFET in comparison to a standard MOSFET.
Now the question arises “What is the benefit for the 500V CE?” This application note will describe two of the
most important factors starting with the switching speed.
2.2.1 Switching Speed
As mentioned in the general description the switching speed increases dramatically. This behavior comes
from the low parasitic capacitances of a SJ MOSFET in comparison to the standard MOSFET. A SJ
MOSFET has about half of the value of input and output capacitance, which brings the benefits for switching
losses and driving losses. Figure 3 represents these parasitic capacitances (marked in red) in a simplified
schematic.
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500V CoolMOSTM CE
Application Note AN 2012-04
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Figure 3: simplified small signal MOSFET equivalent circuit
Because of this capacitance reduction the Eon and Eoff of the 500V CE is about half in comparison to a
standard MOSFET. Furthermore this reduction of capacitances results also in a reduced gate charge Qg
which gives the benefit of reduced driving losses, and the possibility to use a lower cost driver with less gate
drive capability. Figure 4 represents the capacitance comparison of the 500V CE (280mOhm) vs. a
comparable standard MOSFET.
Capacitances
IPA50R280CE vs. Standard MOSFET
10000
Ciss, Coss, Crss [pF]
1000
IPA50R280CE Ciss
IPA50R280CE Coss
100
IPA50R280CE Crss
standard MOS Ciss
standard MOS Coss
standard MOS Crss
10
1
0
100
200
300
400
500
VDS [V]
Figure 4: capacitance comparison 500V CE vs. standard MOSFET
8
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
“A fundamental characteristic of all Superjunction devices is, that both the output and reverse capacitance
show a strong non-linearity. The non-linearity in Superjunction capacitance characteristics comes from the
fact that at a given voltage – typically in the range of 1/10th of the rated blocking voltage – p- and n-columns
deplete each other leading to a fast expansion of the space charge layer throughout the structure. This
means that at a voltage beyond 50V for 500V rated devices both output and reverse capacitance reach
minimum values of a few pF only, resulting in a dv/dt of more than 100V/ns and di/dt of several thousand
A/μs if the load current is allowed to fully commute into the output capacitance during turn-off. The output
capacitance is charged up to the level of the bus voltage where the voltage rise follows then the formula:
dv / dt 
I load
C oss
(1)
The voltage rise is therefore proportional to the load current Iload and inverse proportional to the value of the
output capacitance Coss. Because of the decreasing Coss towards higher voltages, the highest dv/dt is
reached shortly before reaching the bus voltage. The according di/dt is mainly limited by the inductances of
package and PCB circuit. The highest efficiency can now be reached by turning-off the device in this
manner, because the occurring switching losses can be ideally reduced down to the level of the stored
energy in the output capacitance.” [7]
All these benefits will be clearly visible in the efficiency results, which will be described in chapter 4. The
second difference is the so called BJT-Effect.
2.2.2 BJT (Bipolar Junction Transistor)-Effect
If the body diode conducts in forward direction, minority carriers remaining in the base region during diode
recovery can cause a BJT action with destructive results (short circuit of drain source while high voltages are
applied).
How is it possible to trigger the BJT-Effect? This is shown step by step in the following:
In a zero voltage switching topology the forward
current (ISD) is forced into the body diode to clamp
the output at either the positive or negative rail
following a current driven drain to source transition.
This forward current causes the generation of
minority carriers in both the p doped body
(electrons) and nepi regions (holes).
9
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
The MOSFET channel is turned ON and diverts a
portion of the current through the channel away
from the body diode, that is still forward conducting
(MOSFET can conduct current in both directions).
This lower current flowing through the body diode
will reduce the generation of minority carriers but
will not stop it.
The external circuitry reverses the current flow
through the device -> small amount of reverse
current flows in body diode (small due to the very
weak voltage generated by very low current flowing
in the low resistive channel, especially at light load
operation). Some minority carriers will be removed
from the p-n-junction, but not all due to a
conduction period that is short in relation to the
intrinsic carrier lifetime.
If the MOSFET completely turns ON the current will
be completely diverted to the channel, but if the
MOSFET turns OFF when there are still minority
carriers in the body diode the following happens:
The MOSFET will begin to block voltage imposing a
higher reverse voltage on the body diode, with high
dv/dt. The application of high reverse voltage on the
body diode will sweep the remaining carriers across
the junction very quickly. Minority carriers in the nepi
region are swept towards the p+ body. -> if this
current (flowing into RB, represented in Figure 5)
reaches a magnitude sufficient to activate the
intrinsic bipolar transistor, second breakdown will
occur destroying the MOSFET.
In a conventional MOSFET the hole current, fed by reverse recovery charge, flow laterally into the p doped
region crossing the area below the n region before they reach the top side of the device below the gate
electrode: so this current flows through RB of the parasitic bipolar structure, with the risk of forward biasing of
npn-junction and consequent triggering of parasitic BJT.
10
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Figure 5: BJT-Effect
TM
As visible in Figure 5 (right) in a CoolMOS the hole current flows upwards through the p doped column,
before it reaches the metalized contact, but no lateral current will pass through the p doped well and
therefore no current flows through RB reducing the possibility of triggering the BJT-Effect to nearly zero.
Now that the basics of the SJ MOSFET have been discussed, this paper is going to continue with technology
parameters and their influence on the applications in the specific topologies.
3
Technology Parameters
3.1
Gate Charge (Qg)
One of the most important improvements is the Q g reduction which brings benefits especially in light load
conditions due to reduced driving losses. In general the 500V CE has about 40% Q g reduction in comparison
to an comparable standard MOSFET over the whole R DS(on) range. Figure 6 shows the Qg in nC of the 500V
CE against a standard MOSFET over the RDS(on),max range from 190mΩ to 950mΩ.
11
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
500V CE vs. Standard MOS
typical Qg * RDS(on),max [nC*Ω]
350
300
Qg [nC]
250
200
~40% Qg reduction
500V CE
150
standard MOS
100
50
0
0
200
400
600
800
1000
RDS(on),max [mΩ]
Figure 6: Qg comparison 500V CE vs. standard MOSFET
3.2
Energy Stored in Output Capacitance (Eoss)
The reduced energy stored in the output capacitance brings the most important difference in hard switching
topologies but nevertheless it affects also the switching losses in a resonant topology. Normally it is possible
to choose between zero voltage switching (ZVS) or zero current switching (ZCS). In these two cases it is
possible to eliminate the turn-on losses (ZVS) or the turn-off losses (ZCS), but it is not possible to work in
these two operation modes at the same time. Normally for MOSFETs the ZVS operation is preferred due to
the usually important contribution of the output capacitance to the turn-on losses (if hard switching).
Therefore, one part of the switching losses is still always in action and the reduction of Eoss brings a
reduction of those switching losses. Figure 7 represents the Eoss comparison between the 500V CE and a
comparable standard MOSFET of the 500mΩ devices.
12
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
IPP50R500CE vs. Standard MOS
EOSS comparison of 500mOhm devices
10
9
8
IPP50R500CE
EOSS [µJ]
7
6
standard MOS
5
4
3
2
1
0
0
100
200
300
400
500
600
VDS [V]
Figure 7: Eoss comparison 500V CE vs. standard MOSFET
The Eoss loss is in direct proportion to the output capacitance as a function of drain to source voltage of the
MOSFET. In this case the effect of a reduction of Coss is clearly visible. One further benefit out of this is a
faster VDS transition time in resonant topologies, which means that it is possible to reduce the resonant
inductance and circulating current loss, because it is possible to completely discharge the Coss with lower
currents.
4
Measurement Results
In order to show the impact of the mentioned technology parameters this section will describe some
measurements starting with the efficiency comparison in a CCM PFC, which is one of the most suitable
topologies to verify the new MOSFETs in hard switching.
4.1
Efficiency in CCM PFC
In this measurement the 500V CE is compared to a comparable standard MOSFET in the 280mΩ RDS(on)
range.
Setup parameters:

CCM PFC

Vin=90VAC

Vout=400VDC

Pout=0W to 400W

Frequency=100kHz

RG,ext=5Ω

Ambient temperature 25°C

Heat sink temperature preheated to 60°C

Plug and play scenario between 500V CE and standard MOSFET
13
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Figure 8: 500V CE vs. standard MOSFET comparison in absolute efficiency (upper) and delta
efficiency (lower)
This plug and play measurement shows the benefit of a SJ MOSFET in comparison to a standard MOSFET.
In light load condition (~40W). Due to the Qg reduction an efficiency difference in light load operation (~40W)
of more than 0.9% is visible. The efficiency of the IPP50R280CE is on average 0.4% higher than the
comparable standard MOSFET over the whole load range. Here also the effects of the lower Eon and Eoff are
visible.
Figure 9 represents the Eon and Eoff values of an IPA50R500CE in comparison to a comparable standard
MOSFET over RG,ext at different drain currents (ID) and test ambient temperature (TC) of 25°C.
14
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Eoff - IPA50R500CE vs. Standard MOSFET
Eon - IPA50R500CE vs. Standard MOSFET
ID=2.93A; TC=25°C
ID=2.93A; TC=25°C
14
12
Eon [µJ]
Eoff [µJ]
10
8
6
IPA50R500CE
4
standard MOSFET
2
0
0
5
10
15
20
RG,ext [Ω]
25
30
20
18
16
14
12
10
8
6
4
2
0
35
IPA50R500CE
standard MOSFET
0
5
10
15
20
RG,ext [Ω]
25
30
Eoff - IPA50R500CE vs. Standard MOSFET
Eon - IPA50R500CE vs. Standard MOSFET
ID=5.85A; TC=25°C
ID=5.85A; TC=25°C
30
35
40
35
25
30
Eon [µJ]
Eoff [µJ]
20
15
IPA50R500CE
10
20
15
IPA50R500CE
10
standard MOSFET
5
25
standard MOSFET
5
0
0
0
5
10
15
20
RG,ext [Ω]
25
30
35
0
5
10
15
20
RG,ext [Ω]
25
30
35
Figure 9: Eon and Eoff comparison IPA50R500CE vs. standard MOSFET at ID=2.93A (upper) and
ID=5.85A (lower)
It is shown that the Eon and Eoff are much lower on the 500V CE. Furthermore, it is visible that due to the
differences in the Eoff behavior, it is possible to reduce the switching losses in comparison to the standard
MOSFET both in hard switching DCM Mode PFC and soft switching/resonant topologies where the turn-off
losses are dominant. Especially at higher loads it is visible that the reduction to for example 4Ω RG,ext brings
you about 5µJ lower Eoff.
4.2
Hard Commutation on Conducting Body Diode
Higher switching speeds could also cause drawbacks in case of, for example, high di/dt which could provoke
high voltage peaks during hard commutation on a conducting body diode. The following figure represents
this voltage peaks in comparison to a comparable standard MOSFET at hard commutation followed after 2µs
body diode conduction time (under normal operation conditions you will not find longer body diode
conduction times than 400ns).
15
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
IPP50R500CE vs. Standard MOS
hard commutation on conducting body diode; half bridge configuration;
high side MOS = low side MOS; same RG,sum=5Ω
VDS,max, maximum VDS due to high dIrr/dt [V]
500
490
480
470
460
450
IPP50R500CE
440
standard MOS
430
420
410
400
0
1
2
3
4
5
6
7
IF, forward current through body diode [A]
Figure 10: hard commutation on conduction body diode
It is shown in Figure 10 that the maximum VDS has lower or the same values as the slower standard MOS. In
other words the 500V CE has the same or, even better, behavior than the comparable standard MOSFET
due to the self-limiting dv/dt behavior of this SJ MOSFET family.
These two measurements and the technology parameters show that the 500V CE brings benefits in hard
switching topologies and in soft switching topologies.
The following chapter will represent an important design guideline for using these SJ MOSFETs.
5
Design Guideline for Using 500V CE
5.1
Minimum External Gate Resistor (RG,ext)
The RG,int (internal gate resistor) is defined in the datasheets nevertheless it is recommended to use an RG,ext
(external gate resistor) with a value higher than 2Ω.
5.2
Paralleling of 500V CE
For paralleling 500V CE, the use of ferrite beads on the gate or separate totem poles is generally
recommended.
16
500V CoolMOSTM CE
5.3
Application Note AN 2012-04
V1.0 April 2012
Safe Operation after Protection Mode
This chapter is going to describe one design guideline which should be followed as a safety precaution. This
guide should be followed when using the 500V CE in a LLC topology in combination with a controller with
auto-restart after any kind of protection (over voltage protection (OVP), over current protection (OCP), over
power protection (OPP), etc.). If the controller is used in the application with a complete latch-off protection
(system has to be manually restarted) this guideline is not applicable.
In order to provide safe operation the pause time between occurring of a protection state and auto-restart (in
this document named as pause time tp_restart) should be set with respect to the following equation.
t p _ restart  Lr  5H  
t p _ restart
Lr
IS
VF
0.5  I S
VF
s 
…
pause time between occurring of protection state and auto-restart
H 
A
V 
…
resonant inductance or leakage inductance of main transformer
…
continuous forward current of body diode
…
forward voltage of body diode
(2)
The following figure represents a simplified schematic that represents an LLC half bridge and the tp_restart in
correspondence of the gate signal.
17
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
Figure 11: simplified circuitry for LLC half bridge and corresponding gate drive signal with autorestart
TM
Last but not least the next chapter is going to illustrate the 500V CoolMOS
portfolio.
18
CE naming system and product
500V CoolMOSTM CE
6
Application Note AN 2012-04
V1.0 April 2012
Portfolio
TM
500V CoolMOS CE series follows the same naming guidelines as already established with the CP series
e.g. IPP50R500CE:
I
P
P
50
R500
CE
…
…
…
…
…
…
Infineon Technologies
power MOSFET
package type (TO-220)
voltage class divided by 10
on-state resistance in milli Ohms
name of the series
Figure 12: portfolio 500V CoolMOS
19
TM
CE series
500V CoolMOSTM CE
Application Note AN 2012-04
V1.0 April 2012
7
References
[1]
T. Fujihira: “Theory of Semiconductor Superjunction Devices”, Jpn. J. Appl. Phys., Vol.36, pp. 62546262, 1997
A.W. Ludikhuize: “A review of the RESURF technology”, Proc. ISPSD 2000, pp. 11-18
X. B. Chen and C. Hu, “Optimum doping profile of power MOSFET’s epitaxial Layer.”, IEEE Trans.
Electron Devices, vol. ED-29, pp. 985-987, 1982
G. Deboy, F. Dahlquist, T. Reiman and M. Scherf: “Latest generation of Superjunction power
MOSFETs permits the use of hard-switching topologies for high power applications”, Proceedings of
PCIM Nürnberg, 2005, pp. 38-40
TM
G. Deboy, L. Lin, R. Wu: “CoolMOS C6 Mastering the Art of Slowness”, Application Note revision
1.0 2009-12-21, pp. 5-6
TM
IFX: “CoolMOS 900V – New 900V class for superjunction devices – A new horizon for SMPS and
renewable energy applications”, Application Note revision 1.0 2008-02, pp. 6, figure 1
Dr. H. Kapels: “Superjunction MOS devices – From device development towards system
optimization”, paper EPE 2009 – Barcelona, ISBN 9789075815009, pp. 3
[2]
[3]
[4]
[5]
[6]
[7]
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