HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 1 Dual-Channel Line Receiver Hermetically Sealed Optocoupler Data Sheet Description Features The HCPL-193x devices are dual-channel, hermetically sealed, high CMR, line receiver optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either a commercial product or with full MIL-PRF-38534 Class Level H or K testing, or from the DLA Standard Microcircuit Drawing (SMD) 5962-89572. This 16-pin DIP may be purchased with a variety of lead bend and plating options. See Selection Guide — Lead Configuration Options for details. Standard Microcircuit Drawing (SMD) parts are available for each lead style. CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD) Manufactured and tested on a MIL-PRF-38534 certified line QML-38534, Class H and Class K Hermetically sealed 16-pin dual in-line package Performance guaranteed over full military temperature range: –55° C to +125° C High speed: 10 Mb/s Accepts a broad range of drive conditions Adaptive line termination included Internal shield provides excellent common mode rejection External base lead allows LED Peaking and LED current adjustment 1500 Vdc withstand test voltage High radiation immunity HCPL-2602 function compatibility Reliability data available Applications 1. See Selection Guide — Lead Configuration Options for available extensions. Broadcom -1- Military and space High reliability systems Isolated line receiver Simplex/multiplex data transmission Computer-peripheral interface Microprocessor system interface Harsh environmental environments Digital isolation for A/D, D/A conversion Current sensing Instrument input/output isolation Ground loop elimination Pulse transformer replacement HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Functional Diagram Selection Guide — Lead Configuration Options Part Number and Options Commercial HCPL-1930 MIL-PRF-38534 Class H HCPL-1931 MIL-PRF-38534 Class K HCPL-193K Standard Lead Finisha Gold Solder Dippedb Option #200 Butt Joint/Gold Platea Option #100 Gull Wing/Solderedb Option #300 Crew Cut/Gold Platea Option #600 Class H SMD Part Number Truth Table (Positive Logic) Prescript for all below 5962- Gold Platea 8957201EC Solder Dippedb 8957201EA Butt Joint/Gold Platea 8957201YC Input Enable Output On H L Off H H Butt Joint/Solderedb 8957201YA On L H Gull Wing/Solderedb 8957201XA Off L H Crew Cut/Gold Platea Available Crew Cut/Solderedb Available NOTE The connection of a 0.1-μF bypass capacitor between pins 15 and 10 is recommended. Class K SMD Part Number All devices are manufactured and tested on a MIL-PRF-38534 certified line and Class H and K devices are included in the DLA Qualified Manufacturers List QML-38534 for Hybrid Microcircuits. Each unit contains two independent channels, consisting of a GaAsP light emitting diode, an input current regulator, and an integrated high gain photon detector. The input regulator serves as a line termination for line receiver applications. It clamps the line voltage and regulates the LED current so line reflections do not interfere with circuit performance. The regulator allows a typical LED current of 12.5 mA before it starts to shunt excess current. The output of the detector IC is an open collector Schottky clamped transistor. An enable input gates the detector. The internal detector shield provides a guaranteed common mode transient immunity specification of +1000 V/μs. Prescript for all below 5962- Gold Platea 8957202KEC Solder Dippedb 8957202KEA Butt Joint/Gold Platea 8957202KYC Butt Joint/Solderedb 8957202KYA Gull Wing/Solderedb 8957202KXA a. Gold Plate lead finish: Maximum gold thickness of leads is <100 micro inches. Typical is 60 to 90 micro inches. b. Solder lead finish: Sn63/Pb37. DC specifications are compatible with TTL logic and are guaranteed from –55°C to +125°C allowing trouble-free interfacing with digital logic circuits. An input current of 10 mA will sink a six gate fan-out (TTL) at the output with a typical propagation delay from input to output of only 45 ns. Broadcom -2- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Outline Drawings 16-Pin DIP Through Hole, 2 Channels 0.89 (0.035) 1.65 (0.065) 20.06 (0.790) 20.83 (0.820) 8.13 (0.320) MAX. 4.45 (0.175) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 2.29 (0.090) 2.79 (0.110) 7.36 (0.290) 7.87 (0.310) 0.51 (0.020) MAX. Note: Dimensions in millimeters (inches). Device Marking Avago DESIGNATOR Avago P/N DLA SMD[1] DLA SMD[1] PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX 50434 0.20 (0.008) 0.33 (0.013) COMPLIANCE INDICATOR,[1] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE[1] [1] QML PARTS ONLY Broadcom -3- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Hermetic Optocoupler Options Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H, and Class K product. 4.32 (0.170) MAX. 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MIN. 1.14 (0.045) 1.40 (0.055) 2.29 (0.090) 2.79 (0.110) 7.36 (0.290) 7.87 (0.310) 0.51 (0.020) MAX. 200 Lead finish is solder dipped rather than gold plated. This option is available on Commercial, Class H, and Class K product. DLA Drawing (SMD) part numbers contain provisions for lead finish. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercial, Class H, and Class K product. This option has solder-dipped leads. 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 600 1.40 (0.055) 1.65 (0.065) 5° MAX. 0.51 (0.020) MAX. 9.65 (0.380) 9.91 (0.390) 4.57 (0.180) MAX. 1.07 (0.042) 1.32 (0.052) Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H, and Class K product. Contact factory for the availability of this option on DLA part types. 3.81 (0.150) MIN. 0.51 (0.020) MIN. 0.20 (0.008) 0.33 (0.013) 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.25 (0.049) Note: Dimensions in millimeters (inches). Broadcom -4- 7.36 (0.290) 7.87 (0.310) HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature TS –65 +150 °C Operating Temperature TA –55 +125 °C — 260 for 10 sec °C Forward Input Current (each channel) II — 60 mA Reverse Input Current IR — 60 mA Supply Voltage (1 minute max) VCC — 7.0 V Enable Input Voltage (each channel) VE — b Output Collector Current (each channel) IO — 5.5 25 mA Output Collector Power Dissipation (each channel) PO — 40 mW Output Collector Voltage (each channel) VO Lead Solder Temperature — 7 V — 564 mW Input Power Dissipation (each channel) — 168 mW Derate linearly at 1.2 mA/°C above TA = 100°C. b. Not to exceed VCC by more than 500 mV. a V Total Package Power Dissipation a. Note Schematic Notes: The connection of a 0.1-μF bypass capacitor between pins 15 and 10 is recommended. Bypassing of the power supply line is required, with a 0.1-μF ceramic disc capacitor adjacent to each isolator. The power supply bus for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to suppress regenerative feedback via the power supply. ESD Classification (MIL-STD-883, Method 3015) , Class 1 Broadcom -5- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Recommended Operating Conditions Parameter Symbol Min Max Unit Input Current, Low Level IIL 0 250 μA Input Current, High Levela IIH 12.5 60 mA Supply Voltage, Output VCC 4.5 5.5 V High Level Enable Voltage VEH 2.0 VCC V Low Level Enable Voltage VEL 0 0.8 V Fan Out (at RL = 4 kΩ) N — 5 TTL Loads Operating Temperature TA –55 125 °C a. 12.5-mA condition permits at least 20% guardband for optical coupling variation. Initial switching threshold is 10 mA or less. Electrical Specifications TA = –55°C to 125°C unless otherwise stated. Parameter Symbol Test Conditions Limits Group A Subgroupsa Min Typb Max Unit Fig Note High Level Output Current IOH VCC = 5.5V, VO = 5.5V II = 250 μA, VE = 2.0V 1, 2, 3 — 20 250 μA 3 c Low Level Output Voltage VOL VCC = 5.5V; II = 10 mA VE = 2.0V, IOL (Sinking) = 10 mA 1, 2, 3 — 0.3 0.6 V 1 c VI II = 10 mA 1, 2, 3 — 2.2 2.6 V 2 c — 2.35 2.75 Input Voltage II = 60 mA Input Reverse Voltage VR IR = 10 mA 1, 2, 3 — 0.8 1.10 V c Low Level Enable Current IEL VCC = 5.5V, VE = 0.5V 1, 2, 3 — –1.45 –2.0 mA c High Level Enable Current IEH VCC = 5.5V, VE = 1.7V 1, 2, 3 — — –1.5 mA c High Level Enable Voltage VEH — 1, 2, 3 2.0 — — V c, d Low Level Enable Voltage VEL — 1, 2, 3 — — 0.8 V c High Level Supply Current ICCH VCC = 5.5V; II = 0, VE = 0.5V both channels 1, 2, 3 — 21 28 mA Low Level Supply Current ICCL VCC = 5.5V; II = 60 mA, VE = 0.5V both channels 1, 2, 3 — 27 36 mA Input-Output Insulation Leakage Current II-O Relative Humidity ≤ 65, t = 5s, VI-O = 1500 Vdc 1 — — 1 μA Propagation Delay Time to High Output Level tPLH RL = 510Ω; CL = 50 pF, II = 13 mA,VCC = 5.0 V 9 — 55 100 ns 10, 11 — — 140 Broadcom -6- e 4, 5 c, f HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Parameter Data Sheet Symbol Propagation Delay Time to Low Output Level Test Conditions tPHL RL = 510Ω; CL = 50 pF, II = 13 mA, VCC = 5.0V Limits Group A Subgroupsa Min Typb Max 9 — 60 100 10, 11 — — 120 Unit Fig Note ns 4, 5 c, g Common Mode Transient Immunity at High Output Level |CMH| VCM = 50V (peak), VO (min.) = 2V, RL = 510Ω; II = 0 mA, VCC = 5.0V 9, 10, 11 1000 10,000 — V/μs 8, 9 c, h, i Common Mode Transient Immunity at Low Output Level |CML| VCM = 50V (peak), VO (max.) = 0.8V, RL = 510Ω; II = 10 mA, VCC = 5.0V 9, 10, 11 1000 10,000 — V/μs 8, 9 c, j, i a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). Class H and K parts receive 100% testing at 25, 125, and -55° C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typical values are at VCC = 5V, TA = 25°C. c. Each channel. d. No external pull-up is required for a high logic state on the enable input. e. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together. f. The tPLH propagation delay is measured from the 6.5-mA point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse. g. The tPHL propagation delay is measured from the 6.5-mA point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse. h. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output remains in a high logic state, i.e., VOUT > 2.0V. i. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the limits specified for all lots not specifically tested. j. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output remains in a low logic state, i.e., VOUT < 0.8V. Typical Specifications TA = 25°C, VCC = 5V. Parameter Symbol Typ Unit Test Conditions Fig. Note Resistance (Input-Output) RI-O 1012 Ω VI-O = 500 Vdc a, b Capacitance (Input-Output) CI-O 1.7 pF f = 1 MHz a, b Input-Input Insulation Leakage Current II-I 0.5 nA ≤65% Relative Humidity, VI-I = 500 Vdc, t = 5s c Resistance (Input-Input) RI-I 1012 Ω VI-I = 500 Vdc c Capacitance (Input-Input) CI-I 0.55 pF f = 1 MHz c Propagation Delay Time of Enable from VEH to VEL tELH 35 ns Propagation Delay Time of Enable from VEL to VEH tEHL 35 ns RL = 510Ω, CL = 15 pF, II = 13 mA, VEH = 3V, VEL = 0V Output Rise Time (10% to 90%) tr 30 ns RL = 510Ω, CL = 15 pF, II = 13 mA Output Fall Time (90% to 10%) tf 24 ns Input Capacitance CI 60 pF 6, 7 a, d 6, 7 a, e a a f = 1 MHz, VI = 0, PINS 1 to 2 or 5 to 6 a. Each channel. b. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together. a c. Measured between adjacent input leads shorted together, i.e., between 1, 2, and 4 shorted together and pins 5, 6, and 8 shorted together. d. The tELH enable propagation delay is measured from the 1.5V point on the trailing edge of the enable input pulse to the 1.5V point on the trailing edge of the output pulse. e. The tEHL enable propagation delay is measured from the 1.5V point on the leading edge of the enable input pulse to the 1.5V point on the leading edge of the output pulse. Broadcom -7- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Figure 1 Input-Output Characteristics Figure 2 Input Characteristics Figure 3 High Level Output Current vs. Temperature Figure 4 Propagation Delay vs. Temperature Figure 5 Enable Propagation Delay vs. Temperature Broadcom -8- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Figure 6 Test Circuit for tPHL and tPLH Figure 7 Test Circuit for tEHL and tELH Broadcom -9- HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Figure 8 Typical Common Mode Transient Immunity Figure 9 Test Circuit for Common Mode Transient Immunity and Typical Waveforms 1 A 2 B 3 IIN VIN 16 VCC 15 14 4 13 5 12 6 11 7 GND 10 8 5V 510 : OUTPUT VO MONITORING 0.01 μF NODE BYPASS 9 VCM + – PULSE GEN. Figure 10 Burn In Circuit VOUT +2.6 V VCC +5.5 V 100 : 100 : VIN +5.0 V 1 16 2 15 3 14 4 13 5 12 6 11 – 7 10 + 8 9 200 : 200 : 0.01 PF TA = +125 °C CONDITIONS: II = 30 mA IO = 10 mA VCC = 5.5 V Broadcom - 10 - HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Application Circuits Figure 11 Polarity Non-Reversing Figure 12 Polarity Reversing, Split Phase Broadcom - 11 - HCPL-1930, HCPL-1931, HCPL-193K, 5962-89572 Data Sheet Figure 13 Flop-Flop Configurations Broadcom - 12 - For product information and a complete list of distributors, please go to our web site: www.broadcom.com. Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom in the United States, certain other countries and/or the EU. Copyright © 2005-2017 Broadcom. All Rights Reserved. The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV02-3843EN – February 8, 2017