Revised November 1999 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs General Description Features The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems. ■ ICC and IOZ reduced by 50% ■ Multiplexer expansion by tying outputs together ■ Inverting 3-STATE outputs ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT258SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide 74ACT258SJ 74ACT258MTC MTC16 74ACT258PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description S Common Data Select Input OE 3-STATE Output Enable Input I0a–I0d Data Inputs from Source 0 I1a–I1d Data Inputs from Source 1 Za–Zd 3-STATE Inverting Data Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009950 www.fairchildsemi.com 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs November 1988 74ACT258 Truth Table Output Functional Description Select The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Data Outputs Enable Input Inputs OE S I0 I1 Z H X X X Z L H X L H L H X H L Za = OE • (I1a • S + I0a • S) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Zb = OE • (I1b • S + I0b • S) Zc = OE • (I1c • S + I0c • S) Zd = OE • (I1d • S + I0d • S) When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA 1.5 mA VI = VCC − 2.1V V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current VI = VCC, GND VI = VIL, VIH VO = VCC, GND ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA Supply Current 0.6 IOL = 24 mA (Note 2) 5.5 4.0 VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT258 Absolute Maximum Ratings(Note 1) 74ACT258 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 4) Min Typ Max Min Max 5.0 2.0 6.5 8.5 1.5 9.5 ns 5.0 2.0 5.5 7.5 1.5 8.0 ns 5.0 3.0 7.5 10.5 2.0 11.5 ns 5.0 1.5 7.0 9.5 1.5 11.0 ns Propagation Delay tPLH In to Zn tPHL Propagation Delay In to Zn tPLH Propagation Delay S to Zn tPHL Propagation Delay S to Zn tPZH Output Enable Time 5.0 2.0 6.5 8.5 1.5 9.5 ns tPZL Output Enable Time 5.0 2.0 6.5 8.5 1.5 9.5 ns tPHZ Output Disable Time 5.0 1.5 7.0 9.0 1.0 10.0 ns tPLZ Output Disable Time 5.0 2.0 6.0 8.0 1.5 9.0 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 55.0 pF V CC = 5.0V www.fairchildsemi.com 4 Conditions 74ACT258 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 5 www.fairchildsemi.com 74ACT258 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74ACT258 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com 74ACT258 Quad 2-Input Multiplexer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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