IDT IDT74ALVCHS162830DF 3.3v cmos 1-bit to 2-bit address driver with 3-state outputs and bus-hold Datasheet

IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
3.3V CMOS 1-BIT TO 2-BIT
ADDRESS DRIVER WITH
3-STATE OUTPUTS AND
BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCHS162830
DESCRIPTION:
FEATURES:
This 1-bit to 2-bit address driver is built using advanced dual metal CMOS
technology. Diodes to VCC have been added on the inputs to clamp
overshoot.
The ALVCHS162830 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCHS162830 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in TVSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
V CC
OE 2
21
V CC
OE 1
20
V CC
A1
5
1Y 1
7
4
2Y 1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC-4718/2
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2)
Max
Unit
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
2Y2
1
80
1Y3
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
1Y2
2
79
2Y3
TSTG
Storage Temperature
–65 to +150
°C
GND
3
78
GND
IOUT
DC Output Current
–50 to +50
mA
2Y1
4
1Y4
IIK
±50
mA
1Y1
5
76
2Y4
Continuous Clamp Current,
VI < 0 or VI > VCC
VCC
6
75
VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
77
A1
7
74
1Y5
A2
8
73
2Y5
GND
9
72
GND
A3
10
71
1Y6
A4
11
70
2Y6
GND
12
69
GND
A5
13
68
1Y7
A6
14
67
2Y7
VCC
15
66
VCC
A7
16
65
1Y8
CIN
Input Capacitance
VIN = 0V
5
7
pF
A8
17
64
2Y8
COUT
Output Capacitance
VOUT = 0V
7
9
pF
GND
18
63
GND
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
A9
19
62
1Y9
OE1
20
61
2Y9
OE2
21
60
1Y10
A10
22
59
2Y10
GND
23
58
GND
Pin Names
A11
24
57
1Y11
OEx
3-State Output Enable Inputs (Active LOW)
A12
25
56
2Y11
Ax
Data Inputs(1)
VCC
26
55
VCC
xYx
3-State Outputs
A13
27
54
1Y12
A14
28
53
2Y12
GND
29
52
GND
A15
30
51
1Y13
A16
31
50
2Y13
GND
32
49
GND
OE1
OE2
Ax
1Yx
2Yx
A17
33
48
1Y14
L
H
H
H
Z
A18
34
47
2Y14
L
H
L
L
Z
VCC
35
46
VCC
H
L
H
Z
H
2Y18
36
45
1Y15
H
L
L
Z
L
1Y18
37
44
2Y15
L
L
H
H
H
GND
38
43
GND
L
L
L
L
L
2Y17
39
42
1Y16
H
H
X
Z
Z
1Y17
40
41
2Y16
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Description
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE(1)
Inputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
TVSOP
TOP VIEW
2
Outputs
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
– 45
—
—
45
—
—
—
±500
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
Bus-Hold Input Sustain Current
VCC = 3V
Bus-Hold Input Sustain Current
VCC = 2.3V
Bus-Hold Input Overdrive Current
VCC = 3.6V
VI = 2V
IBHL
IBHH
IBHL
IBHHO
VI = 0.7V
VI = 0 to 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
—
µA
µA
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
VCC = 2.7V
VOL
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
IOH = – 4mA
1.9
—
IOH = – 6mA
1.7
—
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
VCC = 3V
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
VCC = 2.7V
VCC = 3V
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Driver Outputs enabled
CPD
Power Dissipation Capacitance per Driver Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
49
53
pF
6
7.5
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
VCC = 2.7V
VCC = 3.3V ± 0.3V
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
1.2
3.8
—
4
1.7
3.5
ns
1
5.7
—
5.7
1
4.8
ns
1
4.9
—
5.4
1.7
5.2
ns
—
—
—
—
—
500
ps
tPLH
Propagation Delay
tPHL
Ax to xYx
tPZH
Output Enable Time
tPZL
OEx to xYx
tPHZ
Output Disable Time
tPLZ
OEx to xYx
tSK(O)
Output Skew(2)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
(1, 2)
tPHL
V IH
VT
0V
ALVC Link
DISABLE
ENABLE
CONTROL
INPUT
GND
tPZL
D.U.T.
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500 Ω
RT
t PLH
CL
ALVC Link
Test Circuit for All Outputs
V OH
VT
V OL
Propagation Delay
V OUT
Pulse
Generator
t PHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500 Ω
tPLH
OUTPUT
V LOAD
V CC
V IN
V IH
VT
0V
SAME PHASE
INPUT TRANSITION
tPLZ
V IH
VT
0V
V LOAD/2
V LOAD/2
VT
V LZ
V OL
tPHZ
VT
V OH
V HZ
0V
0V
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V IH
DATA
VT
INPUT
0V
tSU
tH
V IH
TIMING
VT
INPUT
0V
tREM
V IH
ASYNCHRONOUS
VT
CONTROL
0V
V IH
SYNCHRONOUS
VT
CONTROL
tSU
0V
tH
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other Tests
Open
ALVC Link
Set-up, Hold, and Release Times
V IH
INPUT
VT
0V
tPHL1
tPLH1
V OH
OUTPUT 1
tSK (x)
LOW-HIGH-LOW
PULSE
VT
V OL
tSK (x)
tW
V OH
VT
V OL
OUTPUT 2
VT
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tPHL2
Pulse Width
tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCHS162830
3.3V CMOS 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
ALVC X
IDT
XX
Bus-Hold
Temp. Range
XXX
Family
XX
XXX
Device Type Package
DF
DFG
Thin Very Small Outline Package
TVSOP - Green
830
1-Bit to 2-Bit Address Driver with 3-State Outputs
S162 Double-Density with Resistors and Clamps to VCC, ±12mA
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
H
Bus-Hold
74
–40°C to +85°C
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
6
for Tech Support:
[email protected]
(408) 654-6459
Similar pages