Fairchild FQU5N50C 500v n-channel mosfet Datasheet

TM
FQD5N50C / FQU5N50C
500V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction, electronic lamp ballasts
based on half bridge topology.
•
•
•
•
•
•
4.0A, 500V, RDS(on) = 1.4 Ω @VGS = 10 V
Low gate charge ( typical 18nC)
Low Crss ( typical 15pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
D
!
●
◀
G
S
G!
I-PAK
D-PAK
FQD Series
G D S
▲
●
●
FQU Series
!
S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
FQD5N50C / FQU5N50C
500
Units
V
4
A
- Continuous (TC = 100°C)
2.4
A
16
A
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
(Note 2)
IAR
Avalanche Current
(Note 1)
4
A
EAR
(Note 1)
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C)*
4.8
4.5
2.5
mJ
V/ns
W
PD
Power Dissipation (TC = 25°C)
48
0.38
-55 to +150
W
W/°C
°C
300
°C
TJ, TSTG
TL
- Pulsed
(Note 1)
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
± 30
V
300
mJ
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
-
Max
2.6
Units
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient *
-
50
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
-
110
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
QFET
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
500
--
--
V
--
0.5
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = 500 V, VGS = 0 V
--
--
1
µA
VDS = 400 V, TC = 125°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
2.0
--
4.0
V
--
1.14
1.4
Ω
--
5.2
--
S
--
480
625
pF
--
80
105
pF
--
15
20
pF
--
12
35
ns
--
46
100
ns
--
50
110
ns
--
48
105
ns
--
18
24
nC
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 2.0A
gFS
Forward Transconductance
VDS = 40 V, ID = 2.0A
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 250 V, ID = 5A,
RG = 25 Ω
(Note 4, 5)
VDS = 400 V, ID = 5A,
VGS = 10 V
(Note 4, 5)
--
2.2
--
nC
--
9.7
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
4
A
ISM
--
--
16
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 4 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
263
--
ns
Qrr
Reverse Recovery Charge
--
1.9
--
µC
VGS = 0 V, IS = 5 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 21.5 mH, IAS = 5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 5A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
Electrical Characteristics
FQD5N50C / FQU5N50C
Typical Characteristics
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
Top :
ID, Drain Current [A]
10
1
10
ID, Drain Current [A]
1
0
10
o
150 C
o
25 C
o
0
-55 C
10
※ Notes :
1. VDS = 40V
2. 250μ s Pulse Test
※ Notes :
1. 250μ s Pulse Test
2. TC = 25℃
-1
10
-1
10
-1
0
10
2
1
10
10
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
4.5
1
10
3.5
IDR, Reverse Drain Current [A]
VGS = 10V
3.0
2.5
2.0
VGS = 20V
1.5
1.0
150℃
※ Notes :
1. VGS = 0V
2. 250μ s Pulse Test
25℃
※ Note : TJ = 25℃
-1
0.5
0
5
10
15
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
1200
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1000
12
10
800
Capacitance [pF]
0
10
Ciss
Coss
600
400
※ Notes ;
1. VGS = 0 V
2. f = 1 MHz
Crss
200
VGS, Gate-Source Voltage [V]
RDS(ON) [Ω ],
Drain-Source On-Resistance
4.0
VDS = 100V
VDS = 250V
8
VDS = 400V
6
4
2
※ Note : ID = 5A
0
0
-1
10
0
10
1
10
0
5
10
15
20
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
Typical Characteristics
(Continued)
1.2
3.0
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
RDS(ON) , (Normalized)
Drain-Source On-Resistance
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μ A
0.9
0.8
-100
-50
0
50
100
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 2 A
0.5
150
0.0
-100
200
-50
0
50
100
150
200
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
5
2
10
Operation in This Area
is Limited by R DS(on)
100 µs
ID, Drain Current [A]
ID, Drain Current [A]
4
10 µs
1
10
1 ms
10 ms
100 ms
DC
0
10
3
2
-1
10
※ Notes :
1
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10
0
1
10
2
10
0
25
3
10
10
50
75
VDS, Drain-Source Voltage [V]
125
150
Figure 10. Maximum Drain Current
vs Case Temperature
Figure 9. Maximum Safe Operating Area
D = 0 .5
10
0
0 .2
0 .1
0 .0 5
10
-1
※ N o te s :
1 . Z θ J C ( t) = 2 .6 ℃ /W M a x .
2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C ( t)
0 .0 2
0 .0 1
Z
θ JC
(t), T h e rm a l R e s p o n s e
100
TC, Case Temperature [℃]
PDM
s in g le p u ls e
t1
t2
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2003 Fairchild Semiconductor Corporation
ID (t)
VDS (t)
VDD
tp
Time
Rev. A, October 2003
FQD5N50C / FQU5N50C
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
D-PAK
MIN0.55
0.91 ±0.10
9.50 ±0.30
0.50 ±0.10
0.76 ±0.10
0.50 ±0.10
1.02 ±0.20
2.30TYP
[2.30±0.20]
(1.00)
(3.05)
(2XR0.25)
(0.10)
2.70 ±0.20
6.10 ±0.20
9.50 ±0.30
6.60 ±0.20
(5.34)
(5.04)
(1.50)
(0.90)
2.30 ±0.20
(0.70)
2.30TYP
[2.30±0.20]
(0.50)
2.30 ±0.10
0.89 ±0.10
MAX0.96
(4.34)
2.70 ±0.20
0.80 ±0.20
0.60 ±0.20
(0.50)
6.10 ±0.20
5.34 ±0.30
0.70 ±0.20
6.60 ±0.20
0.76 ±0.10
Dimensions in Millimeters
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
Package Dimensions
(Continued)
I-PAK
2.30 ±0.20
6.60 ±0.20
5.34 ±0.20
0.76 ±0.10
2.30TYP
[2.30±0.20]
0.50 ±0.10
16.10 ±0.30
6.10 ±0.20
0.70 ±0.20
(0.50)
9.30 ±0.30
MAX0.96
(4.34)
1.80 ±0.20
0.80 ±0.10
0.60 ±0.20
(0.50)
2.30TYP
[2.30±0.20]
0.50 ±0.10
Dimensions in Millimeters
©2003 Fairchild Semiconductor Corporation
Rev. A, October 2003
FQD5N50C / FQU5N50C
Package Dimensions
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2003 Fairchild Semiconductor Corporation
Rev. I5
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