MOTOROLA MCM6226BBEJ20 128k x 8 bit static random access memory Datasheet

MOTOROLA
Order this document
by MCM6226BB/D
SEMICONDUCTOR TECHNICAL DATA
MCM6226BB
128K x 8 Bit Static Random
Access Memory
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6226BB is equipped with both chip enable (E1 and E2) and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fast Access Times: 15/17/20/25/35 ns
Equal Address and Chip Enable Access Times
All Inputs and Outputs are TTL Compatible
Three State Outputs
Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
EJ PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
NC
1
32
VCC
A
2
31
A
A
3
30
E2
A
4
29
W
A
5
28
A
A
6
27
A
BLOCK DIAGRAM
A
A
7
26
A
A
A
8
25
A
A
A
9
24
G
A
A
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
ROW
DECODER
A
A
A
A
DQ
DQ
W
G
10
23
A
11
22
E1
A
12
21
DQ
DQ
13
20
DQ
DQ
14
19
DQ
DQ
15
18
DQ
VSS
16
17
DQ
COLUMN I/O
INPUT
DATA
CONTROL
E1
E2
A
A
PIN NAMES
COLUMN DECODER
A
A
A
A
A
A
A
A
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . Chip Enables
DQ . . . . . . . . . . . . . Data Inputs/Outputs
NC . . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 2
10/31/96
 Motorola, Inc. 1996
MOTOROLA
FAST SRAM
MCM6226BB
1
TRUTH TABLE
E1
E2
G
W
Mode
I/O Pin
Cycle
Current
H
X
X
X
Not Selected
High–Z
—
ISB1, ISB2
X
L
X
X
Not Selected
High–Z
—
ISB1, ISB2
L
H
H
H
Output Disabled
High–Z
—
ICCA
L
H
L
H
Read
Dout
Read
ICCA
L
H
X
L
Write
Din
Write
ICCA
H = High, L = Low, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VCC
Output Current (per I/O)
Power Dissipation
Symbol
Value
Unit
VCC
– 0.5 to 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Iout
± 20
mA
PD
1.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Storage Temperature
Tstg
– 55 to + 150
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.5
V
Input High Voltage
VIH
2.2
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns).
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).
DC CHARACTERISTICS AND SUPPLY CURRENTS
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Parameter
Ilkg(I)
—
±1
µA
Output Leakage Current (E* = VIH, Vout = 0 to VCC)
Ilkg(O)
—
±1
µA
AC Active Supply Current (Iout = 0 mA, all inputs =
VIL or VIH, VIL = 0, VIH ≥ 3 V, cycle time ≥ tAVAV min,
VCC = max)
MCM6226BB–15: tAVAV = 15 ns
MCM6226BB–17: tAVAV = 17 ns
MCM6226BB–20: tAVAV = 20 ns
MCM6226BB–25: tAVAV = 25 ns
MCM6226BB–35: tAVAV = 35 ns
ICCA
—
—
—
—
—
195
180
165
150
130
mA
AC Standby Current (VCC = max, E* = VIH, f = fmax)
MCM6226BB–15: tAVAV = 15 ns
MCM6226BB–17: tAVAV = 17 ns
MCM6226BB–20: tAVAV = 20 ns
MCM6226BB–25: tAVAV = 25 ns
MCM6226BB–35: tAVAV = 35 ns
ISB1
—
—
—
—
—
45
40
35
30
25
mA
CMOS Standby Current (E* ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V
or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz)
ISB2
—
5
mA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
*E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
MCM6226BB
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Typ
Max
Unit
All Inputs Except Clocks and DQs
E1, E2, G, and W
Cin
Cck
4
5
6
8
pF
DQ
CI/O
5
8
pF
Characteristic
Input Capacitance
I/O Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1, 2, and 3)
Parameter
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
15
—
17
—
20
—
25
—
35
—
ns
4
Address Access Time
tAVQV
—
15
—
17
—
20
—
25
—
35
ns
Enable Access Time
tELQV
—
15
—
17
—
20
—
25
—
35
ns
Output Enable Access Time
tGLQV
—
6
—
7
—
7
—
8
—
8
ns
Output Hold from Address
Change
tAXQX
3
—
3
—
3
—
3
—
3
—
ns
Enable Low to Output Active
tELQX
5
—
5
—
5
—
5
—
5
—
ns
6, 7, 8
Output Enable Low to Output
Active
tGLQX
0
—
0
—
0
—
0
—
0
—
ns
6, 7, 8
Enable High to Output High–Z
tEHQZ
—
6
—
7
—
7
—
8
—
8
ns
6, 7, 8
Output Enable High to Output
High–Z
tGHQZ
—
6
—
7
—
7
—
8
—
8
ns
6, 7, 8
5
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. All timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device
and from device to device.
7. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E ≤ VIL, G ≤ VIL).
TIMING LIMITS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
(a)
(b)
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6226BB
3
READ CYCLE 1 (See Notes 1, 2, 3, and 9)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
READ CYCLE 2 (See Notes 3 and 5)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tELQX
tEHQZ
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
Q (DATA OUT)
HIGH–Z
DATA VALID
tAVQV
tELICCH
tEHICCL
ICC
SUPPLY CURRENT
ISB
MCM6226BB
4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)
Parameter
Write Cycle Time
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
15
—
17
—
20
—
25
—
35
—
ns
5
Address Setup Time
tAVWL
0
—
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
12
—
14
—
15
—
17
—
20
—
ns
Write Pulse Width
tWLWH,
tWLEH
12
—
14
—
15
—
17
—
20
—
ns
Data Valid to End of Write
tDVWH
7
—
8
—
9
—
10
—
11
—
ns
Data Hold TIme
tWHDX
0
—
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
—
6
—
7
—
7
—
8
—
8
ns
6, 7, 8
Write High to Output Active
tWHQX
5
—
5
—
5
—
5
—
5
—
ns
6, 7, 8
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLWH
tWLEH
W (WRITE ENABLE)
tAVWL
tDVWH
D (DATA IN)
DATA VALID
tWLQZ
Q (DATA OUT)
tWHDX
HIGH–Z
MOTOROLA FAST SRAM
tWHQX
HIGH–Z
MCM6226BB
5
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, 3, and 4)
Parameter
Write Cycle Time
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
15
—
17
—
20
—
25
—
35
—
ns
5
Address Setup Time
tAVEL
0
—
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
12
—
14
—
15
—
17
—
20
—
ns
Enable to End of Write
tELEH,
tELWH
12
—
14
—
15
—
17
—
20
—
ns
Write Pulse Width
tWLEH
12
—
14
—
15
—
17
—
20
—
ns
Data Valid to End of Write
tDVEH
7
—
8
—
9
—
10
—
11
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
0
—
ns
6, 7
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1, 2, 3, and 4)
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
tWLEH
W (WRITE ENABLE)
tDVEH
D (DATA IN)
DATA VALID
tEHDX
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6226BB XX
XX
XX
Motorola Memory Prefix
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Part Number
Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns,
35 = 35 ns)
Package (XJ = 400 mil SOJ, EJ = 300 mil SOJ)
Full Part Numbers — MCM6226BBXJ15
MCM6226BBXJ17
MCM6226BBXJ20
MCM6226BBXJ25
MCM6226BBXJ35
MCM6226BB
6
MCM6226BBXJ15R2
MCM6226BBXJ17R2
MCM6226BBXJ20R2
MCM6226BBXJ25R2
MCM6226BBXJ35R2
MCM6226BBEJ15
MCM6226BBEJ17
MCM6226BBEJ20
MCM6226BBEJ25
MCM6226BBEJ35
MCM6226BBEJ15R2
MCM6226BBEJ17R2
MCM6226BBEJ20R2
MCM6226BBEJ25R2
MCM6226BBEJ35R2
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32 LEAD
400 MIL SOJ
CASE 857A–02
32
F
17
0.17 (0.007)
N
1
32 PL
0.17 (0.007)
S
P
0.17 (0.007)
L
G
T B
DETAIL Z
16
-A-
S
D 32 PL
T B S A
S
T A
S
NOTE 3
B
S
S
-BE
0.10 (0.004)
K
DETAIL Z
-T-
SEATING
PLANE
R
0.25 (0.010)
MOTOROLA FAST SRAM
C
S RADIUS
S
T A
S
B
S
NOTE 3
S
A
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
MILLIMETERS
MIN
MAX
20.83 21.08
10.03 10.29
3.75
3.26
0.50
0.41
2.48
2.24
0.81
0.67
1.27 BSC
1.14
0.89
0.64 BSC
1.14
0.76
11.30
11.05
9.52
9.27
1.01
0.77
INCHES
MIN
MAX
0.820 0.830
0.395 0.405
0.128 0.148
0.016 0.020
0.088 0.098
0.026 0.032
0.050 BSC
0.035 0.045
0.025 BSC
0.030 0.045
0.435 0.445
0.365 0.375
0.030 0.040
MCM6226BB
7
32 LEAD
300 MIL SOJ
CASE 857–02
F 32 PL
0.17 (0.007)
32
17
1
M
D 32 PL
0.17 (0.007)
P
0.17 (0.007) S B
16
–A–
L
G
DETAIL Z
A
S
A
S
NOTE 5
S
S
-B–X–
K
S
NOTE 4
NOTE 3
E C
0.10 (0.004)
-T-
SEATING
PLANE
R
0.25 (0.010)
S RADIUS
S
B
S
NOTE 5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
MILLIMETERS
MIN
MAX
20.83 21.08
7.74
7.50
3.75
3.26
0.50
0.41
2.48
2.24
0.81
0.67
1.27 BSC
1.14
0.89
0.64 BSC
1.14
0.76
8.64
8.38
6.86
6.60
1.01
0.77
INCHES
MIN
MAX
0.820 0.830
0.295 0.305
0.128 0.148
0.016 0.020
0.088 0.098
0.026 0.032
0.050 BSC
0.035 0.045
0.025 BSC
0.030 0.045
0.330 0.340
0.260 0.270
0.030 0.040
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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MCM6226BB
8
◊
MOTOROLA MCM6226BB/D
FAST SRAM
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