Cypress CY14E256LA-SZ45XI 256-kbit (32 k ã 8) nvsram Datasheet

CY14E256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
Functional Description
■
25 ns and 45 ns access times
■
Internally organized as 32 K × 8 (CY14E256LA)
■
Hands-off automatic STORE on power-down with only a small
capacitor
■
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or autostore on power-down
■
RECALL to SRAM initiated by software or power-up
■
Infinite read, write, and RECALL cycles
■
1 million STORE cycles to QuantumTrap
■
20-year data retention
■
Single 5 V + 10% operation
■
Industrial temperature
■
44-pin thin small-outline package (TSOP) Type II and 32-pin
small-outline integrated circuit (SOIC) package
■
Pb-free and restriction of hazardous substances (RoHS)
compliant
The Cypress CY14E256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 KB. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram
VCC
QuantumTrap
512 X 512
ROW DECODER
A5
A6
A7
A8
A9
A 11
A 12
A 13
POWER
CONTROL
STORE
STATIC RAM
ARRAY
512 X 512
STORE/
RECALL
CONTROL
RECALL
A 14
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
SOFTWARE
DETECT
HSB
A13 - A 0
COLUMN I/O
INPUT BUFFERS
DQ 0
VCAP
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 6
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-54952 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2012
CY14E256LA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ................................................................ 4
SRAM Write ................................................................. 4
AutoStore Operation .................................................... 4
Hardware STORE Operation ....................................... 4
Hardware RECALL (Power-up) ................................... 5
Software STORE ......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection ............................................................ 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads .................................................................. 9
AC Test Conditions .......................................................... 9
Document Number: 001-54952 Rev. *I
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle ..................................................... 10
Switching Waveforms .................................................... 10
AutoStore/Power-up RECALL ....................................... 12
Switching Waveforms .................................................... 12
Software Controlled STORE/RECALL Cycle ................ 13
Switching Waveforms .................................................... 13
Hardware STORE Cycle ................................................. 14
Switching Waveforms .................................................... 14
Truth Table For SRAM Operations ................................ 15
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Page 2 of 19
CY14E256LA
Pinouts
Figure 1. Pin Diagram – 44-pin TSOP II / 32-pin SOIC
NC
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-pin TSOP II
(x 8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[4]
NC
[3]
NC
[2]
NC
NC [1]
[1]
NC
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
32-pin SOIC
(x 8)
Top View
(not to scale)
A12
A11
A10
NC
NC
Pin Definitions
Pin Name
I/O Type
A0–A14
Input
DQ0–DQ7
Description
Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.
WE
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power supply Power supply inputs to the device.
HSB
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
is optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No connect
No connect. This pin is not connected to the die.
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Address expansion for 2-Mbit. NC pin not connected to die.
3. Address expansion for 4-Mbit. NC pin not connected to die.
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-54952 Rev. *I
Page 3 of 19
CY14E256LA
The CY14E256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14E256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 15 for a
complete description of read and write modes.
SRAM Read
The CY14E256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0-14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
is initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14E256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power-down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14E256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Document Number: 001-54952 Rev. *I
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power-up. This pull-up is
only effective if the WE signal is tristate during power-up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
VCC
0.1 uF
10 kOhm
Device Operation
VCC
WE
VCAP
VSS
VCAP
Hardware STORE Operation
The CY14E256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14E256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Page 4 of 19
CY14E256LA
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0FC0 Initiate STORE cycle
During any STORE operation, regardless of how it is initiated,
the CY14E256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-up)
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Software STORE
Software RECALL
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14E256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0C63 Initiate RECALL cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE
WE
OE
A14–A0[6]
Mode
I/O
Power
H
X
X
X
Not selected
Output high Z
Standby
L
H
L
X
Read SRAM
Output data
Active
L
L
X
X
Write SRAM
Input data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[7]
Notes
6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54952 Rev. *I
Page 5 of 19
CY14E256LA
Table 1. Mode Selection (continued)
CE
WE
OE
A14–A0[6]
Mode
I/O
Power
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[8]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2[8]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[8]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Data Protection
The CY14E256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14E256LA is in a write mode
(both CE and WE are LOW) at power-up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
tLZHSB (HSB to output active). This protects against inadvertent
writes during power-up or brown out conditions.
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54952 Rev. *I
Page 6 of 19
CY14E256LA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time:
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
At 150 C ambient temperature ...................... 1000 h
DC output current (1 output at a time, 1 s duration) ... 15 mA
At 85 C ambient temperature .................... 20 Years
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Ambient temperature
with power applied ................................... –55 C to +150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 7.0 V
Voltage applied to
outputs in high Z state ........................ –0.5 V to VCC + 0.5 V
Input voltage ....................................... –0.5 V to VCC + 0.5 V
Latch up current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
–40 C to +85 C
4.5 V to 5.5 V
Industrial
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [9]
Max
Unit
VCC
Power supply
4.5
5.0
5.5
V
ICC1
Average VCC current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
–
–
70
52
mA
mA
ICC2
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
10
mA
ICC3
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–
35
–
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
–
–
8
mA
ISB
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile
cycle is complete.
Inputs are static. f = 0 MHz.
–
–
8
mA
IIX[10]
Input leakage current (except
HSB)
VCC = Max, VSS < VIN < VCC
–1
–
+1
A
Input leakage current (for HSB)
VCC = Max, VSS < VIN < VCC
–100
–
+1
A
–1
–
+1
A
IOZ
Off-state output leakage current VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or WE < VIL
VIH
Input HIGH voltage
2.0
–
VCC + 0.5
V
VIL
Input LOW voltage
VSS – 0.5
–
0.8
V
VOH
Output HIGH voltage
IOUT = –2 mA
2.4
–
–
V
VOL
Output LOW voltage
IOUT = 4 mA
–
–
0.4
V
Notes
9. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
10. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document Number: 001-54952 Rev. *I
Page 7 of 19
CY14E256LA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
VCAP[11]
VVCAP[12, 13]
Description
Storage capacitor
Test Conditions
Between VCAP pin and VSS
Maximum voltage driven on VCAP VCC = Max
pin by the device
Min
Typ [9]
61
–
Max
Unit
68
180
F
–
VCC – 0.5
V
Data Retention and Endurance
Over the Operating Range
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Max
Unit
Capacitance
Parameter[13]
CIN
COUT
Description
Test Conditions
Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
7
pF
Input capacitance (for HSB)
8
pF
Output capacitance (except HSB)
7
pF
Output capacitance (for HSB)
8
pF
Thermal Resistance
Parameter[13]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
44-pin TSOP II 32-pin SOIC
Unit
41.74
41.55
C/W
11.90
24.43
C/W
Notes
11. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
12. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
13. These parameters are guaranteed by design and are not tested
Document Number: 001-54952 Rev. *I
Page 8 of 19
CY14E256LA
AC Test Loads
Figure 3. AC Test Loads
963 
5.0 V
963 
5.0 V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
512 
5 pF
R2
512 
AC Test Conditions
Input Pulse Levels .................................................0 V to 3 V
Input Rise and Fall Times (10% to 90%) .................... < 3 ns
Input and Output Timing Reference Levels .................. 1.5 V
Document Number: 001-54952 Rev. *I
Page 9 of 19
CY14E256LA
AC Switching Characteristics
Over the Operating Range
Parameters [14]
Cypress
Alt Parameter
Parameter
25 ns
Description
45 ns
Min
Max
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
tRC
Chip enable access time
Read cycle time
–
25
25
–
–
45
45
–
ns
ns
tAA
Address access time
–
25
–
45
ns
tDOE
tOE
Output enable to data valid
–
12
–
20
ns
tOHA[16]
tLZCE[17, 18]
tHZCE[17, 18]
tLZOE[17, 18]
tHZOE[17, 18]
tPU[17]
tPD[17]
tOH
Output hold after address change
3
–
3
–
ns
tLZ
Chip enable to output active
3
–
3
–
ns
tHZ
Chip disable to output inactive
–
10
–
15
ns
tOLZ
Output enable to output active
0
–
0
–
ns
tOHZ
Output disable to output inactive
–
10
–
15
ns
tPA
Chip enable to power active
0
–
0
–
ns
tPS
Chip disable to power standby
–
25
–
45
ns
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
25
20
20
10
0
20
0
0
–
–
–
–
–
–
–
–
–
10
45
30
30
15
0
30
0
0
–
–
–
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output active after end of write
3
–
3
–
ns
tRC[15]
tAA[16]
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
[17, 18, 19] t
tHZWE
WZ
tOW
tLZWE[17, 18]
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [15, 16, 20]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC (typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure .
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE LOW.
17. These parameters are guaranteed by design and are not tested.
18. Measured ±200 mV from steady state output voltage.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54952 Rev. *I
Page 10 of 19
CY14E256LA
Switching Waveforms (continued)
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [21, 22]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
Figure 6. SRAM Write Cycle #1 (WE Controlled) [22, 23, 24]
tWC
Address
Address Valid
tSCE
tHA
CE
tAW
tPWE
WE
tSA
tHD
tSD
Data Input
Input Data Valid
tLZWE
tHZWE
Data Output
High Impedance
Previous Data
Figure 7. SRAM Write Cycle #2 (CE Controlled) [22, 23, 24]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tSD
Input Data Valid
Data Input
Data Output
tHD
High Impedance
Note
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is low when CE goes low, the outputs remain in the high impedance state.
24. CE or WE must be > VIH during address transitions.
Document Number: 001-54952 Rev. *I
Page 11 of 19
CY14E256LA
AutoStore/Power-up RECALL
Over the Operating Range
Parameter
CY14E256LA
Min
Max
–
20
Description
Unit
tHRECALL[25]
Power-up RECALL duration
tSTORE[26]
tDELAY[27]
STORE cycle duration
–
8
ms
Time allowed to complete SRAM write cycle
–
25
ns
VSWITCH
Low voltage trigger level
–
4.4
V
150
–
µs
HSB output disable voltage
–
1.9
V
HSB to output active time
HSB high active time
–
–
5
500
µs
ns
tVCCRISE
[28]
VHDIS[28]
tLZHSB[28]
tHHHD[28]
VCC rise time
ms
Switching Waveforms
Figure 8. AutoStore or Power-up RECALL [29]
VCC
VSWITCH
VHDIS
t VCCRISE
26
tHHHD
Note
Note 26
tSTORE
tHHHD
Note30
tSTORE
30
Note
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
25. tHRECALL starts from the time VCC rises above VSWITCH.
26. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
27. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
28. These parameters are guaranteed by design and are not tested.
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is less than VSWITCH.
30. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-54952 Rev. *I
Page 12 of 19
CY14E256LA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter [31, 32]
tRC
tSA
tCW
tHA
tRECALL
25 ns
Description
Min
25
0
20
0
–
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
45 ns
Max
–
–
–
–
200
Min
45
0
30
0
–
Max
–
–
–
–
200
Unit
ns
ns
ns
ns
µs
Switching Waveforms
Figure 9. CE and OE Controlled Software STORE/RECALL Cycle [32]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
33
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 10. AutoStore Enable / Disable Cycle [32]
Address
tRC
tRC
Address #1
Address #6
tSA
CE
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tSS
tHZCE
33
Note
t DELAY
DQ (DATA)
RWI
Notes
31. The software sequence is clocked with CE controlled or OE controlled reads.
32. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
33. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document Number: 001-54952 Rev. *I
Page 13 of 19
CY14E256LA
Hardware STORE Cycle
Over the Operating Range
Parameter
CY14E256LA
Description
Min
Max
25
Unit
tDHSB
HSB to output active time when write latch not set
–
tPHSB
Hardware STORE pulse width
15
–
ns
tSS [34, 35]
Soft sequence processing time
–
100
s
ns
Switching Waveforms
Figure 11. Hardware STORE Cycle [36]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
~
~
tDELAY
HSB (OUT)
SO
tLZHSB
RWI
Write Latch not set
~
~
tPHSB
HSB (IN)
tDELAY
tDHSB
tDHSB
~
~
HSB (OUT)
HSB pin is driven high to VCCQ only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
RWI
Figure 12. Soft Sequence Processing [34, 35]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
34. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
35. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
36. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-54952 Rev. *I
Page 14 of 19
CY14E256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 2. Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Ordering Information
Speed
(ns)
25
Ordering Code
Package Diagram
CY14E256LA-SZ25XIT
51-85127
Package Type
Operating Range
32-pin SOIC
Industrial
CY14E256LA-SZ25XI
45
CY14E256LA-SZ45XIT
CY14E256LA-SZ45XI
All the mentioned parts are Pb-free.
Ordering Code Definitions
CY 14 E 256 L A - ZS 25 X I T
Option:
T – Tape and Reel
Blank – Std.
Pb-Free
Die revision:
Blank – No rev
A – 1st Rev
Voltage:
E – 5.0 V
Temperature:
I – Industrial (–40 to 85 oC)
Speed:
25 to 25 ns
45 to 45 ns
Package:
ZS – 44-pin TSOP II
SZ – 32-pin SOIC
Data Bus:
L–×8
Density:
256 – 256 Kb
14 – nvSRAM
Cypress
Document Number: 001-54952 Rev. *I
Page 15 of 19
CY14E256LA
Package Diagrams
Figure 13. 44-pin TSOP II Package Outline, 51-85087
51-85087 *D
Figure 14. 32-pin SOIC (300 Mil) Package Outline, 51-85127
51-85127 *C
Document Number: 001-54952 Rev. *I
Page 16 of 19
CY14E256LA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
CMOS
chip enable
complementary metal oxide semiconductor
°C
degree Celsius
EIA
electronic industries alliance
k
kilo ohms
HSB
I/O
hardware store busy
MHz
Mega Hertz
input/output
A
micro Amperes
JEDEC
joint electron devices engineering council
F
micro Farads
nvSRAM
non-volatile static random access memory
s
micro seconds
OE
RoHS
output enable
mA
milli Amperes
restriction of hazardous substances
ms
milli seconds
RWI
read and write inhibited
mV
milli Volts
SOIC
small outline integrated circuit
ns
nano seconds
SRAM
static random access memory

ohms
TSOP
thin small outline package
%
percent
WE
write enable
pF
pico Farads
ps
pico seconds
V
Volts
W
Watts
Document Number: 001-54952 Rev. *I
Symbol
Unit of Measure
Page 17 of 19
CY14E256LA
Document History Page
Document Title: CY14E256LA, 256-Kbit (32 K × 8) nvSRAM
Document Number: 001-54952
Revision
ECN
Orig. of
Change
Submission
Date
**
2748216
GVCH /
PYRS
08/04/09
New Datasheet
*A
2772059
GVCH
09/30/09
Updated Software STORE, RECALL and Autostore Enable, Disable soft
sequence
*B
2829117
GVCH
12/16/09
Updated STORE cycles to QuantumTrap from 200K to 1 Million
Added Contents. Moved to external web.
*C
2891356
GVCH
03/12/10
Removed inactive parts from Ordering Information table.
Updated links in Sales, Solutions, and Legal Information.
*D
2922858
GVCH
04/26/10
Table 1: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Updated HSB pin operation in Figure 8 and updated footnote 21
Updated package diagram 51-85087
*E
3030490
GVCH
09/15/10
Change: ISB and ICC4 max value from 5 mA to 8 mA.
Areas affected: DC Electrical Characteristics on page 7.
Change: Template and styles update.
Areas affected: Entire datasheet
*F
3143330
GVCH
01/17/2011
Description of Change
Fixed typo in Figure 8.
*G
3219793
GVCH
04/08/2011
Logic Block Diagram: Fixed typo
*H
3315247
GVCH
07/15/2011
Updated DC Electrical Characteristics (Added Note 11 and referred the same
note in VCAP parameter).
Updated Capacitance (Included Input capacitance (for HSB) and Output
capacitance (for HSB)).
Updated AC Switching Characteristics (Added Note 14 and referred the same
note in Parameters).
*I
3660776
GVCH
06/29/2012
Updated DC Electrical Characteristics (Added VVCAP parameter and its
details, added Note 12 and referred the same note in VVCAP parameter, also
referred Note 13 in VVCAP parameter).
Updated Package Diagrams (spec 51-85127 (Changed revision from *B to
*C)).
Document Number: 001-54952 Rev. *I
Page 18 of 19
CY14E256LA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54952 Rev. *I
Revised June 29, 2012
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 19 of 19
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