Mitsubishi M66307SP Line scan buffer with 16-bit mpu bus compatible input Datasheet

MITSUBISHI 〈DIGITAL ASSP〉
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
M66307SP/FP
LINE
SCAN
BUFFER
16BIT
MPU
BUS
COMPATIBLE
INPUTS
LINE
SCAN
BUFFER
withwith
16-BIT
MPU
BUS
COMPATIBLE
INPUTS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M66307SP/FP is an integrated circuit consisting of a line buffer
with static memory, manufactured by the silicon gate CMOS process, which satisfies A3-paper 400DPI requirements. It converts the
stored data from the 16-bit MPU bus into serial data and outputs it at
a transfer rate of up to 10Mbps synchronously with the external data
request clock or an arbitrary continuous clock.
D8
1
32
VCC(5V)
D9
2
31
D7
D10
3
30
D6
D11
4
29
D5
D12
5
28
D4
FEATURES
D13
6
27
D3
•
•
•
•
•
D14
7
26
D2
D15
8
25
D1
WRITE CONTROL
WR
INPUT
CHIP SELECT INPUT CS
COMMAND/DATA
CONTROL INPUT C/D
9
10
RESET INPUT RESET
12
21
EXD EXTENDED D INPUT
13
20
TOG TOGGLE INPUT
14
19
CLK/ φ OUT CLOCK
15
18
DATA OUT DATA OUTPUT
16
17
BUSY/ORDY
DATA INPUTS
DATA INPUTS
(0V)GND
•
•
DACK
22
DMA ACKNOWLEDGE
INPUT
DMA REQUEST
DREQ
OUTPUT
OUTPUT
BUSY/
OUTPUT
READY
OUTPUT
APPLICATION
Image-handling general OA equipment
GND VCC
16
9
10
11
23
24
25
26
27
28
29
30
31
1
2 16
3
4
5
6
7
8
20
21
D0
23
The clock input (CLK/φ IN) contains a Schmitt trigger.
The reset (RESET), Write (WR) and toggle input (TOG) contain
negative noise reduction circuits.
BLOCK DIAGRAM
WR
CS
C/D
DACK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
TOG
EXD
24
Outline 32P4B
32P2W-A
Write
control
circuit
Write/send 13
address
control
9
circuit
Command registers
16
32
9
13
Fixed data
length register
DREQ words register
320 word
Mode register
CMOS
SRAM
16
Expansion
control
circuit
CLK/ φ IN 14
CLKE 15
Clock
control
circuit
RESET 12
Reset
control
circuit
16
Frequency
divider
Clock signal
select circuit
Output
control
circuit
22 DREQ
4
16
Parallel-serial converter
•
Data bus buffer
•
INTERRUPT REQUEST
INTR
OUTPUT
CLOCK INPUT CLK/ φ IN
CLOCK ENABLE
CLKE
INPUT
11
M66307SP/FP
•
•
16-bit MPU bus compatible
Writing data via DMAC is possible
320-word (5,120-bit) static RAM
Data output rate of up to 10Mbps
Built-in function to add fixed data of a specified length at the beginning of output data (Fixed data: Continuous High bit or Low bit
data)
The output format can be selected between FIFO or LIFO.
The output method can be selected from two:
(1) Synchronized with an arbitrary continuous clock (φ IN) on the
system side; the frequency of clock output (CLK/φ OUT) can
be divided by 1, 2, 4, 8, or 16.
(2) Synchronized with the data request clock (CLK IN) on the peripheral equipment side.
Up to two devices can be cascaded.
(1) Toggle configuration
(2) 32-bit bus configuration
High fan-out outputs (CLK/φ OUT, DATA OUT).
Io=±24mA
(±4mA for INTR and DREQ
±8mA for BUSY/ORDY)
Output
control
circuit
13 INTR
17 BUSY/ORDY
Output
control
circuit
18 DATA OUT
Output
control
circuit
19 CLK/ φ OUT
1
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
FUNCTION
The M66307 outputs serial data from the system bus to peripheral
equipment. Containing an internal 320-word (5,120-bit) line buffer, it
can output any number of words(up to 320 words) of stored data
from the data bus at a time. The data can be output synchronously
with an arbitrary continuous clock (φ IN) on the system side or the
data request clock (CLK IN) from the peripheral equipment.
The data can be output MSB or LSB first, or FIFO (First-in, First-out)
OPERATION
Interface of the M66307
The M66307 has two interface sections, one on the system
bus side and one on the peripheral equipment side as
or LIFO (Last-in, First-out) as programmed by the user. When not
programmed, the clock and output format are defaulted to CLK IN,
MSB and FIFO, respectively.
In addition to the above basic functions, the M66307 has such programmable functions that let you add fixed data of a specified length
at the beginning of output data, store one line of fixed data using a
single substitute command, or repetitively output the data stored in
the line buffer.
shown in Figure 1. Up to 320 words of data stored from the system
bus side are output to the peripheral equipment after parallel-serial
conversion.
Address bus
Control bus
Data bus
C/D CS
D0~D15
WR
RESET
φ IN
TOG
EXD
CLKE
System bus
interface section
DACK DREQ INTR BUSY
DATA
CLK IN OUT
CLK/φ
OUT ORDY
Peripheral equipment
interface section
VCC
Notes :
:
:
:
Connect CS to one of address bus directly or via a decoder.
Select either CLK IN or φ IN (indicated by broken line)
Connect DACK and DREQ (indicated by broken line) when DMA transfer is used.
Make sure the unused active Low inputs are pulled-up to VCC.
Fig. 1 Interface of M66307
2
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
The following describes the operation of the M66307 using
the operation flowchart in Fig. 2. The M66307 has three
modes: “static mode”, “write mode”, and “send mode”.
In the static mode, the M66307 is in a standby state.
The M66307 remains in this mode until it is set to the write
mode by the operation mode setting command after reset
input or until it is set to the write mode after the (operation)
stop command is stored.
In the write mode, the M66307 stores up to 320 words of
data from the 16-bit system bus.
In the send mode, the M66307 serially outputs the data
stored in the write mode. The write and send modes are
set by the operation mode setting command.
• Static mode
In the static mode, the M66307 is first initialized.
This initialization involves selecting φ IN or CLK IN, setting
the divide ratio when φ IN is selected, and specifying the
use of expansion/normal, data store by DMA cycle or MPU
cycle, presence of fixed beginning data of specified length added at
the beginning of data output, and the polarity (High or Low)
of the fixed data. Once the above is programmed, the
M66307 executes its functions according to the specification until
changed.
After the initialization is completed, the M66307 must be
programmed for the specification of output formats LSB/
MSB and LIFO/FIFO. In addition, when the “addition of
fixed data of specified length at the beginning of data output” is specified in the initialization, the length of the fixed
beginning data must be programmed; similarly, when “data store
by DMA cycle” is specified, the number of words per line
transferred via DMA must be programmed. Once programmed, the specified format is continued until it is changed.
The initialization and these settings can only be made in
the static mode. When you want to change the specification
in the middle of operation, place the M66307 in the static mode
using the stop command and reprogram the setting. When
initializing the device and setting the output format after rest input, if
your setting is the same as the default value, programming may be
omitted. (See note 1 in Fig. 4.)
When the above settings are completed, the M66307 is
ready for data transfer from the system bus to peripheral
equipment.
• Write mode
When settings in the static mode are completed, set to the
write mode. In this mode, signals for write to internal memory are
enabled, and data is stored in the internal memory at each write
cycle executed by the MPU or DMA controller.
When storing one line of fixed data, note that once the
word length per line is stored as a command, the M66307
operates in the same way as one line of fixed data is
stored.
In the write mode, data output (DATA OUT) outputs the
polarity of “fixed data” that has been set by initialization.
(See Fig. 5.)
• Send mode
After storing data in the write mode is completed, set to the send
mode. In this mode, the M66307 serially outputs the data stored in
the write mode according to the setting for the addition of the fixed
beginning data and the settings of LSB/MSB and LIFO/FIFO. While
the data is output, the M66307 outputs the Busy/Output Ready
signal (BUSY/ORDY).
When one line length of data is output, BUSY/ORDY is cleared and
an interrupt request signal (INTR) is output.
For the next line, restart from the setting in the write mode. If you
want to output the same data for one line, the same data can be
repetitively output without storing by using a transmit repeat request
command.
When you want to stop the M66307 in the middle of operation or
change some settings, use the stop command. The stop command
is valid in both write and send modes.
When operation is stopped, you can initialize the M66307 and reprogram the output specification, the length of fixed beginning data, and
number of DMA transfer words, When you do not
reprogram, the same settings before operation is stopped are
continued.
3
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Reset
C/D=1
Initialization
Static mode
C/D=1
Set the number of DREQ words.
Set the length of fixed beginning data.
Set the output format.
C/D=1
YES
Set to the
write mode
C/D=1
Set for operation
stop
Fixed data
for one line output?
Write mode
NO
C/D=1
Set the one line
fixed data length.
C/D=0 Storing data from
or
data bus
DACK=0
Storing data
for one line length
completed?
NO
YES
C/D=1
Set to send mode
(BUSY/ORDY output)
Outputting data
C/D=1
NO
Outputting data
for one line length
completed?
Set for transmit
repeat request
(INTR output)
YES
Repetitive output
NO
NO
Fig. 2 Operation flowchart of M66307
4
Completed?
YES
Send mode
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
PIN DESCRIPTIONS
Pin
Name
Function
I/O
D0~D15
Data inputs
Input
Normally connected to a 16-bit bus.
WR
Write control
input
Input
Data or command is stored to the M66307 at the Low to High transition. This signal is normally
connected to the write control signal of the control bus.
CS
Chip select
input
Input
When Low, this signal allows data or command to be stored from the MPU to the M66307. It is normally
connected to the address bus directly or via a decoder. When this signal is High, the MPU cannot
access the M66307.
DACK
DMA
acknowledge
input
Input
When Low, this signal allows data to be stored by DMA transfer. It is normally connected to the DMA
acknowledge output (DACK) of the DMA controller.For systems where DMA transfer is not used, this
pin must be pulled-up to VCC.
C/D
Command/
data control
input
Input
This signal discriminates whether the information on the data bus when the MPU accessed the M66307
is command or data. When High, the signal indicates that the information is a command; when Low, it
indicates data. It is normally connected to the address bus directly or via a decoder.
RESET
Reset input
Input
When Low, this signal initializes the command registers and various circuits of the M66307. As a result,
all active Low output signals are set High; clock outputs (CLK, φ OUT) are set High; data output (DATA
OUT) is set Low.
DREQ
DMA request
output
Output
This signal requests DMA cycles. When data store by DMA cycle is defined in the initialization and the
number of DMA transfer words is specified, this output is set Low when the M66307 is set into the write
mode.
When the set number of DMA cycles are completed, it returns High.
INTR
Output
Interrupt
request output
This signal requests an interrupt to the MPU when the written data is sent out (Low output). This
request is cleared by MPU access or toggle input(TOG) [when extended toggle is used] (High output).
BUSY/
ORDY
BUSY/
OUTPUT
READY
output
Output
When Low, this signal informs the MPU that no commands other than STOP can be set to the M66307,
and informs the peripheral equipment that the M66307 is sending data.
When the M66307 is in the send mode, this signal is set Low; when transmission is completed, it
returns High.
CLKE
Clock enable
input
Input
When Low, this signal enables clock input (CLK/φ IN); when High, it disables the clock input. When
clock input is φ IN, CLKE is invalid so that this pin must be pulled-up to VCC or pulled-down to GND.
CLK/φ IN
Clock input
Input
CLK IN is generally used as data request clock from peripheral equipment; φ IN is generally used as
continuous clock on the system side. Selection between CLK IN and φ IN is specified by the initialization
command. Select CLK IN when the data output timing must be matched to the timing of the peripheral
equipment. Select φ IN when the timing need not be matched and data can be sent at a stroke using the
clock from the system. φ IN can be divided into one of five smaller frequencies when the peripheral
equipment is slow to read data. (Note: The continuous clock of φ IN may not necessarily be the system
clock.)
TOG
Toggle input
Input
This signal can only be valid when extended toggle is used (using two M66307s) and CLK IN is
selected for clock input. This input sets the write and send modes. Each time this signal is set Low, the
IC in the write mode is reversed to the send mode and the IC in the send mode is reversed to the write
mode. It is impossible to control mode inversion with this function and operation mode setting
command together.
DATA
OUT
Data output
Output
The data stored in the internal memory or fixed data is serially output synchronously with clock input
(CLK/φ IN) according to the settings of output format (LSB/MSB, LIFO/FIFO).
Clock output
Output
Peripheral devices take in data with the “rise” of clock pulses.
Extended D
input
Input
CLK/
φ OUT
EXD
This signal is used for an extended system using two M66307s. Connect the EXD of the master IC to
the DATA OUT pin of the slave IC. The EXD of the slave IC must be pulled-up to VCC. (See the
application example.) For normal use, pull up EXD to VCC or pull down it to GND.
5
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Outline of commands
When the MPU accesses the M66307 for write with C/D =
High as shown in Table 1, the M66307 reads the information
on the data bus into the register as a command. When the MPU
accesses the M66307 for write with C/D = Low, the M66307 reads
the information into the internal memory as data. There are eight
kinds of commands classified by the upper four bit (D15 to D12).
Table 1. Access for Write
C/D
CS
DACK
WR
X
X
X
H
X
H
H
H
L
H
L
L
H
X
H
L
X : denotes H or L.
6
Function
The M66307 cannot be accessed.
Command is stored in the internal command register.
Data is stored in the internal memory.
(During MPU cycle)
(During DMA cycle)
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
1. Register configuration
The M66307 has the command registers shown in Figure 4. The
mode register consists of a total of eight flags (F0-F7) and seven bits
(B0-B6). Each flag and bit are set to default values (=0) by reset
input.
There are some commands that do not have a register. These include the one line fixed data setting command, transmit repeat request command, and the stop command.
Group 1
1
2
3
4
5
6
7
8
Group 2
Group 3
Group 4
Initialization command
DREQ words setting command
Fixed beginning date length setting command
Output format setting command
Operation mode setting command
One line fixed data setting command
Transmit repeat request command
Stop command
2. Command organization
The commands are broadly classified into four groups as shown in
Fig. 3. It shows the relationship between the three modes of the
M66307 (static, write and send modes) and the storable commands.
Command
Mode
Send
Group 1 Group 2 Group 3 Group 4
Static
Write
Send complete
(BUSY=“H”)
5
6
7
Send
(BUSY=“L”)
Note : Command store is valid within
Fig. 3 Command store Map
Description of commands
Command Upper bit
name (D15~D12)
Contents
Initialization
command
1000
This command initializes the hardware setting of the system by selecting clock input and setting the specification for
the use of extension, specification for DREQ output, specification for fixed data output, and the logical polarity of “fixed
data.”
DREQ words
setting command
0111
When [N] is set, M66307 outputs a Low from the DREQ pin when setting the write mode. When [N+1] words are
written by the DMA controller (MPU), it outputs a High from the DREQ pin.
Fixed
beginning
data length
setting
command
0110
This command sets the length of fixed beginning data from 3 to 4,095. When [n] is set to the fixed beginning data
length setting register, “fixed data” is output from the DATA OUT pin each time the send mode is entered. When “fixed
data” for [n+1] bits is output, the M66307 starts outputting the data stored in memory. Clock output (CLK/φ OUT), the
clock for synchronization, is output even while fixed data is being output. Note that even when the output format is
LIFO, the data in the internal memory is output after outputting fixed data is completed.
0100
This command sets the output format for LIFO or FIFO and for MSB first or LSB first.
Operation
mode
setting
command
0000
This command is stored in the 4-bit (B3, B2, B1, B0) register shown in Figure 4. The write and send modes are set by
this register. The send mode setting command when an extended 32-bit system is used and the mode inverting
command when an extended toggle system is used are two-word commands. Store the second word after storing the
first word. B3 is a DREQ mask bit. If the write mode is set by setting B3=1 when in the DREQ mode (F4=1), the
M66307 does not output a Low from the DREQ pin. When in the DREQ mode, set B3=1 when setting the write mode
before storing the one line fixed data setting command. It is impossible to control mode inversion with this command
and extended toggle input (TOG) together.
One line fixed
data setting
command
0011
When this command is stored, you obtain the same effect as writing “fixed data” for the set number of words. When set
to the send mode, “fixed data” equivalent to [(fixed beginning data set value+1)+(one line fixed data setting word
value+1)x16] bits is output along with the sync clock (CLK/φ OUT).
Transmit
repeat request
command
0010
This command allows you to resend the same data that has already been sent. This command becomes executable
after transmission is completed. When using an extended system, store the second word of the operation mode
setting command following the transmit repeat request command.
Stop
command
1111
This command stops the operation of the M66307. This command is valid in all modes. It initializes all registers and
circuits except the initialization register, output format setting register, DREQ words setting register, and fixed beginning data length register, thereby placing the M66307 into the static mode. In addition to stopping operation, this
command may be used when you want to store the commands that can only be valid in the static mode (e.g., group 1
and group 2 commands).
Output format
setting command
7
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
φ CLK FLAG
(1=φ IN, 0=CLK IN)
Valid when D11=1– Divide retio setting bit (See Table 2).
Toggle extension flag(1=toggle; 0=normal use)
Invalid when D4=1–32-bit extension flag (1=32; 0=16-bit bus)
Mode
register
DREQ mode flag(1=DREQ mode;
0=not DREQ mode)
Fixed beginning data output flag (1=output;
0=not output)
Fixed data polarity flag (1=High; 0=Low)
Initialization command
1
0
0
0
D15D14D13D12
DREQ
words
register
Fixed
beginning
data
length
register
Mode
register
F7 B6 B5 B4 0
0
0
F6 F5 F4 F3 F2
D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DREQ words setting command
(valid when F4=1)
0
1
1
1
0
0
Number of DMA transfer words
0 A8 A7 A6 A5 A4 A3 A2 A1 A0
Fixed beginning data length setting command
(valid when F3=1)
0
1
1
0
Number of fixed beginning data output bits
E11E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
LIFO/FIFO flag (1=LIFO; 0=FIFO output)
LSB/MSB-first flag (1=LSB; 0=MSB-first output)
Output format setting command
0
1
0
0
0
0
0
0
0
0
0
0
0
0 F1 F0
One line fixed data output line length
One line fixed data setting command
0
0
1
1
0
0
0 W8 W7 W6 W5 W4 W3 W2 W1 W0
Transmit repeat request command (Note 2)
0
Mode
register
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Operation mode setting bits (See Table 3.)
Operation mode setting command
0
0
0
0
0
0
0
0
0
0
0
0
0 B2 B1 B0
0
0
0
0
0
0
0
0
0
Stop command
1
1
1
1
Table 2. Divide Ratio Setting
Divide ratio
1
1/2
1/4
1/8
1/16
B6
0
0
0
0
1
B5
0
0
1
1
0
0
0
0
Table 3. Operation Mode Setting
B4
0
1
0
1
0
Bit
Item
Write mode
Send mode
Write mode
Exten- 32 bits
∗1 First word
ded
Send mode Second word
use
∗1 First word
Toggle
Mode inversion Second word
Normal use
B3
B2
B1
B0
∗2
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
∗2
0
0
∗2
∗2
∗1 : Store the first
word, then
store the
second word.
∗2 : DREQ mask bit
(Refer to
description of
commands.)
Note 1) The default values of flags (F0-F7) and bits (B0-B6) are zero (0).
2) When using an extended system, store the second word of the operation mode setting command following the transmit
repeat request command.
3) It is impossible to control mode inversion with operation mode setting command and extended toggle input (TOG)
together.
Fig. 4 Register configuration of M66307
8
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Operation timing
1. Storing commands and data from system bus to M66307 Figures
5 and 6 show the timings at which commands and data from the
system bus are stored in the M66307 after reset is input or the stop
command is issued.
Output format
Fixed beginning
Write mode set
Intialization data length (n) set set
1WORD
(N-1)WORD
NWORD
CS
C/D
DACK
WR
D0~D15
DREQ
DATA OUT
Fixed data
Static mode
Write mode
Note : Number of transfer words N=1 to 320; fixed data bit length n=3 to 4,096
Fig. 5 Storing commands and data by MPU cycle
Intialization
CS
Number of Fixed beginning
Output format
DREQ words data length (n) set set
Write mode set
(N-1) set
C/D
DACK
WR
D0~D15
DREQ
1WORD
(N-1)WORD
NWORD
DATA OUT
Static mode
Fixed data
MPU cycle
Write mode
DMA cycle
Note : Number of transfer words N=1 to 320; fixed data bit length n=3 to 4,096
Fig. 6 Storing commands by MPU cycle and storing data by DMA cycle
9
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
2. Sending data from M66307 to peripheral equipment
After data for one line is stored from the system bus into the M66307,
the M66307 serially sends the data to the peripheral equipment.
There are 16 methods to send data as shown in Fig. 7. Figures 8 to
11 show the send timings for four of the 16 send method.
MSB
FIFO
Without fixed
beginning
data output
LSB
MSB
LIFO
LSB
MSB
CLK IN
FIFO
With fixed
beginning
data output
LIFO
LSB
MSB
FIFO
Fig. 9
Fig. 10
LSB
MSB
LIFO
LSB
MSB
φ IN
FIFO
With fixed
beginning
data output
Fig. 11
LSB
MSB
Sending method
Without fixed
beginning
data output
Fig. 8
LSB
MSB
LIFO
LSB
Fig. 7 Various methods for sending data
Send mode set
Write mode set
CS
C/D
DACK
WR
D0~D15
1
2
3
N×16–2 N×16–1 N×16 N×16+1
CLK IN
CLK/φ OUT
(Note)
DATA OUT
Fixed data DOF DOE DOD
DN3
DN2
DN1 DN0
BUSY/ORDY
INTR
DREQ
Note : DATA OUT outpus fixed data with CLK IN of N×16+1 or more.
: N : Transfer words
: Dij : i=transfer words (0-N); j=bits (0-F)
Fig. 8 Send timing of M66307 (CLK IN, without fixed beginning data output, FIFO, MSB)
10
(Fixed data)
Fixed data
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Send mode set
Write mode set
CS
C/D
DACK
WR
Note : Y=(n+1)+16×N
D0~D15
1
2
n+1
n+2
n+3
n+4
Y–3 Y–2
Y–1
(Y+1) (Y+2)
Y
CLK IN
CLK/φ OUT
(Note)
DATA OUT
DOF DOE
Fixed data
DN0
DN3 DN2 DN
(Fixed data)
Fixed data
BUSY/ORDY
INTR
DREQ
Note : DATA OUT outputs fixed data with CLK IN of (n+1)+(16×N)+1 or more.
: N:Transfer words; n:fixed beginning data length (register set value)
: Dij: i=transfer words (0-N); j=bits (0-F)
Fig. 9 Send timing of M66307 (CLK IN, with fixed begnning data output, FIFO, MSB)
Send mode set
Write mode set
WR
D0~D15
φ IN
CLK/φ OUT
DATA OUT
Fixed data
DOF
DOE
DN3
DN2 DN1
DN0
Fixed data
BUSY/ORDY
INTR
Note : The same input/output and conditions as in Figure 8 are not shown here.
Fig. 10 Send timing of M66307 (φ IN without fixed data output, FIFO, MSB)
Send mode set
Write mode set
WR
D0~D15
1
2
3
N×16–2 N×16–1 N×16 N×16+1
CLK IN
CLK/φ OUT
DATA OUT
(Note)
(Fixed
Fixed data
data)
Fixed data
Output formats
FIFO, MSB
DOF
DOE
DOD
DN3
DN2
DN1
DN0
FIFO, LSB
DOO
LIFO, MSB
DNF
DO1
DO2
DNC
DND
DNE
DNF
DNE
DND
D03
D02
D01
D00
LIFO, LSB
DN0
DN1
DN2
DOC
DOD
DOE
DOF
Note : The same input/output and conditions as in Figure 8 are not shown here.
Fig. 11 Send timing of M66307 (CLK IN, without fixed data output)
11
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
ABSOLUTE MAXIMUM RATINGS
Symbol
` VCC
Parameter
Condition
Input voltage
VO
Output voltage
Pd
Power dissipation
Tstg
Storage temperature
Unit
–0.3~+7.0
V
–0.3~VCC+0.3
V
0~VCC
V
700
mW
–65~+150
°C
Supply voltage
VI
Rating
Ta=25°C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C unless otherwise noted)
Parameter
Symbol
Min.
Limits
Typ.
Max.
4.5
5.0
5.5
Unit
VCC
Supply voltage
GND
Supply voltage
VI
Input voltage
0
VCC
VO
Output voltage
0
VCC
V
Topr
Ambient temperature
70
°C
V
0
0
V
V
ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VCC=5V±10% unless otherwise noted)
Symbol
VIH
Input “H” voltage
VIL
Input “L” voltage
VT+
VH
VOH
VOL
VOH
VOL
VOH
VOL
II
Positive threshold
voltage
Negative threshold
voltage
Hysteresis width
Output “H” voltage
Output “L” voltage
Output “H” voltage
Output “L” voltage
Output “H” voltage
Output “L” voltage
Input current
ICC1
Supply current (in write and send modes)
ICC2
Supply current (in static mode)
CI
Input capacitance
VT–
Test condition
Parameter
Min.
D0~D15, WR, C/D, CS,
DACK, EXD
RESET, CLKE, CLK/φ
IN, TOG
Max.
VCC+0.3
V
–0.3
0.8
V
2.4
VCC+0.3
V
0.6
V
0.55
±10
V
V
V
V
V
V
V
µA
110
mA
1
mA
10
pF
0.2
DATA OUT,
CLK/φ OUT
BUSY/ORDY
DREQ, INT
IOH=–24mA
IOL=+24mA
IOH=–8mA
IOL=+8mA
IOH=–4mA
IOL=+4mA
VI=0~VCC
VI=0 or VCC
Output pin open
VI=0 or VCC
Output pin open
Unit
2.2
–0.3
Notes 1 : The current that flows into the IC is defined as positive (unsigned).
2 : The typical values are for VCC=5V and Ta=25°C.
12
Limits
Typ.
VCC–0.8
0.55
VCC–0.8
0.55
VCC–0.8
50
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
TIMING REQUIREMENTS (Ta=0~70°C, VCC=5V±10%, GND=0V unless otherwise noted)
Symbol
tC(φI)/(CI)
tW±(φI)/(CI)
tSU(CE–CI)
th(CI–CE)
tCW
tW(W)
tSU(D–W)
th(W–D)
tSU(A–W)
th(W–A)
tSU(DAC–W)
th(W–DAC)
trec(W)
trec(W–CI)
trec(CI–W)
tW(R)
trec(R-W)
tW(T)
trec(CI-T)
trec(T-CI)
trec(W-T)
trec(T-W)
Parameter
Test condition
Clock cycle time
Clock pulse width
Clock enable setup time before clock
Clock enable hold time after clock
Write cycle time
Write pulse width
Data setup time before rising edge of write signal
Data hold time after rising edge of write signal
Address setup time before falling edge of write signal
Address hold time after rising edge of write signal
DMA acknowledge input setup time before falling edge of
write signal
DMA acknowledge input hold time after rising edge of
write signal
Write recovery time
Clock recovery time after rising edge of write signal
Write recovery time after falling edge of clock
Reset pulse width
Write recovery time after reset
Mode inversion pulse width
Mode inversion recovery time after falling edge of clock
Clock recovery time after rising edge of mode inversion
Mode inversion recovery time after rising edge of write signal
Write recovery time after rising edge of mode inversion
Min.
Limits
Typ.
Max.
Unit
100
45
35
5
100
60
45
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
0
ns
40
250
250
250
250
250
100
250
250
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : A delay in clock input (CLK/φ IN) rise time (tr) or fall time (tf) may cause erroneous operation.
tr, tf : 20ns or less is recommended.
13
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
SWITCHING CHARACTERISTICS (Ta=0~70°C, VCC=5V±10%)
Symbol
tPLH(CI-DO)
Propagation time between clock and DATA OUT
tPHL(CI-DO)
tPLH(CI-CO)
CL=50pF
CL=150pF
CL=50pF
CL=150pF
CL=50pF
CL=150pF
CL=50pF
CL=150pF
Limits
Typ.
25
27
30
35
21
23
26
31
Max.
75
100
75
100
75
100
75
100
Parameter
Propagation time between clock and CLK/φ OUT
tPHL(CI-CO)
Test condition
Min.
Unit
ns
ns
ns
ns
tPHL(CI-INT)
Propagation time between clock and INTR
CL=50pF
32
85
ns
tPLH(CI-BUS)
Propagation time between clock and BUSY/ORDY CL=50pF
25
85
ns
CL=50pF
CL=150pF
CL=50pF
CL=150pF
CL=50pF
CL=150pF
CL=50pF
CL=150pF
35
100
120
100
120
100
120
100
120
tPLH(φI-DO)
Propagation time between clock and DATA OUT
tPHL(φI-DO)
tPLH(φI-φO)
Propagation time between clock and CLK/φ OUT
tPHL(φI-φO)
40
33
36
ns
ns
ns
ns
tPHL(φI-INT)
Propagation time between clock and INTR
CL=50pF
42
100
ns
tPLH(φI-BUS)
Propagation time between clock and BUSY/ORDY CL=50pF
34
100
ns
CL=50pF
CL=150pF
CL=50pF
CL=150pF
39
40
42
47
150
180
150
180
tPLH(W-DO)
Propagation time between write and DATA OUT
tPHL(W-DO)
ns
ns
tPLH(W-INT)
Propagation time between write and INTR
CL=50pF
39
150
ns
tPHL(W-BUS)
Propagation time between write and BUSY/ORDY CL=50pF
47
150
ns
51
150
ns
20
85
ns
tPHL(W-DRE)
Propagation time between write and DREQ
CL=50pF
tPLH(W-DRE)
tPLH(T-DO)
Propagation time between mode inversion and
DATA OUT
CL=50pF
CL=150pF
70
71
200
250
ns
tPLH(T-INT)
Propagation time between mode inversion and
INTR
CL=50pF
68
200
ns
tPHL(T-BUS)
Propagation time between mode inversion and
BUSY/ORDY
CL=50pF
53
200
ns
tPHL(T-DRE)
Propagation time between mode inversion and
DREQ
CL=50pF
58
200
ns
Note : AC test waveform
Input pulse level
Input pulse rise time
Input pulse fall time
Reference voltage Input voltage
Output voltage
14
0~3V
6ns
6ns
1.3V
1.3V
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
TIMING DIAGRAMS
Write Timing
(1) Storing commands and data from MPU
tCW
C/D
tsu(A-W)
th(W-A)
CS
tsu(A-W)
th(W-A)
tW(W)
WR
D0~D15
tsu(D-W)
th(W-D)
(2) Storing data from DMAC
tCW
DACK
th(W-DAC)
tsu(DAC-W)
tW(W)
WR
D0~D15
tsu(D-W)
th(W-D)
(3) Write recovery time
WR
trec(W)
(4) Output timing during write
Write mode set
Number of transfer words
1
WR
2
N+1
DREQ
tPLH(W-DRE)
tPHL(W-DRE)
DATA OUT
Fixed data
tPHL(W-DO), tPLH(W-DO)
Note : The above shows the timing when the DREQ mode flag is set by initialization and the number of transfer words
N is set. When the DREQ mode flag is not set, DREQ is tied High.
15
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Send Timing
(1) Clock input: CLK IN
Send mode
Write mode
WR
tC(CI)
trec(CI-W)
trec(W-CI)
CLK IN
tW+(CI) tW–(CI)
CLK OUT
tPHL(CI-CO)
DATA OUT
tPLH(CI-CO)
Fixed data
Fixed data
tPLH, tPHL(CI-DO)
BUSY/ORDY
tPLH(CI-BUS)
tPHL(W-BUS)
INTR
tPHL(CI-INT)
Send mode
tPLH(W-INT)
Write mode
trec(W-CI)
WR
tsu(CE-CI)
th(CI-CE)
tsu(CE-CI)
th(CI-CE)
trec(CI-W)
CLKE
CLK IN
CLK OUT
DATA OUT
Fixed data
Fixed data
(2) Clock input : φ IN
Send mode
Write mode
WR
tC(φ I)
φ IN
tW+(φ I)
tW–(φ I)
φ OUT
tPHL(φ I-φ O)
DATA OUT
tPLH(φ I-φ O)
Fixed data
Fixed data
tPLH,tPHL(φ I-DO)
BUSY/ORDY
INTR
tPHL(W-BUS)
tPLH(φ I-BUS)
tPHL(φ I-INT)
16
tPLH(W-INT)
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Reset Timing
tW(R)
RESET
WR
trec(R-W)
Timing when using extended toggle
(1) Write mode setting
tW(T)
TOG
WR
trec(T-W)
tPLH(T-DO), tPHL(T-DO)
DATA OUT
Fixed data
DREQ
tPHL(T-DRE)
tPLH(T-INT)
INTR
(2) Send mode setting
tW(T)
TOG
WR
trec(W-T)
trec(T-CI)
CLK IN
BUSY/ORDY
TOG
tPHL(T-BUS)
tW(T)
trec(CI-T)
trec(T-CI)
tsu(CE-CI)
CLKE
th(CI-CE)
CLK IN
17
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Application Examples
1. Connection diagram
Data bus
Data bus
Control signal
Address bus
CS
M66307
MPU
INT
R/W
Decoder
Image memory and
memory management
unit
Address bus
(1) Connection example for memory data transfer by MPU
D0~D15
C/D
WR
DACK
DREQ
INTR
VCC
N.C.
M66307
CS
18
D0~D15
C/D
WR
DACK
DREQ
INTR
Decoder
Image memory and
memory management
unit
Control signal
(2) Connection example for DMA transfer
MPU
R/W
DMAC
DACK
DREQ
R/W
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
2. Connection diagram when using extended toggle
(1) Toggle configuration (When using data request clock (CLK IN) on the peripheral equipment side)
DACK
RESET
C/D
CS
WR
D0~D15
VCC
WR
DACK
C/D
DREQ
RES
INTR
(Slave)
CS
C/φ I
VCC
D8~D15
D0~D7
WR
VCC
D0~D7
CS
DACK
C/D
DREQ
EXD
RES
TOG
INTR
C/φ O
C/φ I
(Master)
D8~D15
EXD
TOG
C/φ O
CLKE
DO
CLKE
DO
GND
B/O
GND
B/O
CLK/φ OUT
DATA OUT
CLKE
CLK IN
INTR
ORDY
DREQ
TOG
Fig. 12 Wiring diagram of toggle configuration
(2) Toggle configuration (when using continuous clock (φ IN) from the system side)
M74××74, one chip
DACK
RESET
C/D
D
CS
S
Q
D
T
WR
φ IN
S
Q
T
1/2
2/2
D0~D15
VCC
WR
DACK
C/D
DREQ
RES
INTR
(Slave)
CS
C/φ I
VCC
D8~D15
D0~D7
WR
VCC
D0~D7
CS
DACK
C/D
DREQ
EXD
RES
TOG
INTR
C/φ O
C/φ I
(Master)
D8~D15
EXD
TOG
C/φ O
CLKE
DO
CLKE
DO
GND
B/O
GND
B/O
CLK/φ OUT
DATA OUT
INTR
ORDY
DREQ
TOG
Fig. 13 Wiring diagram of toggle configuration
19
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
(3) Toggle Operation Flowchart
IC mode
Reset
Master IC
Slave IC
Static mode
Static mode
Write mode
Refer to Common
instructions 1, (iv),
given below.
Send mode
Write mode
Write mode
Send mode
Initial setting
DREQ words, fixed beginning data
length, and output format are set.
Toggle input or mode inversion
command is set.
Data from data bus is stored.
Toggle input or mode inversion
command is set.
Data from data bus is stored,
and data is output.
Toggle input or mode inversion
command is set.
Data from data bus is stored,
and data is output.
Toggle input or mode inversion
command is set.
(4) Toggle Operation Instructions
1 Common instructions
(i) Set the operation mode by using mode inversion command or toggle input (TOG).
(ii) When setting operation mode with toggle input (TOG)
in the DREQ mode (flag F4 = 1), do not use the one-line
fixed data setting command.
(iii) The settings of master IC and slave IC are determined
during the initial setting.
When flag F6 is set to 1:
M66307 EXD is “H” → Slave IC
M66307 EXD is “L” → Master IC
(iv) After a reset and the first mode setting, slave IC is in the
send mode. However, transmission is impossible because there is no data in the line memory.
New data is written in this stage.
(v) It is impossible to control mode inversion by using operation mode setting command and extended toggle input
(TOG) together.
20
2 When CLK IN is used:
(i) Toggle operation is feasible when the circuit is connected
as shown in Fig. 12.
3 When φ IN is used:
(i) Toggle operation is feasible when the circuit is connected
as shown in Fig. 13.
(ii) At the initial setting, set clock input to CLK IN.
φ IN cannot be selected.
(iii) Divider clock output is not feasible.
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
3.Connection diagram when using extended 32-bit bus
(1) 32-bit bus configuration (when using data request clock (CLK IN) on the peripheral equipment side)
DACK
RESET
C/D
CS
WR
D16~D31
D0~D15
VCC
D8~D15
VCC
D8~D15
WR
CS
DACK
CS
DACK
C/D
DREQ
C/D
DREQ
RES
INTR
C/φ I
VCC
D0~D7
EXD
RES
TOG
INTR
C/φ O
C/φ I
CLKE
DO
GND
B/O
(Master)
D0~D7
(Slave)
WR
VCC
EXD
TOG
C/φ O
CLK/φ OUT
CLKE
DO
DATA OUT
GND
B/O
CLKE
CLK IN
ORDY
INTR
DREQ
BUSY
Fig. 14 Wiring diagram of 32-bit bus configuration
(2) 32-bit bus configuration (when using continuous clock (φ IN) from the system side)
M74××74, one chip
DACK
RESET
C/D
CS
D
WR
T
φ IN
S
Q
D
S
Q
T
1/2
2/2
D16~D31
D0~D15
VCC
D8~D15
VCC
D8~D15
WR
D0~D7
CS
DACK
CS
DACK
C/D
DREQ
C/D
DREQ
RES
INTR
C/φ I
VCC
EXD
RES
TOG
INTR
C/φ O
C/φ I
(Master)
D0~D7
(Slave)
WR
VCC
EXD
TOG
C/φ O
CLK/φ OUT
DATA OUT
CLKE
DO
CLKE
DO
GND
B/O
GND
B/O
INTR
DREQ
ORDY
BUSY
Fig. 15 Wiring diagram of 32-bit bus configuration
21
MITSUBISHI 〈DIGITAL ASSP〉
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
(3) 32-bit Bus Operation Flowchart
IC mode
Reset
Master IC
Slave IC
Static mode
Static mode
Write mode
Write mode
Send mode
Send mode
Write mode
Write mode
Initial setting
DREQ words, fixed beginning data
length, and output format are set.
Write mode is set.
Data from data bus is stored.
Send mode is set.
Data is output to data bus.
Write mode is set.
Data from data bus is stored.
Send mode is set.
(4) 32-bit Bus Operation Instructions
1 Common instructions
(i) Store the same value for both master IC and slave IC.
(ii) The settings of master IC and slave IC are determined
during the initial setting.
When flag F5 is set to 1:
M66307 EXD is “H” → Slave IC
M66307 EXD is “L” → Master IC
(iii) The upper 16 bits are sent to the master IC, and the lower
16 bits are sent to the slave IC. The IC that transmits data
first is determined by to which of FIFO or LIFO the output
setting command is set.
When 32-bit parallel data is stored three times, serial output data is transmitted, as shown in the table, according to
the output format determined by the output setting command.
2 CLK IN is used:
(i) Thirty-two-bit bus operation is feasible when the circuit is
connected as shown in Fig. 14.
3 When φ IN is used:
(i) Thirty-two-bit bus operation is feasible when the circuit is
used as shown in Fig. 15.
(ii) At the initial setting, set clock input to CLK IN. φ IN cannot
be used.
(iii) Divider clock output is not feasible.
Output format
FIFO
LIFO
Serial output data
MSB D31(1)~D0(1), D31(2)~D0(2), D31(3)~D0(3)
LSB
D0(1)~D31(1), D0(2)~D31(2), D0(3)~D31(3)
MSB D31(3)~D0(3), D31(2)~D0(2), D31(1)~D0(1)
LSB
D0(3)~D31(3), D0(2)~D31(2), D0(1)~D31(1)
D0(n) and D31(n): 32-bit parallel data stored at the n-th position.
22
Similar pages