TI ONET3301PA 155-mbps to 3.3-gbps limiting amplifier Datasheet

features
D Multi-Rate Operation from 155 Mbps Up To
D
D
D
D
D
D
D
D
3.3 Gbps
106-mW Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
Output Polarity Select
CML Data Outputs
Receive Signal Strength Indicator (RSSI)
Loss of Signal Detection
SLLS603C − MARCH 2004 − REVISED OCTOBER 2005
D Single 3.3-V Supply
D Surface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
applications
D SONET/SDH Transmission Systems at OC3,
D
D
OC12, OC24, OC48
1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
Gigabit Ethernet Receivers
description
The ONET3301PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 3.3 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mVp−p.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1200 mVp−p.
The ONET3301PA includes loss of signal detection, as well as a received signal strength indicator.
The ONET3301PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package and requires a single 3.3-V
supply.
This power efficient limiting amplifier typically dissipates less than 106 mW. It is characterized for operation from
–40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
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&#"! " ! $""! $ !'$ !$ $( !#$!
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!$!+ %% $!$
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block diagram
A simplified block diagram of the ONET3301PA is shown in Figure 1.
This compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2
COC1
VCC
Offset
Cancellation
GND
OUTPOL
VCCO
DIN+
+
DIN−
−
+
+
+
Gain Stage
Gain Stage
+
DOUT+
−
Input Buffer
DOUT−
Gain Stage
CML
Output
Buffer
DISABLE
Bandgap Voltage
Reference and
Bias Current
Generation
Loss of Signal
and
RSSI Detection
LOS
RSSI
TH
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
loss of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linearly proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
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The relation between the LOS assert voltage VAST (in mVp−p) and the external resistor RTH (in kΩ) connected
to the TH pin can be approximated as given below:
R
V
TH
[
AST
V
[
43 kW
* 600 W
ń mV p*p
AST
(1)
43 mV p*p
R
TH
ń kW ) 0.6
(2)
bandgap voltage and bias generation
The ONET3301PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
package
RSSI
COC1
COC2
GND
For the ONET3301PA, a small footprint 3 mm × 3 mm 16-pin QFN package is used with a lead pitch of 0,5 mm.
The pin out is shown in Figure 2.
16 15 14 13
VCC
1
DIN− 3
VCC 4
10 DOUT−
9 OUTPOL
6 7
8
GND
5
DISABLE
LOS
12 VCCO
11 DOUT+
TH
DIN+ 2
Figure 2. Pinout of ONET3301PA in a 3 mm y 3 mm 16-Pin QFN Package (Top View)
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terminal functions
The following table shows a pin description for the ONET3301PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
3.3-V ±10% supply voltage
VCC
1, 4
Supply
DIN+
2
Analog in
Noninverted data input. On-chip 50-Ω terminated to VCC
DIN–
3
Analog in
Inverted data input. On-chip 50-Ω terminated to VCC
TH
5
Analog in
LOS threshold adjustment with resistor to GND.
DISABLE
6
CMOS in
Disables CML output stage when set to high level.
LOS
7
CMOS out
GND
8, 16, EP
Supply
OUTPOL
9
CMOS in
Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
High level indicates that the input signal amplitude is below the programmed threshold level.
Circuit ground. Exposed die pad (EP) must be grounded.
DOUT–
10
CML out
Inverted data output. On-chip 50-Ω back-terminated to VCCO
DOUT+
11
CML out
Noninverted data output. On-chip 50-Ω back-terminated to VCCO
VCCO
12
Supply
RSSI
13
Analog out
COC1
14
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
COC2
15
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
3.3-V ±10% supply voltage for output stage
Analog output voltage proportional to the input data amplitude. Indicates the strength of the received
signal (RSSI).
absolute maximum ratings
over operating free-air temperature range unless otherwise noted†
VALUE
UNIT
–0.3 to 4
V
0.5 to 4
V
–0.3 to 4
V
±1
V
VCC, VCCO
VDIN+, VDIN−
Supply voltage, See Note 1
VTH,VDISABLE,VLOS,VOUTPOL,VDOUT+,
VDOUT−, VRSSI, VCOC1, VCOC2
Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI,
COC1, and COC2, See Note 1
VCOC_DIFF
VDIN_DIFF
Differential voltage between COC1 and COC2
ILOS
IDIN+, IDIN−, IDOUT+, IDOUT–
Current into LOS
ESD
ESD rating at all pins
TJ(max)
Tstg
Maximum junction temperature
Storage temperature range
TA
TL
Characterized free-air operating temperature range
−40 to 85
°C
260
°C
Voltage at DIN+, DIN–, See Note 1
Differential voltage between DIN+ and DIN–
Continuous current at inputs and outputs
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
±2.5
V
–1 to 9
mA
–25 to 25
mA
3
kV (HBM)
125
°C
−65 to 85
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
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recommended operating conditions
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
Supply voltage, VCC, VCCO
Operating free-air temperature, TA
−40
UNIT
dc electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at VCC = 3.3 V and
TA = 25°C
PARAMETER
VCC,VCCO
ICC
TEST CONDITIONS
MIN
Supply voltage
3
Supply current
DISABLE = low (excludes CML output current)
DISABLE = high
VOD
Differential data output voltage swing
rIN, rOUT
Data input/output resistance
V(IN_MIN)
V(IN_MAX)
DISABLE = low
600
Single ended
TYP
3.6
40
mA
10
780
1200
mVp−p
mVp−p
Ω
100
RSSI output voltage
Input = 80 mVp−p, RRSSI ≥ 10 kΩ
2800
RSSI linearity
20−dB input signal, VIN ≤ 80 mVpp
BER < 10–10
±3%
±8%
3
5
Data input overload
2.1
LOS hysteresis
LOS assert threshold range
223−1 PRBS (at 2.5 Gbps and 155 Mbps)
2.4
V
V
0.4
2.5
mVp−p
mVp−p
V
0.6
ISINK = –30 µA
ISOURCE = 1 mA
223−1 PRBS (at 2.5 Gbps and 155 Mbps)
LOS low voltage
mV
1200
CMOS input low voltage
LOS high voltage
V
32
Input = 2 mVp−p, RRSSI ≥ 10 kΩ
Data input sensitivity
UNIT
0.25
50
CMOS input high voltage
VTH
MAX
3.3
4.5
V
dB
5−40
mVp−p
ac electrical characteristics
over recommended operating conditions (unless otherwise noted), typical operating condition is at VCC = 3.3 V and
TA = 25°C
PARAMETER
Low frequency −3-dB bandwidth
TEST CONDITIONS
COC = open
COC = 100 nF
DJ
MAX
45
kHz
Gb/s
µVRMS
180
K28.5 pattern at 3.3 Gbps
223−1 PRBS equivalent pattern at 2.7 Gbps
8.5
25
9.3
30
K28.5 pattern at 2.1 Gbps
223−1 PRBS equivalent pattern at 155 Mbps
7.8
25
25
50
Input = 5 mVpp
6.5
RJ
Random jitter
tr
tf
Output rise time
20% to 80%
Output fall time
20% to 80%
PSNR
Power supply noise rejection
f < 2 MHz
tDIS
tLOS
Disable response time
Input = 10 mVpp
60
85
60
85
26
ps
ps
dB
20
2
psp−p
psRMS
3
LOS assert/deassert time
UNIT
70
3.3
Input referred noise
Deterministic jitter, See Note 2
TYP
0.8
Data rate
vNI
MIN
ns
100
µs
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
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APPLICATION INFORMATION
Figure 3 shows the ONET3301PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
Besides the ac-coupling capacitors, C1 through C4 in the input and output data signal lines, the only required
external component is the LOS threshold setting resistor RTH. In addition, an optional external filter capacitor
(COC) may be used if a lower cutoff frequency is desired.
RSSI
RSSI
COC1
COC2
GND
COC
Optional
VCC
DIN−
DOUT+
ONET3301PA
16-Pin QFN
TH
VCC
DOUT−
VCC
C3
C4
OUTPOL
DISABLE
DOUT−
OUTPOL
LOS
RTH
Figure 3. Basic Application Circuit With AC-Coupled I/Os
6
DOUT+
GND
DIN+
LOS
DIN−
C2
VCCO
DISABLE
DIN+
C1
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RANDOM JITTER
vs
DIFFERENTIAL INPUT VOLTAGE
900
10
800
9
8
700
Random Jitter − psRMS
VOD − Differential Output Voltage − mVP-P
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
600
500
400
300
200
7
6
5
4
3
2
100
1
0
0
1
2
3
4
5
0
6
5
10
15
20
25
30
35
40
VID − Differential Input Voltage − mVP-P
VID − Differential Input Voltage − mVP-P
Figure 5
Figure 4
SMALL SIGNAL GAIN
vs
FREQUENCY
BIT ERROR RATIO
vs
DIFFERENTIAL INPUT VOLTAGE
100
60
10-2
55
50
10-4
Small Signal Gain − dB
45
Bit Error Ratio
10-6
10-8
10-10
10-12
10-14
40
35
30
25
20
15
10
10-16
10-18
1.0
5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.01
1
10
100
1k
10k
Figure 7
Figure 6
POST OFFICE BOX 655303
0.1
f − Frequency − MHz
VID − Differential Input Voltage − mVP-P
• DALLAS, TEXAS 75265
7
SLLS603C − MARCH 2004 − REVISED OCTOBER 2005
OUTPUT EYE-DIAGRAM AT 3.3 GBPS AND
MAXIMUM INPUT VOLTAGE (1200 mVp−p)
VOD − Differential Output Voltage − 100 mV/Div
VOD − Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM AT 3.3 GBPS AND
MINIMUM INPUT VOLTAGE (5 mVp−p)
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 8
Figure 9
VOD − Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM AT
3.3 GBPS, 855C, AND MINIMUM
INPUT VOLTAGE (5 mVp−p)
t − Time − 100 ps/Div
Figure 10
8
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OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MAXIMUM INPUT VOLTAGE (1200 mVp−p)
VOD − Differential Output Voltage − 100 mV/Div
VOD − Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM AT 2.5 GBPS AND
MINIMUM INPUT VOLTAGE (5 mVp−p)
t − Time − 100 ps/Div
t − Time − 100 ps/Div
Figure 11
Figure 12
LOS ASSERT/DEASSERT VOLTAGE
vs
EXTERNAL RESISTANCE RTH
DIFFERENTIAL INPUT RETURN GAIN
vs
FREQUENCY
0
SDD11 − Differential Input Return Gain − dB
LOS Assert/Deassert Voltage − mVP-P
70
60
50
40
30
20
LOS Deassert Voltage
10
−5
−10
−15
−20
−25
−30
−35
−40
−45
LOS Assert Voltage
0
0
2
4
6
8
10
12
14
−50
0.1
RTH − Threshold Voltage Setting Resistance − kΩ
1
5
f − Frequency − GHz
Figure 13
Figure 14
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RECEIVE SIGNAL STRENGTH INDICATOR
vs
DIFFERENTIAL INPUT VOLTAGE
SDD22 − Differential Output Return Gain − dB
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
0.1
1
5
RSSI − Receive Signal Strength Indicator Voltage − mV
DIFFERENTIAL OUTPUT RETURN GAIN
vs
FREQUENCY
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
0
f − Frequency − GHz
20
30
40
Figure 16
POST OFFICE BOX 655303
50
60
70
80
VID − Differential Input Voltage − mVP-P
Figure 15
10
10
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ONET3301PARGTR
NRND
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
301P
PYML
ONET3301PARGTRG4
NRND
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
301P
PYML
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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31-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ONET3301PARGTR
Package Package Pins
Type Drawing
QFN
RGT
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ONET3301PARGTR
QFN
RGT
16
3000
338.1
338.1
20.6
Pack Materials-Page 2
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