IRF IP2003APBF Synchronous buck multiphase optimized lga power block intergrated power semiconductors,drivers&passive Datasheet

PD-97051A
iP2003APbF
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
•
•
•
•
•
•
•
•
•
Integrated Power Semiconductors, Drivers & Passives
Full function multiphase building block
Output current 40A continuous with no derating up to
TPCB = 100°C and TCASE = 100°C
Operating frequency up to 1.0 MHz
Proprietary packaging enables ultra low Rthj-case top
Efficient dual sided cooling
Small footprint low profile (9mm x11mm x 2.2mm) package
Optimized for very low power losses
LGA interface
Ease of design
iP2003APbF Power Block
Description
The iP2003APbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM
controller, the output inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin #
1
iP2003APbF Internal Block Diagram
VSWS1
VSWS2
VIN
PRDY
ENABLE
PWM
VDD
MOSFET
Driver with
dead time
control
VSW
PGND
INTERFACE
CONNECTION
PARTS
PER BAG
PARTS
PER
REEL
iP2003APbF
LGA
10
---
iP2003ATRPbF
LGA
---
1000
PACKAGE
DESCRIPTION
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T&R
ORIENTATION
Fig 12
8/16/06
Pin N am e
Pin Function
V DD
Supply voltage for the internal circuitry.
W hen set to logic level high, internal circuitry
of the device is enabled. W hen set to logic
level low, the PRD Y pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current reduces to 10µ A.
2
ENA BLE
3
PW M
T T L-level input signal to M OSFET drivers.
4
PRD Y
Power Ready - This pin indicates the status of
EN AB LE or V D D . T his output will be driven
low when EN ABLE is logic low or when V D D
is less than 4.4V (typ.). W hen EN AB LE is
logic high and V D D is greater than 4.4V (typ.),
this output is driven high. T his output has a
10mA source and 1mA sink capability.
5, 7
PG ND
6
V SW
8
V IN
9
V SW S1
10
V SW S2
Power G round - connection to the ground of
bulk and filter capacitors.
Switching N ode - connection to the output
inductor.
Input voltage pin. External bypass ceramic
capacitors must be added directly next to the
block.
Floating pin. For internal use. E xternally, short
to V SW S2 pin only .
Floating pin. For internal use. E xternally, short
to V SW S1 pin only .
1
iP2003APbF
All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Parameter
Symbol
VIN to PGND
VIN
VDD to PGND
PWM to PGND
Enable to PGND
Output RMS Current
Typ
-
Max
16
Units
V
VDD
-
-
V
PWM
-0.3
-
6.0
VDD +0.3
V
Not to exceed 6.0V
ENABLE
IOUT
-0.3
-
VDD +0.3
V
Not to exceed 6.0V
-
-
40
A
Measured at VSW
Typ
Max
Units
5.0
-
5.5
13.2
V
V
Recommended Operating Conditions:
Min
Parameter
Symbol
Supply Voltage
VDD
Input Voltage
Output Voltage
VIN
4.6
3.0
VOUT
0.8
-
3.3
V
IOUT
300
-40
-
40
1000
85
125
A
kHz
%
°C
Output Current
Operating Frequency
Operating Duty Cycle
Block Temperature
Conditions
Min
-
fsw
D
TBLK
Electrical Specifications @ VDD = 5V (unless otherwise specified):
Parameter
Symbol
Min
Typ
Max
Units
PLOSS
Block Power Loss c
9.4
11.7
W
Conditions
Conditions
VIN=12V, VOUT=1.3V
IOUT=40A, fSW=1MHz
Turn On Delay d
td(on)
-
63
-
Turn Off Delay d
VIN Quiescent Current
td(off)
-
26
-
IQ-VIN
-
-
1.0
mA
Enable = 0V, VIN=12V
VDD Quiescent Current
IQ-VDD
-
10
-
µA
Enable = 0V, VDD=5V
Under-Voltage Lockout
Start Threshold
UVLO
VSTART
4.2
4.4
4.5
V
VHvs-UVLO
-
150
-
mV
ENABLE
VIH
2.1
-
-
V
VIL
-
-
0.8
PRDY
VOH
4.5
4.6
-
VOL
-
0.1
0.2
Logic Level High
PWM
VOH
2.1
-
-
Logic Level Low
VOL
-
-
0.8
Hysteresis
Enable
Input Voltage High
Input Voltage Low
Power Ready
Logic Level High
Logic Level Low
PWM Input
ns
V
L = 0.3µH
VDD=4.6V, ILoad=10mA
VDD <UVLO Threshold, ILoad = 1mA
V
 Measurement made using six 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
‚ Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
2
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iP2003APbF
16
VIN = 12V
VOUT = 1.3V
14
f sw
12
L
Power Loss (W)
= 1MHz
T BLK = 125°C
= 0.30µH
10
Maximum
8
Typical
6
4
2
0
0
5
10
15
20
25
30
35
40
Output Current (A)
Fig. 1: Power Loss vs. Current
Case Temperature (°C)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
40
Safe
Operating
Area
36
Output Current (A)
32
28
Tx
24
20
16
VIN = 12V
VOUT = 1.3V
12
8
f sw
= 1MHz
L
= 0.30µH
4
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
PCB Temperature (°C)
Fig. 2: Safe Operating Area (SOA) vs. TPCB & TCASE
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3
iP2003APbF
Typical Performance Curves
1.20
f sw
= 1MHz
5
1.16
L
= 0.3µH
T BLK = 125°C
4
6
1.12
3
1.08
2
1.04
1
1.00
0
-1
0.96
3
4
5
6
7
8
9
10
11
12
1.16
4.0
1.12
3.0
1.08
2.0
VIN = 12V
I OUT = 40A
1.04
f sw
1.00
-1.0
0.8
1.2
1.6
-1
-2
-3
0.80
-4
0.75
-5
0.70
-6
0.65
Power Loss (Normalized)
0
IOUT = 40A
L = 0.30µH
TBLK = 125°C
-7
300
400
500
600
700
2.8
3.2
3.6
800
900 1000
VIN = 12V
VOUT = 1.3V
I OUT = 40A
1.04
f sw
1.0
= 1MHz
T BLK = 125°C
1.02
1.5
0.5
1.00
0.0
0.98
-0.5
0.1
0.3
Switching Frequency (kHz)
0.5
0.7
0.9
Output Inductance (µH)
Fig. 5: Normalized Power Loss vs. Frequency
Fig. 6: Normalized Power Loss vs. Inductance
100
Average IDD (mA)
90
80
70
60
Does not include
PRDY current
TBLK = 25°C
50
40
300
400
500
600
700
800
900
1000
Switching Frequency (kHz)
4
Fig. 7: IDD (VDD current) vs. Frequency
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SOA Temp Adjustment (°C)
Power Loss (Normalized)
1.06
SOA Temp Adjustment (°C)
VIN = 12V
VOUT = 1.3V
200
2.4
Fig. 4: Normalized Power Loss vs. VOUT
1
0.85
2.0
Output Voltage (V)
1.05
0.90
0.0
0.96
13
Fig. 3: Normalized Power Loss vs. VIN
0.95
= 1MHz
L
= 0.30µH
T BLK = 125°C
Input Voltage (V)
1.00
1.0
SOA Temp Adjustment (°C)
1.24
Power Loss (Normalized)
7
VOUT = 1.3V
I OUT = 40A
SOA Temp Adjustment (°C)
Power Loss (Normalized)
1.28
iP2003APbF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum
current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn
out through the printed circuit board and the top of the case.
Case Temperature (ºC)
Procedure
0
30
40
50
60
70
80
90
100
110
120
36
34
32
Output Current (A)
3) Draw a horizontal line from the intersection of the vertical
line with the SOA curve to the Y-axis. The point at which
the horizontal line meets the Y-axis is the SOA current.
20
42
40
38
1) Draw a line from Case Temp axis at TCASE to the PCB
Temp axis at TPCB.
2) Draw a vertical line from the TX axis intercept to the SOA
curve.
10
30
28
26
24
22
20
TX
18
16
14
Safe
Operating
Area
VIN = 12V
VOUT = 1.3V
fSW = 1MHz
L=0.3uH
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
110
120
PCB Temperature (ºC)
Calculating Power Loss and SOA for Different Operating Conditions
To calculate power loss for a given set of operating conditions, the following procedure should be followed:
Determine the maximum current for each iP2003APbF and obtain the maximum power loss from Fig 1. Use the curves
in Figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. The
maximum power loss under the operating conditions is then the product of the power loss from Fig. 1 and the normalized values.
To calculate the SOA for a given set of operating conditions, the following procedure should be followed:
Determine the maximum PCB temperature and Case temperature at the maximum operating current of each
iP2003APbF. Obtain the SOA temperature adjustments that match the operating conditions in the application from
Figs. 3, 4, 5 and 6. Then, add the sum of the SOA temperature adjustments to the Tx axis intercept in Fig 2.
The example below explains how to calculate maximum power loss and SOA.
Example:
Operating Conditions
Output Current = 40A
Sw Freq= 900kHz
Input Voltage = 10V
Inductor = 0.2µH
Output Voltage = 3.3V
TPCB = 100°C, TCASE = 110°C
Calculating Maximum Power Loss:
(Fig. 1)
(Fig. 3)
(Fig. 4)
(Fig. 5)
(Fig. 6)
Maximum power loss = 15W
Normalized power loss for input voltage ≈ 0.98
Normalized power loss for output voltage ≈ 1.14
Normalized power loss for frequency ≈ 0.94
Normalized power loss for inductor value ≈ 1.013
Calculated Maximum Power Loss for given conditions = 15W x 0.98 x 1.14 x 0.94 x 1.013 ≈ 15.96W
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5
iP2003APbF
Calculating SOA Temperature:
(Fig.
(Fig.
(Fig.
(Fig.
3)
4)
5)
6)
SOA Temperature Adjustment
SOA Temperature Adjustment
SOA Temperature Adjustment
SOA Temperature Adjustment
for
for
for
for
input voltage ≈ -0.5°C
output voltage ≈ 3.3°C
frequency ≈ -1.2°C
inductor value ≈ 0.25°C
TX axis intercept temp adjustment = - 0.5°C + 3.3°C - 1.2°C + 0.25°C ≈ 1.85°C
Assuming TCASE = 110°C & TPCB = 100°C:
The following example shows how the SOA current is adjusted for a TX increase of 1.85°C.
Case Temperature (°C)
Output Current (A)
0
10
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
20
30
40
50
60
70
80
90
100
110
120
TX
Safe
Operating
Area
VIN = 12V
VOUT = 1.3V
fSW = 1MHz
L=0.3uH
0
10
20
30
40
50
60
70
80
90
100
110
120
PCB Temperature (ºC)
PIN = V IN Average x IIN Average
PDD = V DD Average x IDD Average
POU T = VOUT Average x IOU T Average
PLOSS = (PIN + PDD ) - POUT
Average
Input
Current
(IIN )
90%
A
DC
Average
VDD
Current
(IDD )
Average
VDD
Voltage
(VDD )
A
V
DC
PRDY
VIN
ENABLE
PWM
V
PWM
10%
AverageOutput
Current (I
OUT )
VSW
90%
A
VDD
PGND
iP2003APbF
iP2003A
VSW
Averaging
Circuit
V
Fig. 8: Power Loss Test Circuit
6
Average
Input
Voltage
(VIN )
Average
Output
Voltage
(VOUT )
10%
td(on)
td(off)
Fig. 9: Timing Diagram
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iP2003APbF
PCB Layout Guidelines
One of the most critical elements of proper PCB layout with iP2003APbF is the placement of the external
input bypass capacitors and the routing of the connecting power tracks.
It is recommended that the designer uses the following guidelines:
1.
2.
3.
4.
The diagram below suggests the addition of the input bypass capacitors either on the top side of
the PCB (capacitors C1-C6) or top and bottom side (C7, C8), if placement on the bottom side is
feasible. The amount of the input capacitors is based on the input ripple current handling
requirement of the iP2003APbF. To support 12A input RMS current, based on 12V input, 1.3V
and 40A output and 1MHz, the iP2003APbF will require enough input ceramic capacitors to
support the input RMS AC current. These capacitors must be placed as close to the iPOWIR
device as possible.
In the diagram below, observe the routing of the power tracks that connect the external bypass
capacitors.
Provide a mid-layer solid ground plane with connections to the top through vias.
Refer to IR application note AN-1029a to determine the size of the vias and the copper weight
and thickness when designing the PCB.
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7
iP2003APbF
2.5 [0.10]
2.0 [0.08]
0508
6B7D
iP2003A
iP2003AP
XX
0
A
B
0.3556
9.00
[.354]
6
3.9116
2X
8.509
0.15 [.006] C
1.9050
Fig 10: Maximum TCASE measurement location
VS WS 1
0
1.2337
1.3593
VS WS2 VDD
2.2243
0.332
VIN
ORIENTATION
CORNER ID
3.253
PGND
11.00
[.433]
ENABLE
PGND
7.1773
PWM
VSW
0.15 [.006] C
T OP VIEW
2X
6
2.31 [.0909]
2.13 [.0839]
C
S IDE VIEW
(1)
X
(2),(3)
X
(4)
(5)
8
Y
Y
X
Y
X
Y
1.1430
2.1016
(6)
1.1430
1.1016
(7)
1.1430
1.2192
(8)
1.778
5.334
(9),(10)
X
Y
X
Y
X
Y
X
Y
4.5183
3.429
3.429
3.429
3.048
4.953
2.032
1.016
0.635
6.9567
8.6124
PRDY
8.9248
BOTTOM VIEW
5
NOTES :
1.
2.
3.
4.
5
DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994.
DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ].
CONTROLLING DIMENS ION: MILLIMETER
LAND DES IGNAT ION PER JES D MO 222, S PP-010.
PRIMARY DATUM C IS S EATING PLANE.
6
BILATERAL TOLERANCE Z ONE IS APPLIED TO EACH S IDE OF T HE
PACKAGE BODY.
LAYOUT NOTES :
1. LAND PATT ERN ON US ER’S PCB S HOULD BE AN IDENTICAL MIRROR
IMAGE OF T HE PATTERN S HOWN IN THE BOT TOM VIEW.
2. LANDS S HOULD BE S OLDER MAS K DEFINED.
Fig 11: Mechanical Drawing
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iP2003APbF
Refer to the following application notes for detailed guidelines and suggestions when
implementing iPOWIR Technology products:
AN-1030: Applying iPOWIR Products in Your Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
AN-1047: Graphical solution for two branch heatsinking Safe Operating Area
Detailed explanation of the dual axis SOA graph and how it is derived.
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
BGA and LGA Packages
This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on
printed circuit boards, accounting for thermal and electrical performance and assembly considerations .
Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as
soldering, pick and place, reflow, cleaning and reworking recommendations.
AN-1029a: Optimizing a PCB Layout for an iPowir Technology Design
IRDCiP2003A : Reference design for iP2003APbF
0508
6B7D
iP2003A
iP2003AP
0508
6B7D
iP2003A
iP2003AP
XX
24mm
XX
12mm
FEED DIRECTION
NOTES :
1. OUT LINE CONFORMS T O EIA-481 & EIA-541.
iP2003APbF,
iP2003A, LGALGA
Fig. 12: Tape & Reel Information
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9
iP2003APbF
XX
Fig. 13: Part Marking
A
H
I
A
B,C
J
G
B
E
D
E
C
F
D
S T ENCIL DES IGN
X
Y
X
Y
X
Y
X
Y
0.9906
1.9492
0.9906
0.9492
0.9906
1.0668
1.6764
5.2324
F
G
H
I,J
X
3.3274
Y
X
3.3274
3.3274
Y
2.9464
X
4.8514
1.9304
0.9144
0.5334
Y
X
Y
NOT ES :
1. T HIS VIEW IS S T ENCIL S QUEEGEE VIEW
2. DIMENS IONS ARE S HOWN IN MILLIMET ERS .
3. T HIS OPENING IS BAS ED ON US ING 150 MICRON S T ENCIL.
IF US ING DIFFERENT T HICKNES S S TENCIL, T HIS OPENING
NEEDS T O BE ADJUS T ED ACCORDINGLY
The recommended reflow peak temperature not to exceed 260°C. The total furnance time is approximately
5 minutes with approximately 10 seconds at the peak temperature.
Fig.14: Recommended solder profile and stencil design
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/06
10
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