IDT IDT70T3799MS133BBG High-speed 2.5v 256/128k x 72 synchronous dual-port static ram with 3.3v or 2.5v interface Datasheet

HIGH-SPEED 2.5V
ADVANCED
256/128K x 72
IDT70T3719/99M
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
◆
◆
◆
◆
◆
◆
◆
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
Functional Block Diagram
BE7L
BE7R
BE0L
BE0R
FT/PIPEL
1/0
0a 1a
0h 1h
1h 0h
1a 0a
a
h
h
a
FT/PIPER
1/0
R/WL
R/WR
CE0L
CE1L
1
1
0
0
B
W
0
L
1/0
OEL
B
W
7
L
D OUT0-8_L
D OUT9-17_L
DO UT 18-26_L
D OUT 27-35_L
D OUT 36-44_L
D OUT 45-53_L
D OUT 54-62_L
D OUT 63-72_L
1h 0h
FT/PIPEL
B
W
7
R
B
W
0
R
CE0R
CE1R
1/0
OER
D OUT0-8_R
D OUT9-17_R
D OUT18-26_R
DOUT27-35_R
DOUT36-44_R
DOUT45-53_R
DOUT54-62_R
DOUT63-72_R
1a 0a
0a 1a
,
0h 1h
0/1
FT/PIPER
0/1
a
h
h
a
256/128K x 72
MEMORY
ARRAY
Byte 7
Byte 0
Byte 0
Byte 7
I/O0L - I/O71L
DIN_L
I/O0R - I/O71R
DIN _R
CLKL
CLKR
A17L (1)
A 0L
REPEATL
ADSL
CNTENL
,
A17R (1)
Counter/
Address
Reg.
Counter/
Address
Reg.
ADDR_R
ADDR_L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0L
CE1L
R/W L
A 0R
REPEATR
ADSR
CNTENR
CE0R
CE1R
TDI
JTAG
TDO
R/W R
COL L
INTL
TCK
TMS
TRST
COL R
INTR
(2)
ZZ L
ZZ
CONTROL
ZZ R
(2)
LOGIC
NOTES:
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
5687 drw 01
JUNE 2005
1
©2005 Integrated Device Technology, Inc.
DSC 5687/1
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3719/99M has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3719/99M can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.42
2
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4,5)
70T3719/99M
BBG-324(6)
324-Pin BGA
Top View(7)
06/27/05
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
I/O39R
I/O38R
I/O37R
I/O36R
COLL
A15L
A12L
A8L
BE7L
BE2L
CE1L
ADSL
A6L
A1L
I/O32R
I/O33R
I/O34R
I/O35R
A
B
I/O39L
I/O38L
I/O37L
I/O36L
TDO
A17L(1)
A13L
A10L
BE6L
BE5L
BE1L
OEL
REPEATL
A0L
I/O32L
I/O33L
I/O34L
I/O35L
B
C
I/O40R
I/O41R
I/O42R
I/O43R
INTL
A16L
A11L
A7L
BE0L
CE0L
R/WL CNTENL
A4L
A3L
I/O31R
I/O30R
I/O29R
I/O28R
C
D
I/O40L
I/O41L
I/O42L
I/O43L
TDI
NC
A14L
A9L
BE4L
BE3L
CLKL
A5L
A2L
ZZL
I/O31L
I/O30L
I/O29L
I/O28L
D
E
I/O47R
I/O46R
I/O45R
I/O44R PL/FTL
VDD
VDDQL
VDDQR
VDDQR
VDDQL
VDDQL
VDDQR
VDDQR
OPTL
I/O24R
I/O25R
I/O26R
I/O27R
E
F
I/O47L
I/O46L
I/O45L
I/O44L
VDD
VDD
VDDQL
Vs s
Vs s
Vs s
VDD
VDD
VDD
VDD
I/O24L
I/O25L
I/O26L
I/O27L
F
G
I/O48R
I/O49R
I/O50R
I/O51R
VDDQR VDDQR
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQR
VDDQR
I/O23R
I/O22R
I/O21R
I/O20R
G
H
I/O48L
I/O49L
I/O50L
I/O51L
VDDQL
VDDQL
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQL
VDDQL
I/O23L
I/O22L
I/O21L
I/O20L
H
J
I/O55R
I/O54R
I/O53R
I/O52R
VDDQR
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQR
I/O16R
I/O17R
I/O18R
I/O19R
J
K
I/O55L
I/O54L
I/O53L
I/O52L
VDDQR
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQR
I/O16L
I/O17L
I/O18L
I/O19L
K
L
I/O56R
I/O57R
I/O58R
I/O59R
VDDQL
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQL
I/O15R
I/O14R
I/O13R
I/O12R
L
M
I/O56L
I/O57L
I/O58L
I/O59L
VDDQL
VDD
Vs s
Vs s
Vs s
Vs s
Vs s
Vs s
VDDQL
VDDQL
I/O15L
I/O14L
I/O13L
I/O12L
M
N
I/O63R
I/O62R
I/O61R
I/O60R
VDDQR VDDQR
VDDQL
VDDQL
Vs s
Vs s
VDD
VDDQR
VDDQR
VDDQR
I/O8R
I/O9R
I/O10R
I/O11R
N
P
I/O63L
I/O62L
I/O61L
I/O60L
ZZR
TMS
VDD
VDD
VDD
VDDQL
VDDQL
VDD
VDD
OPTR
I/O8L
I/O9L
I/O10L
I/O11L
P
R
I/O64R
I/O65R
I/O66R
I/O67R
COLR
A17R(1)
A12R
A9R
BE4R
CE0R
OER
A6R
A2R
A1R
I/O7R
I/O6R
I/O5R
I/O4R
R
T
I/O64L
I/O65L
I/O66L
I/O67L PL/FTR A16R
A13R
A7R
BE7R
BE3R
CE1R
ADSR
A4R
A0R
I/O7L
I/O6L
I/O5L
I/O4L
T
U
I/O71R
I/O70R
I/O69R
I/O68R
TCK
INTR
A14R
A10R
BE2R
BE6R
BE1R
R/WR REPEATR
A3R
I/O0R
I/O1R
I/O2R
I/O3R
U
V
I/O71L
I/O70L
I/O69L
I/O68L
TRST
NC
A15R
A11R
A8R
BE5R
BE0R
CLKR CNTENR
A5R
I/O0L
I/O1L
I/O2L
I/O3L
V
1
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
12
13
5687 tbl 01
NOTES:
1. Pin is a NC for IDT70T3799.
2. All VDD pins must be connected to 2.5V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 19mm x 19mm x 1.4mm, with 1.76mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)(6)
R/WL
R/WR
Read/Write Enable (Input)
OEL
OER
Output Enable (Input)
A0L - A17L(5)
A0R - A17R(5)
Address (Input)
I/O0L - I/O71L
I/O0R - I/O71R
Data Input/Output
CLKL
CLKR
Clock (Input)
PL/FTL
PL/FTR
Pipeline/Flow-Through (Input)
ADSL
ADSR
Address Strobe Enable (Input)
CNTENL
CNTENR
Counter Enable (Input)
REPEATL
REPEATR
Counter Repeat(3)
BE0L - BE7L
BE0R - BE7R
Byte Enables (9-bit bytes) (Input)(6)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
OPTL
OPTR
Option for selecting V DDQX(1,2) (Input)
ZZL
ZZR
Sleep Mode pin(4) (Input)
VDD
Power (2.5V)(1) (Input)
VSS
Ground (0V) (Input)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz) (Input)
TMS
Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
INTL
INTR
Interrupt Flag (Output)
COLL
COLR
Collision Alert (Output)
5687 tbl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADS X.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A17x is a NC for the IDT70T3799M.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
4
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
OE
CLK
CE0
CE1
X
½
H
X
X
½
X
X
½
X
½
X
(1,2,3,4,5)
R/W
ZZ
I/O Operation(6)
MODE
All BE = X
X
L
All Bytes= High-Z
Deselected: Power Down
L
All BE = X
X
L
All Bytes = High-Z
Deselected: Power Down
L
H
All BE = H
X
L
All Bytes = High-Z
All Bytes Deselected
L
H
BEn = L, All other BE = H
L
L
Byte n = DIN, All other Bytes = High-Z Write to Byte X Only
½
L
H
BE4-7 = L, BE0-3 = H
L
L
Byte 4-7 = DIN, Byte 0-3 = High-Z
Write to Lower Bytes Only
X
½
L
H
BE4-7 = H, BE0-3 = L
L
L
Byte 4-7 = High-Z, Byte 0-3 = DIN
Write to Upper Bytes Only
X
½
L
H
BE0-7 = L
L
L
Byte 0-7 = DIN
Write to All Bytes
L
½
L
H
BEn = L, All other BE = H
H
L
Byte n = DOUT, All other Bytes = High-Z Read Byte X Only
L
½
L
H
BE4-7 = L, BE0-3 = H
H
L
Byte 4-7 = DOUT, Byte 0-3 = High-Z
Read Lower Bytes Only
L
½
L
H
BE4-7 = H, BE0-3 = L
H
L
Byte 4-7 = High-Z, Byte 0-3 = DOUT
Read Upper Bytes Only
L
½
L
H
All BE = L
H
L
All Bytes = DOUT
Read All Bytes
H
X
X
X
All BE = X
X
L
All Bytes = High-Z
Outputs Disabled
X
X
X
X
All BE = X
X
H
All Bytes = High-Z
Sleep Mode
Byte Enables
5687 tbl 03
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = Don't Care. See Truth Table II.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5. For the examples shown here, BEn may correspond to any of the eight byte enable signals.
Truth Table II—Address Counter Control
(1,2)
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS(4)
CNTEN
REPEAT(4,6)
I/O(3)
An
X
An
½
L
X
H
DI/O(n)
(5)
MODE
External Address Used
X
An
An + 1
½
H
L
H
DI/O(n+1) Counter Enabled-Internal Address generation
X
An + 1
An + 1
½
H
H
H
DI/O(n+1) Enabled Address Blocked-Counter disabled (An + 1 reused)
X
X
An
½
X
X
L
DI/O(n)
Counter Set to last valid ADS load
5687 tbl 04
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
5
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Ambient
Temperature
Grade
GND
VDD
0 C to +70 C
0V
2.5V + 100mV
-40OC to +85OC
0V
2.5V + 100mV
O
Commercial
Industrial
(1)
O
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
5687 tbl 05
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
V DD
Core Supply Voltage
2.4
2.5
2.6
V
V DDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
V SS
Ground
0
0
0
V
V IH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
1.7
____
VDDQ + 100mV (2)
V
V IH
Input High Voltage
JTAG
1.7
____
VDD + 100mV (2)
V
V IH
Input High Voltage ZZ, OPT, PIPE/FT
V DD - 0.2V
____
VDD + 100mV (2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
_
5687 tbl 06a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and V DDQX for that port must be supplied as indicated
above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
V DD
Parameter
Core Supply Voltage
(3)
VDDQ
I/O Supply Voltage
V SS
Ground
V IH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
V IH
Input High Voltage
JTAG
V IH
Input High Voltage ZZ, OPT, PIPE/FT
Min.
Typ.
Max.
Unit
2.4
2.5
2.6
V
3.15
3.3
3.45
V
0
0
0
V
2.0
____
VDDQ + 150mV (2)
V
1.7
____
VDD + 100mV (2)
V
V DD - 0.2V
____
VDD + 100mV (2)
V
(1)
____
0.8
V
____
0.2
V
_
VIL
Input Low Voltage
-0.3
VIL
Input Low Voltage ZZ, OPT, PIPE/FT
-0.3(1)
5687 tbl 06b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than tCYC /2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated
above.
6.42
6
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
V DD Terminal Voltage
with Respect to GND
-0.5 to 3.6
VTERM(2)
(VDDQ)
V DDQ Terminal Voltage
with Respect to GND
-0.3 to V DDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to V DDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT(For V DDQ = 3.3V) DC Output Current
50
IOUT(For V DDQ = 2.5V) DC Output Current
40
V
mA
mA
5687 tbl 07
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance (1)
(TA = +25°C, F = 1.0MHZ)
Conditions(2)
Max.
Unit
Input Capacitance
VIN = 0V
15
pF
Output Capacitance
VOUT = 0V
10.5
Symbol
CIN
(2)
COUT
Parameter
pF
5687 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3719/99M
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
Parameter
Test Conditions
Input Leakage Current(1)
(1,2)
JTAG & ZZ Input Leakage Current
(1,3)
Output Leakage Current
Output Low Voltage
(1)
(1)
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
10
µA
VDD = Max., V IN = 0V to VDD
___
±30
µA
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
___
10
µA
IOL = +4mA, VDDQ = Min.
___
0.4
V
V
V
VOH (3.3V)
Output High Voltage
IOH = -4mA, V DDQ = Min.
2.4
___
VOL (2.5V)
Output Low Voltage (1)
IOL = +2mA, VDDQ = Min.
___
0.4
VOH (2.5V)
Output High Voltage (1)
IOH = -2mA, V DDQ = Min.
2.0
___
V
5687 tbl 09
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
7
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (3) (VDD = 2.5V ± 100mV)
70T3719/99M
S166
Com'l
Only
Symbol
IDD
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
Izz
Parameter
Test Condition
Version
70T3719/99M
S133
Com'l
& Ind
Typ. (4)
Max.
Typ. (4)
Max.
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
640
900
520
740
IND
S
___
___
520
900
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
350
460
280
380
IND
S
___
___
280
470
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
500
650
400
500
IND
S
___
___
400
620
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
COM'L
S
12
20
12
20
IND
S
___
___
12
25
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX(1)
COM'L
S
500
650
400
500
IND
S
___
___
400
620
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX(1)
COM'L
S
12
20
12
20
IND
S
___
___
12
25
Unit
mA
mA
mA
mA
mA
mA
5687 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = V IL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, I SB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
6.42
8
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
Figure 1
5687 tbl 11
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
5687 drw 03
Figure 1. AC Output Test load.
∆ tCD
(Typical, ns)
∆ Capacitance (pF) from AC Test Load
6.42
9
5687 drw 04
,
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3719/99M
S166
Com'l
Only
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)(1)
(1)
70T3719/99M
S133
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
20
____
25
____
ns
ns
tCYC2
Clock Cycle Time (Pipelined)
6
____
7.5
____
tCH1
Clock High Time (Flow-Through)(1)
8
____
10
____
ns
tCL1
Clock Low Time (Flow-Through)(1)
8
____
10
____
ns
tCH2
Clock High Time (Pipelined)(2)
2.4
____
3
____
ns
ns
(1)
tCL2
Clock Low Time (Pipelined)
2.4
____
3
____
tSA
Address Setup Time
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.7
____
1.8
____
ns
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
tSB
Byte Enable Setup Time
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.7
____
1.8
____
ns
ns
tHW
R/W Hold Time
0.5
____
0.5
____
tSD
Input Data Setup Time
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
ns
tSAD
ADS Setup Time
1.7
____
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
0.5
____
ns
tSCN
CNTEN Setup Time
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.4
____
4.6
ns
Output Enable to Output Low-Z
1
____
1
____
ns
tOHZ
Output Enable to Output High-Z
1
3.6
1
4.2
ns
tCD1
Clock to Data Valid (Flow-Through)(1)
____
12
____
15
ns
tCD2
Clock to Data Valid (Pipelined)(1)
____
3.6
____
4.2
ns
Data Output Hold After Clock High
1
____
1
____
ns
tCKHZ
Clock High to Output High-Z
1
3.6
1
4.2
ns
tCKLZ(4)
Clock High to Output Low-Z
1
____
1
____
ns
tINS
Interrupt Flag Set Time
____
7
____
7
ns
tINR
Interrupt Flag Reset Time
____
7
____
7
ns
tCOLS
Collision Flag Set Time
____
3.6
____
4.2
ns
tCOLR
Collision Flag Reset Time
____
3.6
____
4.2
ns
tZZSC
Sleep Mode Set Cycles
2
____
2
____
cycles
tZZRC
Sleep Mode Recovery Cycles
3
____
3
____
cycles
5
____
6
____
ns
tOLZ(4)
(4)
tDC
(4)
Port-to-Port Delay
tCO
tOFS
Clock-to-Clock Offset
Please refer to collision Detection Timing Table
on Page 19.
Clock-to-Clock Offset for Collision Detection
5687 tbl 12
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. Guaranteed by design (not production tested).
6.42
10
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
BEn
R/W
tSW tHW
tSA
ADDRESS
(4)
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
,
tOE
5687 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
(3)
CE1
tSB
tHB
BEn
tSB
R/W
tHB
tSW tHW
tSA
ADDRESS
tHC
(4)
tHA
An
An + 1
tCD1
An + 2
tCKHZ
Qn
DATAOUT
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
Qn + 2
tOLZ
(5)
tDC
(1)
tOE
5687 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
11
,
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read
(1,2)
tCYC2
tCH2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
tCKHZ
Q0
DATAOUT(B1)
tSC
tCKHZ
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
Q3
tCKLZ
tDC
tHA
A0
ADDRESS(B2)
tCD2
Q1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
tCKHZ
tCD2
,
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5687 drw 07
Timing Waveform of a Multi-Device Flow-Through Read
tCH1
(1,2)
tCYC1
tCL1
CLK
tSA
tH
A
A0
ADDRESS(B1)
CE0(B1)
tSC tHC
tSC tHC
tCD1
tCD1
D0
DATAOUT(B1)
tDC
tSA
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tCKHZ
(1)
tCD1
tCD1
D3
D1
tDC
tCKLZ
(1)
D5
tCKHZ(1)
tCKLZ
(1)
tHA
A0
A1
A6
A5
A4
A3
A2
tSC tHC
CE0(B2)
tSC tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
,
5687 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3719/99M for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN, and REPEAT = VIH.
6.42
12
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A
"
ADDRESS"A"
NO
MATCH
MATCH
tSD
DATAIN"A"
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
,
tDC
5687 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + t CYC2 + t CD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,4)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
"A"
NO
MATCH
MATCH
tSD
DATAIN
tHA
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
,
5687 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + t CD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
13
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
(4)
READ
NOP
WRITE
READ
5687 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)
tCH2
(2)
tCYC2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 3
An + 4
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
5687 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
14
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKLZ
tCKHZ
READ
NOP
(5)
WRITE
Qn + 3
tDC
READ
,
5687 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
BEn
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5687 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
15
,
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance
tCH2
(1)
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
,
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5687 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance
tCYC1
tCH1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
,
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5687 drw 16
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = V IH.
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
16
(1)
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1)
tCH2
t CYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHC
N
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
Timing Waveform of Counter Repeat
Dn + 4
WRITE WITH COUNTER
,
5687 drw 17
(2,6)
tCYC2
CLK
tSA tHA
An
ADDRESS
(3)
INTERNAL
ADDRESS
An+2
An+1
An
An+2
An
An+1
An+2
An+2
tSAD tHAD
ADS
tSW tHW
R/W
tSCN tHCN
CNTEN
REPEAT
(4)
tSRPT tHRPT
,
tSD tHD
DATAIN
D0
D3
D2
D1
tCD1
An
DATAOUT
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
An+1
ADVANCE
COUNTER
READ
An+1
An+2
An+2
,
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
5687 drw 18
NOTES:
1. CE 0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE 0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
17
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Waveform of Interrupt Timing
Advanced
Industrial and Commercial Temperature Ranges
(2)
CLKL
tSW
tHW
tSA
tHA
R/WL
ADDRESSL(3)
3FFFF
tSC
CEL
tHC
(1)
tINS
INTR
tINR
CLKR
tSC
tHC
CER(1)
R/WR
ADDRESSR(3)
tSW
tHW
tSA
tHA
3FFFF
NOTES:
1. CE0 = VIL and CE 1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III — Interrupt Flag
(1)
Left Port
CLKL
R/WL
CEL
5687 drw 19
Right Port
(3,4)
A17L-A0L
INTL
CLKR
(2)
R/WR
CE R
(2)
A17R-A0R(3,4)
INTR
Function
Ç
L
L
3FFFF
X
Ç
X
X
X
L
Set Right INTR Flag
Ç
X
X
X
X
Ç
X
L
3FFFF
H
Reset Right INTR Flag
Ç
X
X
X
L
Ç
L
L
3FFFE
X
Set Left INTL Flag
Ç
H
L
3FFFE
H
Ç
X
X
X
X
Reset Left INTL Flag
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE 1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A17X is a NC for IDT70T3799, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
18
5687 tbl 13
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
Both Ports Writing with Left Port Clock Leading
CLKL
tOFS
tSA
(4)
tHA
ADDRESSL
A3
A2
A1
A0
tCOLR
tCOLS
COLL
(3)
tOFS
CLKR
tSA
tHA
(4)
ADDRESSR
A0
A3
A2
A1
tCOLR
tCOLS
COLR
5687 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
Region 1 (ns)
(1)
Region 2 (ns)
5ns
0 - 2.8
2.81 - 4.6
6ns
0 - 3.8
3.81 - 5.6
7.5ns
0 - 5.3
5.31 - 7.1
NOTES:
1. Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
(2)
56876 tbl 14
Truth Table IV — Collision Detection Flag
Left Port
CLKL
R/WL
CEL
Ç
H
L
Ç
H
Ç
Ç
Right Port
(2)
CER(1)
A17R-A0R(2)
COLR
H
L
MATCH
H
Both ports reading. Not a valid collision.
No flag output on either port
Ç
L
L
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
H
Ç
H
L
MATCH
L
Right port reading, Left port writing.
Valid collision, flag output on Right port.
L
Ç
L
L
MATCH
L
Both ports writing. Valid collision. Flag
output on both ports.
COLL
CLKR
MATCH
H
Ç
L
MATCH
L
L
L
MATCH
L
L
MATCH
A17L-A0L
(1)
R/WR
Function
NOTES:
1. CE 0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
19
5687 tbl 15
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode
(1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
DATAOUT
Dn+1
(4)
NOTES:
1. CE1 = V IH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = V IH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
20
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Functional Description
The IDT70T3719/99M provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3719/99Ms for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table I. The left port clears the interrupt through access of
address location 3FFFE when CEL = VIL and R/WL = VIH. Likewise, the
right port interrupt flag (INT R ) is asserted when the left
port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 3FFFF (1FFFF
or 1FFFE for IDT70T3799M). The message (72 bits) at 3FFFE or 3FFFF
(1FFFF or 1FFFE for 70T3799M) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations
3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3799M) are not used
as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.
Collision Detection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no data
is corrupted, lost, or incorrectly output, so no collision flag is output on either
port. (b) One port writing, the other port reading - the end result of the write
will still be valid. However, the reading port might capture data that is in
a state of transition and hence the reading port’s collision flag is output. (c)
Both ports writing - there is a risk that the two ports will interfere with each
other, and the data stored in memory will not be a valid write from either
port (it may essentially be a random combination of the two). Therefore,
the collision flag is output on both ports. Please refer to Truth Table IV for
all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock edge
of the affected port following the collision, and remains low for one cycle.
Please refer to Collision Detection Timing table on Page 19. During that
next cycle, the internal arbitration is engaged in resetting the alert flag (this
avoids a specific requirement on the part of the user to reset the alert flag).
If two collisions occur on subsequent clock cycles, the second collision may
not generate the appropriate alert flag. A third collision will generate the
Advanced
Industrial and Commercial Temperature Ranges
alert flag as appropriate. In the event that a user initiates a burst access
on both ports with the same starting address on both ports and one or both
ports writing during each access (i.e., imposes a long string of collisions
on contiguous clock cycles), the alert flag will be asserted and cleared
every other cycle. Please refer to the Collision Detection timing waveform
on Page 19.
Collision detection on the IDT70T3719/99M represents a significant
advance in functionality over current sync multi-ports, which have no such
capability. In addition to this functionality the IDT70T3719/99M sustains
the key features of bandwidth and flexibility. The collision detection function
is very useful in the case of bursting data, or a string of accesses made to
sequential addresses, in that it indicates a problem within the burst, giving
the user the option of either repeating the burst or continuing to watch the
alert flag to see whether the number of collisions increases above an
acceptable threshold value. Offering this function on chip also allows users
to reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives the
user more flexibility in developing a solution.
Sleep Mode
The IDT70T3719/99M is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is asynchronous
and active high. During normal operation, the ZZ pin is pulled low. When
ZZ is pulled high, the port will enter sleep mode where it will meet lowest
possible power conditions. The sleep mode timing diagram shows the
modes of operation: Normal Operation, No Read/Write Allowed and Sleep
Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
6.42
21
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Depth and Width Expansion
Advanced
Industrial and Commercial Temperature Ranges
The IDT70T3719/99M can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 144-bits.
The IDT70T3719/99M features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
A18/A17(1)
IDT70T3719/99M
CE0
CE1
IDT70T3719/99M
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70T3719/99M
CE0
IDT70T3719/99M
CE1
CE1
CE0
CE0
Control Inputs
Control Inputs
Figure 4. Depth and Width Expansion with IDT70T3719/99M
5687 drw 23
NOTE:
1. A18 is for IDT70T3719, A17 is for IDT70T3799.
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
,
JTAG Functionality and Configuration
The IDT70T3719/99M is composed of two independent memory
arrays, and thus cannot be treated as a single JTAG device in the scan
.
chain. The two arrays (A and B) each have identical characteristics and
commands but must be treated as separate entities in JTAG operations.
Please refer to Figure 5.
JTAG signaling must be provided serially to each array and utilize the
information provided in the Identification Register Definitions, Scan
Register Sizes, and System Interface Parameter tables. Specifically,
commands for Array B must precede those for Array A in any JTAG
operations sent to the IDT70T3719/99M. Please reference Application
Note AN-411, "JTAG Testing of Multichip Modules" for specific instructions on performing JTAG testing on the IDT70T3719/99M. AN-411 is
available at www.idt.com.
IDT70T3719/99M
TDI
Array A
TDOA
TDIB
Array B
TCK
TMS
TRST
5687 drw 24
Figure 5. JTAG Configuration for IDT70T3719/99M
6.42
22
TDO
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5687 drw 25
tJRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics (1,2,3,4)
70T3719/99M
Symbol
Parameter
Min.
Max.
Units
ns
tJCYC
JTAG Clock Input Period
100
____
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
JTAG Clock Rise Time
____
(1)
ns
JTAG Clock Fall Time
____
(1)
3
ns
ns
tJR
tJF
3
tJRST
JTAG Reset
50
____
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
0
____
ns
15
____
ns
15
____
ns
tJDC
tJS
tJH
JTAG Data Output Hold
JTAG Setup
JTAG Hold
5687 tbl 16
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
23
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field Array B
Value
Instruction Field Array A
Array B
Revision Number (31:28)
0x0
Revision Number (63:60)
Value
Description
Array A
0x0
Reserved for Version number
IDT Device ID (27:12)(1)
0x330
IDT Device ID (59:44)(1)
0x330
Defines IDT Part number
IDT JEDEC ID (11:1)
0x33
IDT JEDEC ID (43:33)
0x33
Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0)
1
ID Register Indicator Bit (Bit 32)
1
Indicates the presence of an ID Register
5687 tbl 17
NOTE:
1. Device ID for IDT70T3719M is 0x330. Device ID for IDT70T3799M is 0x331.
Scan Register Sizes
Register Name
Instruction (IR)
Bit Size
Array A
Bit Size
Array B
Bit Size
70T3719M
4
4
8
Bypass (BYR)
1
1
2
Identification (IDR)
32
32
64
Note (3)
Note (3)
Note (3)
Boundary Scan (BSR)
5687 tbl 18
System Interface Parameters
Instruction
Code
Description
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
00000000
BYPASS
11111111
IDCODE
00100010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
01000100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers except INTx and COLx to a High-Z state.
HIGHZ
Places the bypass register (BYR) between TDI and TDO.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
00110011
SAMPLE/PRELOAD
00010001
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
01010101, 01110111,
10001000, 10011001,
10101010, 10111011,
11001100
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
PRIVATE
01100110,11101110,
11011101
For internal use only.
5687 tbl 19
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
24
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
Power
Speed
Package
A
A
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
BB
324-pin BGA (BBG-324)
166
133
Commercial Only
Commercial & Industrial
S
Standard Power
70T3719M
70T3799M
18Mbit (256K x 72) 2.5V Synchronous Dual-Port RAM
9Mbit (128K x 72) 2.5V Synchronous Dual-Port RAM
Speed in Megahertz
5687 drw 26
IDT Clock Solution for IDT70T3719/99M Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70T3719/99M
3.3/2.5
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
LVTTL
15pF
40%
166
75ps
5T2010
5T9010
5T905, 5T9050
5T907, 5T9070
5687 tbl 20
Datasheet Document History:
06/27/05:
Initial Advanced Datasheet
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
25
for Tech Support:
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