ATMEL AT91SAM9XE128 At91 arm thumb microcontroller Datasheet

Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
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– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for
AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,
AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024
Pages of 512 Bytes Respectively.
• 128-bit Wide Access
• Fast Read Time: 60 ns
• Page Programming Time: 4 ms, Including Page Auto-erase,
Full Erase Time: 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash
Security Bit
Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory
Interface
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device
and Double Port in 217-ball LFBGA Device
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
Bus Matrix
– Six 32-bit-layer Matrix
– Remap Command
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
AT91 ARM
Thumb
Microcontrollers
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6254AS–ATARM–14-Feb-08
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
• Clock Generator (CKGR)
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2
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply,
Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
– 20-bit Interval Timer Plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
One 4-channel 10-bit Analog to Digital Converter
Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Peripheral DMA Controller Channels (PDC)
Two-slot Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
One Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
One 2-wire UART
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
Two Two-wire Interfaces (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
– Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package
1. AT91SAM9XE128/256/512 Description
The AT91SAM9XE128/256/512 is based on the integration of an ARM926EJ-S processor with
fast ROM and RAM, 128, 256 or 512 Kbytes of Flash and a wide range of peripherals.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.
The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB
Host Controller. It also integrates several standard peripherals, like USART, SPI, TWI, Timer
Counters, Synchronous Serial Controller, ADC and a MultiMedia Card Interface.
The AT91SAM9XE128/256/512 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device
operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.
The AT91SAM9XE128/256/512 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of
interfacing with a wide range of memory devices.
The pinout and ball-out are fully compatible with the AT91SAM9260 with the exception that the
pin BMS is replaced by the pin ERASE.
3
6254AS–ATARM–14-Feb-08
2. AT91SAM9XE128/256/512 Block Diagram
The block diagram shows all the features for the 217-LFBGA package. Some functions are not
accessible in the 208-PQFP package and the unavailable pins are highlighted in “Multiplexing
on PIO Controller A” on page 39, “Multiplexing on PIO Controller B” on page 40, “Multiplexing on
PIO Controller C” on page 41. The USB Host Port B is also not available. Table 2-1 on page 4
defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.
Table 2-1.
4
Unavailable Signals in 208-pin PQFP Device
PIO
Peripheral A
Peripheral B
-
HDPB
-
-
HDMB
-
PA30
SCK2
RXD4
PA31
SCK0
TXD4
PB12
TWD1
ISI_D10
PB13
TWCK1
ISI_D11
PC2
AD2
PCK1
PC3
AD3
SPI1_NPCS3
PC12
IRQ0
NCS7
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
NRST
POR
VDDCORE
MCI
RSTC
SHDC
RTT
PDC
TWI0
TWI1
4GPREG
PIT
PMC
PDC
BOD
POR
OSC
RC
WDT
OSC
PLLB
PLLA
PDC
DBGU
AIC
System
Controller
SLAVE
VDDBU
SHDN
WKUP
OSCSEL
XIN32
XOUT32
XIN
XOUT
PLLRCA
DRXD
DTXD
PCK0-PCK1
FIQ
IRQ0-IRQ2
TST
Filter
M
CD
B
0M
CD
M
CD MC B3
A0 CD
B
M
C
M DA
CC 3
D
M A
CC
K
PIOC
PIOB
PIOA
PDC
USART0
USART1
USART2
USART3
USART4
APB
ER
AS
E
T
CT TWWD
RTS0- CK
C
SC S0- TS
R 3
RX K0- TS
S 3
T D0 CK
X
D0-RX 3
-T D5
X
DSD5
DCR0
D
R0
DT I0
R0
6254AS–ATARM–14-Feb-08
JT
AG
SE
L
NT
R
TD ST
TDI
TMO
TC S
RTK
CK
MMU
TC0
TC1
TC2
ROM
32 Kbytes
Bus Interface
PDC
SPI0
SPI1
Flash
128, 256
or 512
Kbytes
I
ICache
16 Kbytes
TC3
TC4
TC5
Fast SRAM
16 or 32
Kbytes
D
DCache
8 Kbytes
ARM926EJ-S Processor
In-Circuit Emulator
JTAG Selection and Boundary Scan
SSC
PDC
ET
E XC
T
K
ECXE -E
R
N
ERRS -E XC
T
ERXE -EC XE K
R O
ET X0 -E L R
- R
M X0 ER XD
D - X
M C ETX 3 V
D
3
F1 IO
00
DMA
4-channel
10-bit ADC
PDC
Peripheral
Bridge
6-layer Matrix
FIFO
SPI0_, SPI1_
USB
Device
DPRAM
DMA
DMA
ECC
Controller
Static
Memory
Controller
SDRAM
Controller
CompactFlash
NAND Flash
EBI
USB
OHCI
Transc.
HD
P
HD B
M
B
Image
Sensor
Interface
Transceiver
24-channel
Peripheral
DMA
FIFO
10/100 Ethernet
MAC
Transc.
IS
I
_M
IS CK
I_
IS PC
I
_ K
I D
S
I_ O-I
V
IS SY SI_
I_ N D7
H
SY C
NC
HD
HD PA
M
A
NP
NPCS
NPCS3
N CS2
P
C 1
SP S0
MC
OK
TC
M SI
IS
L
O
TI K0
O -T
T A C
I
O 0-T LK
TC B0 IOA2
L -T 2
TI K3 IOB
O TI A3 TC 2
O -T LK
B
5
I
3
-T OA
IO 5
B5
TK
TF
TD
RD
RF
RK
AD
0A
AD D3
TR
IG
AD
VR
EF
VD
DA
NA
G
ND
AN
A
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
D16-D31
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
NCS2, NCS6, NCS7
NCS3/NANDCS
Figure 2-1.
D
D
DDM
P
MASTER
AT91SAM9XE128/256/512 Preliminary
AT91SAM9XE128/256/512 Block Diagram
5
3. Signals Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Name
Signal Description List
Function
Type
Active
Level
Comments
Power Supplies
VDDIOM
EBI I/O Lines Power Supply
Power
1.65V to 1.95V or 3.0V to 3.6V
VDDIOP0
Peripherals I/O Lines Power Supply
Power
3.0V to 3.6V
VDDIOP1
Peripherals I/O Lines Power Supply
Power
1.65V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
1.65V to 1.95V
VDDANA
Analog Power Supply
Power
3.0V to 3.6V
VDDPLL
PLL Power Supply
Power
1.65V to 1.95V
VDDCORE
Core Chip and Embedded Memories
Power Supply
Power
1.65V to 1.95V
GND
Ground
Ground
GNDPLL
PLL Ground
Ground
GNDANA
Analog Ground
Ground
GNDBU
Backup Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
OSCSEL
Slow Clock Oscillator Selection
Input
PLLRCA
PLL A Filter
Input
PCK0 - PCK1
Programmable Clock Output
Output
Input
Output
Accepts between 0V and
VDDBU.
Output
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP
Wake-Up Input
Driven at 0V only. Do not tie
over VDDBU.
Output
Accepts between 0V and
VDDBU.
Input
ICE and JTAG
NTRST
Test Reset Signal
Input
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor. Accepts
between 0V and VDDBU.
RTCK
Return Test Clock
6
Low
Pull-up resistor
Output
Output
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Input
High
Pull-down resistor
I/O
Low
Pull-up resistor
Comments
Flash Memory
ERASE
Flash and NVM Configuration Bits
Erase Command
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
Pull-down resistor. Accepts
between 0V and VDDBU.
Input
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ2
External Interrupt Inputs
Input
FIQ
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB30
Parallel IO Controller B
I/O
Pulled-up input at reset
PC0 - PC31
Parallel IO Controller C
I/O
Pulled-up input at reset
External Bus Interface - EBI
D0 - D31
Data Bus
A0 - A25
Address Bus
I/O
Pulled-up input at reset
NWAIT
External Wait Signal
NCS0 - NCS7
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signal
Output
Low
NRD
Read Signal
Output
Low
NUB
Upper Byte Select
Output
Low
NLB
Lower Byte Select
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signal
Output
Low
Output
Input
0 at reset
Low
Static Memory Controller - SMC
CompactFlash Support
CFCE1 - CFCE2
CompactFlash Chip Enable
Output
Low
CFOE
CompactFlash Output Enable
Output
Low
CFWE
CompactFlash Write Enable
Output
Low
CFIOR
CompactFlash IO Read
Output
Low
CFIOW
CompactFlash IO Write
Output
Low
CFRNW
CompactFlash Read Not Write
Output
CFCS0 - CFCS1
CompactFlash Chip Select Lines
Output
Low
7
6254AS–ATARM–14-Feb-08
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
NAND Flash Support
NANDCS
NAND Flash Chip Select
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
SDRAM Controller
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
High
SDCS
SDRAM Controller Chip Select
Output
Low
BA0 - BA1
Bank Select
Output
SDWE
SDRAM Write Enable
Output
Low
RAS - CAS
Row and Column Signal
Output
Low
SDA10
SDRAM Address 10 Line
Output
Multimedia Card Interface MCI
MCCK
Multimedia Card Clock
Output
MCCDA
Multimedia Card Slot A Command
I/O
MCDA0 - MCDA3
Multimedia Card Slot A Data
I/O
MCCDB
Multimedia Card Slot B Command
I/O
MCDB0 - MCDB3
Multimedia Card Slot B Data
I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
DTR0
USART0 Data Terminal Ready
DSR0
USART0 Data Set Ready
Input
DCD0
USART0 Data Carrier Detect
Input
RI0
USART0 Ring Indicator
Input
Output
Input
Output
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
RD
SSC Receive Data
Input
TK
SSC Transmit Clock
I/O
RK
SSC Receive Clock
I/O
TF
SSC Transmit Frame Sync
I/O
RF
SSC Receive Frame Sync
I/O
8
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Timer/Counter - TCx
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Serial Peripheral Interface - SPIx_
SPIx_MISO
Master In Slave Out
I/O
SPIx_MOSI
Master Out Slave In
I/O
SPIx_SPCK
SPI Serial Clock
I/O
SPIx_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPIx_NPCS1-SPIx_NPCS3
SPI Peripheral Chip Select
Output
Low
Two-Wire Interface
TWDx
Two-wire Serial Data
I/O
TWCKx
Two-wire Serial Clock
I/O
USB Host Port
HDPA
USB Host Port A Data +
Analog
HDMA
USB Host Port A Data -
Analog
HDPB
USB Host Port B Data +
Analog
HDMB
USB Host Port B Data +
Analog
USB Device Port
DDM
USB Device Port Data -
Analog
DDP
USB Device Port Data +
Analog
Ethernet 10/100
ETXCK
Transmit Clock or Reference Clock
Input
MII only, REFCK in RMII
ERXCK
Receive Clock
Input
MII only
ETXEN
Transmit Enable
Output
ETX0-ETX3
Transmit Data
Output
ETX0-ETX1 only in RMII
ETXER
Transmit Coding Error
Output
MII only
ERXDV
Receive Data Valid
Input
RXDV in MII, CRSDV in RMII
ERX0-ERX3
Receive Data
Input
ERX0-ERX1 only in RMII
ERXER
Receive Error
Input
ECRS
Carrier Sense and Data Valid
Input
MII only
ECOL
Collision Detect
Input
MII only
EMDC
Management Data Clock
EMDIO
Management Data Input/Output
EF100
Force 100Mbit/sec.
Output
I/O
Output
High
9
6254AS–ATARM–14-Feb-08
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Image Sensor Interface
ISI_D0-ISI_D11
Image Sensor Data
Input
ISI_MCK
Image sensor Reference clock
output
ISI_HSYNC
Image Sensor Horizontal Synchro
input
ISI_VSYNC
Image Sensor Vertical Synchro
input
ISI_PCK
Image Sensor Data clock
input
Analog to Digital Converter
AD0-AD3
Analog Inputs
Analog
ADVREF
Analog Positive Reference
Analog
ADTRG
ADC Trigger
Digital pulled-up inputs at
reset
Input
Fast Flash Programming Interface
PGMEN[2:0]
Programming Enabling
Input
PGMNCMD
Programming Command
Input
Low
PGMRDY
Programming Ready
Output
High
PGMNOE
Programming Read
Input
Low
PGMNVALID
Data Direction
Output
Low
PGMM[3:0]
Programming Mode
Input
PGMD[15:0]
Programming Data
I/O
10
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
4. Package and Pinout
The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch) or
in a 217-ball LFBGA Green package (0.8 mm ball pitch).
4.1
208-pin PQFP Package Outline
Figure 4-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet.
Figure 4-1.
208-pin PQFP Package Outline (Top View)
156
105
157
104
208
53
1
52
11
6254AS–ATARM–14-Feb-08
4.2
208-pin PQFP Package Pinout
Table 4-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
12
Pinout for 208-pin PQFP Package
Signal Name
PA24
PA25
PA26
PA27
VDDIOP0
GND
PA28
PA29
PB0
PB1
PB2
PB3
VDDIOP0
GND
PB4
PB5
PB6
PB7
PB8
PB9
PB14
PB15
PB16
VDDIOP0
GND
PB17
PB18
PB19
TDO
TDI
TMS
VDDIOP0
GND
TCK
NTRST
NRST
RTCK
VDDCORE
GND
ERASE
OSCSEL
TST
JTAGSEL
GNDBU
XOUT32
XIN32
VDDBU
WKUP
SHDN
HDMA
HDPA
VDDIOP0
Pin
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Signal Name
GND
DDM
DDP
PC13
PC11
PC10
PC14
PC9
PC8
PC4
PC6
PC7
VDDIOM
GND
PC5
NCS0
CFOE/NRD
CFWE/NWE/NWR0
NANDOE
NANDWE
A22
A21
A20
A19
VDDCORE
GND
A18
BA1/A17
BA0/A16
A15
A14
A13
A12
A11
A10
A9
A8
VDDIOM
GND
A7
A6
A5
A4
A3
A2
NWR2/NBS2/A1
NBS0/A0
SDA10
CFIOW/NBS3/NWR3
CFIOR/NBS1/NWR1
SDCS/NCS1
CAS
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Signal Name
RAS
D0
D1
D2
D3
D4
D5
D6
GND
VDDIOM
SDCK
SDWE
SDCKE
D7
D8
D9
D10
D11
D12
D13
D14
D15
PC15
PC16
PC17
PC18
PC19
VDDIOM
GND
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
GND
VDDCORE
VDDPLL
XIN
XOUT
GNDPLL
NC
GNDPLL
PLLRCA
VDDPLL
GNDANA
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal Name
ADVREF
PC0
PC1
VDDANA
PB10
PB11
PB20
PB21
PB22
PB23
PB24
PB25
VDDIOP1
GND
PB26
PB27
GND
VDDCORE
PB28
PB29
PB30
PB31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VDDIOP0
GND
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
VDDIOP0
GND
PA18
PA19
VDDCORE
GND
PA20
PA21
PA22
PA23
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
4.3
217-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet.
Figure 4-2.
217-ball LFBGA Package Outline (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U
Ball A1
13
6254AS–ATARM–14-Feb-08
4.4
217-ball LFBGA Package Pinout
Table 4-2.
Pinout for 217-ball LFBGA Package
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
CFIOW/NBS3/NWR3
NBS0/A0
NWR2/NBS2/A1
A6
A8
A11
A13
BA0/A16
A18
A21
A22
CFWE/NWE/NWR0
CFOE/NRD
NCS0
PC5
PC6
PC4
SDCK
CFIOR/NBS1/NWR1
SDCS/NCS1
SDA10
A3
A7
A12
A15
A20
NANDWE
PC7
PC10
PC13
PC11
PC14
PC8
WKUP
D8
D1
CAS
A2
A4
A9
A14
BA1/A17
A19
NANDOE
PC9
PC12
DDP
HDMB
NC
VDDIOP0
SHDN
D9
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
E1
E2
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F14
F15
F16
F17
G1
G2
G3
G4
G14
G15
G16
G17
H1
H2
H3
H4
H8
H9
H10
H14
H15
H16
H17
J1
J2
J3
J4
A5
GND
A10
GND
VDDCORE
GND
VDDIOM
GND
DDM
HDPB
NC
VDDBU
XIN32
D10
D5
D3
D4
HDPA
HDMA
GNDBU
XOUT32
D13
SDWE
D6
GND
OSCSEL
ERASE
JTAGSEL
TST
PC15
D7
SDCKE
VDDIOM
GND
NRST
RTCK
TMS
PC18
D14
D12
D11
GND
GND
GND
VDDCORE
TCK
NTRST
PB18
PC19
PC17
VDDIOM
PC16
J14
J15
J16
J17
K1
K2
K3
K4
K8
K9
K10
K14
K15
K16
K17
L1
L2
L3
L4
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
N2
N3
N4
N14
N15
N16
N17
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
TDO
PB19
TDI
PB16
PC24
PC20
D15
PC21
GND
GND
GND
PB4
PB17
GND
PB15
GND
PC26
PC25
VDDIOP0
PA28
PB9
PB8
PB14
VDDCORE
PC31
GND
PC22
PB1
PB2
PB3
PB7
XIN
VDDPLL
PC23
PC27
PA31
PA30
PB0
PB6
XOUT
VDDPLL
PC30
PC28
PB11
PB13
PB24
VDDIOP1
PB30
PB31
PA1
PA3
PA7
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
PB5
NC
GNDANA
PC29
VDDANA
PB12
PB23
GND
PB26
PB28
PA0
PA4
PA5
PA10
PA21
PA23
PA24
PA29
PLLRCA
GNDPLL
PC0
PC1
PB10
PB22
GND
PB29
PA2
PA6
PA8
PA11
VDDCORE
PA20
GND
PA22
PA27
GNDPLL
ADVREF
PC2
PC3
PB20
PB21
PB25
PB27
PA12
PA13
PA14
PA15
PA19
PA17
PA16
PA18
VDDIOP0
14
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
Table 4-2.
Pinout for 217-ball LFBGA Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
D2
D3
D4
D2
RAS
D0
J8
J9
J10
GND
GND
GND
P14
P15
P16
PA9
PA26
PA25
Pin
Signal Name
5. Power Considerations
5.1
Power Supplies
The AT91SAM9XE128/256/512 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and
1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is
selectable by software.
• VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
3.0V and 3.6V, 3V or 3.3V nominal.
• VDDIOP1 pin: Powers the Peripherals I/O lines involving the Image Sensor Interface; voltage
ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDPLL pins: Power the PLL cells and the main oscillator; voltage ranges from 1.65V and
1.95V, 1.8V nominal.
• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V,
3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and
their associated I/O lines in the multiplexing tables. These supplies enable the user to power the
device differently for interfacing with memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power
supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These
ground pins are respectively GNDBU, GNDPLL and GNDANA.
5.2
Power Consumption
The AT91SAM9XE128/256/512 consumes about 500 µA of static current on VDDCORE at
25°C. This static current rises up to 5 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 20 µA in worst case conditions.
For dynamic power consumption, the AT91SAM9XE128/256/512 consumes a maximum of 130
mA on VDDCORE at maximum conditions (1.8V, 25°C, processor running full-performance
algorithm out of high speed memories).
5.3
Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its
maximum speed either out of 1.8V or 3.3V external memories.
15
6254AS–ATARM–14-Feb-08
The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power
supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data
signals) do not exceed 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either
1.8V or 3.3V. The user must program the EBI voltage range before getting the device out of its
Slow Clock Mode.
6. I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied
to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it
can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All the JTAG signals are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is a bi-directional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value
can be found in the table “DC Characteristics” in the section “AT91SAM9XE Electrical Characteristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
6.4
ERASE Pin
The pin ERASE is used to re-initialize the Flash content and the NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operations.
16
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
This pin is debounced on the RC oscillator or 32,768 Hz to improve the glitch tolerance. Minimum debouncing time is 200 ms.
6.5
PIO Controllers
All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to “DC Characteristics” in the section
“AT91SAM9XE128/256/512 Electrical Characteristics”. Programming of this pull-up resistor is
performed independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
6.6
I/O Line Drive Levels
The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC3 are high-drive current capable.
Each of these I/O lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines.
Refer to the “DC Characteristics” section of the product datasheet.
6.7
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6.8
Slow Clock Selection
The AT91SAM9XE128/256/512 slow clock can be generated either by an external 32,768 Hz
crystal or the on-chip RC oscillator.
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 200 µs for the internal RC oscillator. The pin
OSCSEL must be tied either to GNDBU or VDDBU for correct operation of the device.
Refer to the Slow Clock Selection table in the Electrical Characteristics section of the product
datasheet for the states of the OSCSEL signal.
17
6254AS–ATARM–14-Feb-08
7. Processor and Architecture
7.1
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 8 KB Data Cache, 16 KB Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2
Bus Matrix
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
18
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal ROM boot, one for internal flash boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal ROM or internal Flash
– Selection is made by General purpose NVM bit sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
(ROM or Flash)
– Allows Handling of Dynamic Exception Vectors
7.2.1
Matrix Masters
The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can
perform an access concurrently with others, depending on whether the slave it accesses is
available.
Each Master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
7.2.2
List of Bus Matrix Masters
Master 0
ARM926™ Instruction
Master 1
ARM926 Data
Master 2
Peripheral DMA Controller
Master 3
USB Host Controller
Master 4
Image Sensor Controller
Master 5
Ethernet MAC
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal Flash
Slave 1
Internal SRAM
Internal ROM
Slave 2
USB Host User Interface
Slave 3
External Bus Interface
Slave 4
Reserved
Slave 5
Internal Peripherals
19
6254AS–ATARM–14-Feb-08
7.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
Table 7-3.
AT91SAM9XE128/256/512 Masters to Slaves Access
Master
Slave
0 and 1
2
3
4
5
ARM926 Instruction
and Data
Periphera DMA
Controller
ISI Controller
Ethernet MAC
USB Host
Controller
0
Internal Flash
X
–
–
X
1
Internal SRAM
X
X
X
X
X
Internal ROM
X
X
–
–
–
UHP User Interface
X
–
–
–
–
3
External Bus Interface
X
X
X
X
X
4
Reserved
–
–
–
–
–
Internal Peripherals
X
X
–
–
–
2
7.3
Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-four channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the Two Wire Interface
– One for Multimedia Card Interface
– One for Analog To Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
– TWI0 Transmit Channel
– TWI1 Transmit Channel
– DBGU Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
20
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC Transmit Channel
– TWI0 Receive Channel
– TWI1 Receive Channel
– DBGU Receive Channel
– USART4 Receive Channel
– USART3 Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– ADC Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC Receive Channel
– MCI Transmit/Receive Channel
7.4
Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
21
6254AS–ATARM–14-Feb-08
8. Memories
Figure 8-1.
AT91SAM9XE128/256/512 Memory Mapping
Address Memory Space
Internal Memory Mapping
0x0000 0000
Notes : (1) Can be ROM or Flash
depending on GPNVM[3]
0x0000 0000
Boot Memory (1)
Internal Memories
256M Bytes
0x10 0000
ROM
0x0FFF FFFF
EBI
Chip Select 0
Reserved
256M Bytes
0x20 0000
Flash
128, 256 or 512K Bytes
0x28 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
32K Bytes
0x10 8000
0x1000 0000
Reserved
EBI
Chip Select 1/
SDRAMC
256M Bytes
0x30 0000
SRAM
32K Bytes
0x30 8000
Reserved
0x3000 0000
0x50 0000
EBI
Chip Select 2
UHP
256M Bytes
0x50 4000
EBI
Chip Select 3/
NANDFlash
256M Bytes
0x0FFF FFFF
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
EBI
Chip Select 5/
Compact Flash
Slot 1
256M Bytes
16K Bytes
0x3FFF FFFF
0x4000 0000
Reserved
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
Peripheral Mapping
0xF000 0000
System Controller Mapping
Reserved
0x7000 0000
0xFFFA 0000
EBI
Chip Select 6
256M Bytes
0x7FFF FFFF
0x8000 0000
TCO, TC1, TC2
16K Bytes
UDP
16K Bytes
MCI
16K Bytes
TWI0
16K Bytes
0xFFFF C000
Reserved
0xFFFA 4000
0xFFFF E800
0xFFFA 8000
EBI
Chip Select 7
256M Bytes
0xFFFA C000
0x8FFF FFFF
0x9000 0000
ECC
512 Bytes
SDRAMC
512 Bytes
SMC
512 Bytes
0xFFFF EA00
0xFFFF EC00
0xFFFB 0000
USART0
16K Bytes
0xFFFB 4000
0xFFFF EE00
USART1
16K Bytes
0xFFFB 8000
USART2
16K Bytes
SSC
16K Bytes
ISI
16K Bytes
EMAC
16K Bytes
MATRIX
0xFFFF EF10
0xFFFF F000
0xFFFB C000
512 Bytes
CCFG
512 Bytes
AIC
0xFFFF F200
0xFFFC 0000
0xFFFC 4000
1,518M Bytes
SPI0
16K Bytes
0xFFFC C000
SPI1
16K Bytes
USART3
16K Bytes
USART4
TWI1
16K Bytes
0xFFFF FC00
16K Bytes
0xFFFF FD00
TC3, TC4, TC5
16K Bytes
0xFFFE 0000
ADC
16K Bytes
22
512 bytes
EEFC
512 bytes
PMC
256 Bytes
0xFFFF FD20
RSTC
16 Bytes
SHDC
16 Bytes
RTTC
0xFFFF FD30
16 Bytes
PITC
16 Bytes
WDTC
16 Bytes
GPBR
16 Bytes
0xFFFF FD40
0xFFFE 4000
0xFFFF FD50
0xFFFF FD60
Reserved
0xFFFF FFFF
PIOC
0xFFFF FD10
0xFFFD C000
256M Bytes
512 bytes
0xFFFF FA00
0xFFFD 8000
Internal Peripherals
512 Bytes
PIOB
0xFFFD 4000
0xF000 0000
PIOA
0xFFFF F800
0xFFFD 0000
0xEFFF FFFF
512 Bytes
0xFFFF F600
0xFFFC 8000
Undefined
(Abort)
DBGU
0xFFFF F400
0xFFFF C000
SYSC
16K Bytes
0xFFFF FFFF
Reserved
0xFFFF FFFF
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap, refer to Table 8-3, “Internal Memory Mapping,” on page 27 for details.
A complete memory map is presented in Figure 8-1 on page 22.
8.1
8.1.1
Embedded Memories
AT91SAM9XE128
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 16 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 128 KB Embedded Flash
8.1.2
AT91SAM9XE256
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 32 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 256 KB Embedded Flash
8.1.3
AT91SAM9XE512
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 32 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 512 KB Embedded Flash
8.1.4
ROM Topology
The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs.
Each of these two programs is stored at 16 KB Boundary and the program executed at address
23
6254AS–ATARM–14-Feb-08
zero depends on the combination of the TST pin and PA0 to PA2 pins. Figure 8-2 shows the contents of the ROM and the program available at address zero.
Figure 8-2.
ROM Boot Memory Map
0x0000 0000
0x0000 0000
0x0000 0000
SAM-BA
Program
SAM-BA
Program
FFPI
Program
FFPI
Program
0x0000 7FFF
0x0000 3FFF
ROM
8.1.4.1
0x0000 3FFF
TST=1
PA0=1
PA1=1
PA2=0
TST=0
Fast Flash Programming Interface
The Fast Flash Programming Interface programs the device through a serial JTAG interface or a
multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard
industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.
Table 8-1.
8.1.4.2
Signal Description
Signal Name
PIO
Type
Active Level
Comments
PGMEN0
PA0
Input
High
Must be connected to VDDIO
PGMEN1
PA1
Input
High
Must be connected to VDDIO
PGMEN2
PA2
Input
Low
Must be connected to GND
PGMNCMD
PA4
Input
Low
Pulled-up input at reset
PGMRDY
PA5
Output
High
Pulled-up input at reset
PGMNOE
PA6
Input
Low
Pulled-up input at reset
PGMNVALID
PA7
Output
Low
Pulled-up input at reset
PGMM[3:0]
PA8..PA10
Input
Pulled-up input at reset
PGMD[15:0]
PA12..PA27
Input/Output
Pulled-up input at reset
SAM-BA® Boot Assistant
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in
situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication through the DBGU or through the
USB Device Port.
24
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
• Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via
software auto-detection.
• Communication through the USB Device Port is depends on crystal selected:
– limited to an 18,432 Hz crystal if the internal RC oscillator is selected
– supports a wide range of crystals from 3 to 20 MHz if the 32,768 Hz crystal is
selected
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
8.1.5
Embedded Flash
The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes
directly connected to the 32-bit internal bus. Each page contains 128 words.
The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is
write-only as 128 32-bit words, and accessible all along the 1 MB address space, so that each
word can be written at its final address.
The Flash benefits from the integration of a power reset cell and from a brownout detector to
prevent code corruption during power supply changes, even in the worst conditions.
8.1.5.1
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked.
The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configurable through its User Interface on the APB bus. It ensures the interface of the Flash block with
the 32-bit internal bus. Its 128-bit wide memory interface increases performance, four 32-bit data
are read during each access, this multiply the throughput by 4 in case of consecutive data.
It also manages the programming, erasing, locking and unlocking sequences of the Flash using
a full set of commands. One of the commands returns the embedded Flash descriptor definition
that informs the system about the Flash organization, thus making the software generic programming of the access parameters of the Flash (number of wait states, timings, etc.)
8.1.5.2
Lock Regions
The memory plane of 128, 256 or 512 Kbytes is organized in 8, 16 or 32 locked regions of 32
pages each. Each lock region can be locked independently, so that the software protects the
first memory plane against erroneous programming:
If a locked-regions erase or program command occurs, the command is aborted and the EEFC
could trigger an interrupt.
The Lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
25
6254AS–ATARM–14-Feb-08
Figure 8-3.
Flash First Memory Plane Mapping
0x0020 0000
Locked Region 0
Page 0
Locked Regions Area
128, 256 or 512 Kbytes
256, 512 or
1024 Pages
Page 31
Locked Region 7, 15 or 31
0x0021 FFFF
or 0x0023 FFFF
or 0x0027 FFFF
8.1.5.3
512 bytes
16 KBytes
32 bits wide
GPNVM Bits
The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User
Interface.
Table 8-2.
GPNVMBit[#]
8.1.5.4
General-purpose Non volatile Memory Bits
Function
0
Security Bit
1
Brownout Detector Enable
2
Brownout Detector Reset Enable
3
Boot Mode Select (BMS)
Security Bit
The AT91SAM9XE128/256/512 features a security bit, based on a specific GPNVM bit, GPNVMBit[0]. When the security is enabled, access to the Flash, either through the ICE interface or
through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of
the code programmed in the Flash.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full
Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are
permitted.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation.
26
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
8.1.5.5
Non-volatile Brownout Detector Control
Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a
power loss, the brownout detector operations remain in their state.
• GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the
BOD, clearing it disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables
the brownout detector by default.
• GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting
GPNVMBit[2] enables the brownout reset when a brownout is detected, clearing
GPNVMBit[2] disables the brownout reset. Asserting ERASE disables the brownout reset by
default.
8.1.6
Boot Strategies
Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the GPNVMBit[3] state at reset.
Table 8-3.
Internal Memory Mapping
REMAP = 0
REMAP = 1
Address
0x0000 0000
GPNVMBit[3] clear
GPNVMBit[3] set
ROM
Flash
SRAM
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. Refer to the section “AT91SAM9XE Bus
Matrix” in the product datasheet for more details.
When REMAP = 0, a non volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to
lay out to 0x0, at his convenience, the ROM or the Flash. Refer to the section “Enhanced
Embedded Flash Controller (EEFC)” in the product datasheet for more details.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 22.
The AT91SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3]
at reset. The internal memory area mapped between address 0x0 and 0x0FFF FFFF is reserved
for this purpose.
If GPNVMBit[3] is set, the boot memory is the internal Flash memory
If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a
Flash erase, the boot memory is the internal ROM.
8.1.6.1
GPNVMBit[3] = 0, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device Port
27
6254AS–ATARM–14-Feb-08
8.1.6.2
GPNVMBit[3] = 1, Boot on Internal Flash
• Boot on slow clock (On-chip RC or 32,768 Hz)
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:
1. Program the PMC (main oscillator enable or bypass mode)
2. Program and start the PLL
3. Switch the main clock to the new value.
8.2
External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256 MB memory area assigned.
Refer to the memory map in Figure 8-1 on page 22.
8.2.1
External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– ECC Controller
• Additional logic for NANDFlash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64 MB linear)
• Up to 8 chip selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
8.2.2
Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
28
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
8.2.3
SDRAM Controller
• Supported devices:
– Standard and Low Power SDRAM (Mobile SDRAM)
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, power down and deep power down modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
8.2.4
Error Corrected Code Controller
• Hardware error corrected code generation
– Detection and correction by software
• Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path
• Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes
specified by software
• Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data
path
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes
with 8-bit data path
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes
with 8-bit data path
29
6254AS–ATARM–14-Feb-08
9. System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a
set of registers for the chip configuration. The chip configuration registers configure the EBI chip
select assignment and voltage range for external memories.
The System Controller’s peripherals are all mapped within the highest 16 KB of address space,
between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All
the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB.
Figure 9-1 on page 31 shows the System Controller block diagram.
Figure 8-1 on page 22 shows the mapping of the User Interfaces of the System Controller
peripherals.
30
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
9.1
System Controller Block Diagram
Figure 9-1.
AT91SAM9XE128/256/512 System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq2
fiq
periph_irq[2..24]
efc2_irq
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ntrst
PCK
debug
MCK
periph_nreset
dbgu_rxd
Debug
Unit
MCK
debug
periph_nreset
Periodic
Interval
Timer
pit_irq
Watchdog
Timer
wdt_irq
gpnvm[2]
POR
dbgu_txd
jtag_nreset
MCK
periph_nreset
Reset
Controller
periph_nreset
proc_nreset
backup_nreset
security_bit(gpnvm0)
flash_poe
flash_poe
flash_wrdis
VDDBU Powered
SLCK
SLCK
backup_nreset
Real-Time
Timer
rtt_irq
SLCK
XIN32
XOUT32
gpnvm[1..3]
backup_nreset
periph_clk[20]
Shutdown
Controller
periph_nreset
rtt0_alarm
USB Host
Port
periph_irq[20]
SLOW
CLOCK
OSC
4 General-Purpose
Backup Registers
SLCK
XIN
cal
UHPCK
WKUP
OSCSEL
Embedded
Flash
rtt_alarm
SHDN
RC
OSC
Bus Matrix
rstc_irq
NRST
VDDBU
POR
Boundary Scan
TAP Controller
gpnvm[3]
bod_rst_en
BOD
por_ntrst
jtag_nreset
dbgu_irq
wdt_fault
WDRPROC
flash_wrdis
VDDBU
ARM926EJ-S
proc_nreset
cal
gpnvm[1]
VDDCORE
por_ntrst
int
SLCK
debug
idle
proc_nreset
VDDCORE
nirq
nfiq
Advanced
Interrupt
Controller
UDPCK
int
MAIN
OSC
MAINCK
XOUT
PLLRCA
PLLA
PLLACK
PLLB
Power
Management
Controller
periph_clk[2..27]
pck[0-1]
periph_clk[10]
PCK
UDPCK
periph_nreset
USB
Device
Port
periph_irq[10]
UHPCK
MCK
PLLBCK
pmc_irq
periph_nreset
idle
periph_clk[6..24]
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
PA0-PA31
PB0-PB31
PC0-PC31
PIO
Controllers
periph_irq[2..4]
irq0-irq2
fiq
dbgu_txd
Embedded
Peripherals
periph_irq[6..24]
in
out
enable
31
6254AS–ATARM–14-Feb-08
9.2
Reset Controller
• Based on two Power-on reset cells
– One on VDDBU and one on VDDCORE
• Status of the last reset
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
reset, user reset or watchdog reset
• Controls the internal resets and the NRST pin output
– Allows shaping a reset signal for the external devices
9.3
Brownout Detector and Power-on Reset
The AT91SAM9XE128/256/512 embeds one brownout detection circuit and power-on reset
cells. The power-on reset are supplied with and monitor VDDCORE and VDDBU.
Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption
during power-up or power-down sequences or if brownouts occur on the VDDCORE power
supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low
during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.
The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed
trigger level. It secures system operations in the most difficult environments and prevents code
corruption in case of brownout on the VDDCORE.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger
level (Vbot-), the brownout output is immediately activated. For more details on Vbot, see the
table “Brownout Detector Characteristics” in the section “AT91SAM9XE128/256/512 Electrical
Characteristics” in the full datasheet.
When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + Vhyst), the reset
is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below
the threshold voltage for longer than about 1µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV typical, to ensure spike free
brownout detection. The typical value of the brownout detector threshold is 1.55V with an accuracy of ± 2% and is factory calibrated.
The brownout detector is low-power, as it consumes less than 12 µA static current. However, it
can be deactivated to save its static current. In this case, it consumes less than 1 µA. The deactivation is configured through the GPNVMBit[1] of the Flash.
Additional information can be found in the “Electrical Characteristics” section of the product
datasheet.
9.4
Shutdown Controller
• Shutdown and Wake-Up logic
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
32
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
9.5
Clock Generator
• Embeds a low power 32,768 Hz slow clock oscillator and a low-power RC oscillator
selectable with OSCSEL signal
– Provides the permanent slow clock SLCK to the system
• Embeds the main oscillator
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
• Embeds 2 PLLs
– PLL A outputs 80 to 240 MHz clock
– PLL B outputs 70 MHz to 130 MHz clock
– Both integrate an input divider to increase output accuracy
– PLLB embeds its own filter
Figure 9-2.
Clock Generator Block Diagram
Clock Generator
OSC_SEL
On Chip
RC OSC
XIN32
Slow Clock
SLCK
Slow Clock
Oscillator
XOUT32
XIN
Main
Oscillator
Main Clock
MAINCK
PLL and
Divider A
PLLA Clock
PLLACK
PLL and
Divider B
PLLB Clock
PLLBCK
XOUT
PLLRCA
Status
Control
Power
Management
Controller
9.6
Power Management Controller
• Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– independent peripheral clocks, typically at the frequency of MCK
– 2 programmable clock outputs: PCK0, PCK1
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
33
6254AS–ATARM–14-Feb-08
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
Figure 9-3.
AT91SAM9XE128/256/512 Power Management Controller Block Diagram
Processor
Clock
Controller
int
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
PCK
Idle Mode
Divider
/1,/2,/4
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
PLLBCK
9.7
ON/OFF
Prescaler
/1,/2,/4,...,/64
USB Clock Controller
ON/OFF
Divider
/1,/2,/4
pck[..]
UDPCK
UHPCK
Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real Time OS or Linux®/WindowsCE® compliant tick generator
9.8
Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.9
Real-time Timer
• Real-time Timer with 32-bit free-running back-up counter
• Integrates a 16-bit programmable prescaler running on slow clock
• Alarm Register capable to generate a wake-up of the system through the Shutdown
Controller
9.10
General-purpose Back-up Registers
• Four 32-bit backup general-purpose registers
34
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
9.11
Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• Three External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect modeIs are
enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.12
Debug Unit
• Composed of two functions
– Two-pin UART
– Debug Communication Channel (DCC) support
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
35
6254AS–ATARM–14-Feb-08
9.13
Chip Identification
• Chip ID:
– 0x3299A3A0 for the SAM9XE512
– 0x329A93A0 for the SAM9XE256
– 0x329973A0 for the SAM9XE128
• JTAG ID: 05B1_C03F
• ARM926 TAP ID: 0x0792603F
36
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
10. Peripherals
10.1
User Interface
The Peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of
address space. A complete memory map is presented in Figure 8-1 on page 22.
10.2
Peripheral Identifier
The AT91SAM9XE128/256/512 embeds a wide range of peripherals. Table 10-1 defines the
Peripheral Identifiers of the AT91SAM9XE128/256/512. A peripheral identifier is required for the
control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the
peripheral clock with the Power Management Controller.
Table 10-1.
Note:
AT91SAM9XE128/256/512 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A
3
PIOB
Parallel I/O Controller B
4
PIOC
Parallel I/O Controller C
5
ADC
Analog-to-digital Converter
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
MCI
Multimedia Card Interface
10
UDP
USB Device Port
11
TWI0
Two Wire Interface 0
12
SPI0
Serial Peripheral Interface 0
13
SPI1
Serial Peripheral Interface1
14
SSC
Synchronous Serial Controller
15
-
Reserved
16
-
Reserved
17
TC0
Timer/Counter 0
18
TC1
Timer/Counter 1
19
TC2
Timer/Counter 2
20
UHP
USB Host Port
21
EMAC
Ethernet MAC
22
ISI
Image Sensor Interface
23
US3
USART 3
24
US4
USART 4
25
TWI1
Two Wire Interface 1
26
TC3
Timer/Counter 3
27
TC4
Timer/Counter 4
28
TC5
Timer/Counter 5
29
AIC
Advanced Interrupt Controller
IRQ0
30
AIC
Advanced Interrupt Controller
IRQ1
31
AIC
Advanced Interrupt Controller
IRQ2
Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
37
6254AS–ATARM–14-Feb-08
10.2.1
Peripheral Interrupts and Clock Control
10.2.1.1
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
• Enhanced Embedded Flash Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2
10.3
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9XE128/256/512 features 3 PIO controllers, PIOA, PIOB, PIOC, which multiplex
the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and
“Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral function which are output only, might be duplicated within the both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
38
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
10.3.1
PIO Controller A Multiplexing
Table 10-2.
Multiplexing on PIO Controller A
PIO Controller A
Application Usage
Reset
State
Power
Supply
MCDB0
I/O
VDDIOP0
MCCDB
I/O
VDDIOP0
I/O
VDDIOP0
MCDB3
I/O
VDDIOP0
RTS2
MCDB2
I/O
VDDIOP0
PA5
CTS2
MCDB1
I/O
VDDIOP0
PA6
MCDA0
I/O
VDDIOP0
PA7
MCCDA
I/O
VDDIOP0
PA8
MCCK
I/O
VDDIOP0
PA9
MCDA1
I/O
VDDIOP0
PA10
MCDA2
ETX2
I/O
VDDIOP0
PA11
MCDA3
ETX3
I/O
VDDIOP0
PA12
ETX0
I/O
VDDIOP0
PA13
ETX1
I/O
VDDIOP0
PA14
ERX0
I/O
VDDIOP0
PA15
ERX1
I/O
VDDIOP0
PA16
ETXEN
I/O
VDDIOP0
PA17
ERXDV
I/O
VDDIOP0
PA18
ERXER
I/O
VDDIOP0
PA19
ETXCK
I/O
VDDIOP0
PA20
EMDC
I/O
VDDIOP0
PA21
EMDIO
I/O
VDDIOP0
PA22
ADTRG
ETXER
I/O
VDDIOP0
PA23
TWD0
ETX2
I/O
VDDIOP0
PA24
TWCK0
ETX3
I/O
VDDIOP0
PA25
TCLK0
ERX2
I/O
VDDIOP0
PA26
TIOA0
ERX3
I/O
VDDIOP0
PA27
TIOA1
ERXCK
I/O
VDDIOP0
PA28
TIOA2
ECRS
I/O
VDDIOP0
PA29
SCK1
ECOL
I/O
VDDIOP0
SCK2
RXD4
I/O
VDDIOP0
I/O
VDDIOP0
I/O Line
Peripheral A
Peripheral B
PA0
SPI0_MISO
PA1
SPI0_MOSI
PA2
SPI0_SPCK
PA3
SPI0_NPCS0
PA4
(1)
PA30
(1)
PA31
Note:
SCK0
TXD4
1. Not available in the 208-lead PQFP package.
Comments
Function
Comments
39
6254AS–ATARM–14-Feb-08
10.3.2
PIO Controller B Multiplexing
Table 10-3.
Multiplexing on PIO Controller B
PIO Controller B
I/O Line
Peripheral A
Peripheral B
PB0
SPI1_MISO
PB1
Application Usage
Reset State
Power Supply
TIOA3
I/O
VDDIOP0
SPI1_MOSI
TIOB3
I/O
VDDIOP0
PB2
SPI1_SPCK
TIOA4
I/O
VDDIOP0
PB3
SPI1_NPCS0
TIOA5
I/O
VDDIOP0
PB4
TXD0
I/O
VDDIOP0
PB5
RXD0
I/O
VDDIOP0
PB6
TXD1
TCLK1
I/O
VDDIOP0
PB7
RXD1
TCLK2
I/O
VDDIOP0
PB8
TXD2
I/O
VDDIOP0
PB9
RXD2
I/O
VDDIOP0
PB10
TXD3
ISI_D8
I/O
VDDIOP1
PB11
RXD3
ISI_D9
I/O
VDDIOP1
PB12(1)
TWD1
ISI_D10
I/O
VDDIOP1
PB13(1)
TWCK1
ISI_D11
I/O
VDDIOP1
PB14
DRXD
I/O
VDDIOP0
PB15
DTXD
I/O
VDDIOP0
PB16
TK0
TCLK3
I/O
VDDIOP0
PB17
TF0
TCLK4
I/O
VDDIOP0
PB18
TD0
TIOB4
I/O
VDDIOP0
PB19
RD0
TIOB5
I/O
VDDIOP0
PB20
RK0
ISI_D0
I/O
VDDIOP1
PB21
RF0
ISI_D1
I/O
VDDIOP1
PB22
DSR0
ISI_D2
I/O
VDDIOP1
PB23
DCD0
ISI_D3
I/O
VDDIOP1
PB24
DTR0
ISI_D4
I/O
VDDIOP1
PB25
RI0
ISI_D5
I/O
VDDIOP1
PB26
RTS0
ISI_D6
I/O
VDDIOP1
PB27
CTS0
ISI_D7
I/O
VDDIOP1
PB28
RTS1
ISI_PCK
I/O
VDDIOP1
PB29
CTS1
ISI_VSYNC
I/O
VDDIOP1
PB30
PCK0
ISI_HSYNC
I/O
VDDIOP1
PB31
PCK1
ISI_MCK
I/O
VDDIOP1
Note:
40
Comments
Function
Comments
1. Not available in the 208-lead PQFP package.
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
10.3.3
PIO Controller C Multiplexing
Table 10-4.
Multiplexing on PIO Controller C
PIO Controller C
I/O Line
Peripheral A
Application Usage
Peripheral B
Comments
Reset State
Power Supply
PC0
SCK3
AD0
I/O
VDDIOP0
PC1
PCK0
AD1
I/O
VDDIOP0
(1)
PCK1
AD2
I/O
VDDIOP0
(1)
SPI1_NPCS3
AD3
I/O
VDDIOP0
PC2
PC3
PC4
A23
SPI1_NPCS2
A23
VDDIOM
PC5
A24
SPI1_NPCS1
A24
VDDIOM
PC6
TIOB2
CFCE1
I/O
VDDIOM
PC7
TIOB1
CFCE2
I/O
VDDIOM
PC8
NCS4/CFCS0
RTS3
I/O
VDDIOM
PC9
NCS5/CFCS1
TIOB0
I/O
VDDIOM
PC10
A25/CFRNW
CTS3
A25
VDDIOM
PC11
NCS2
SPI0_NPCS1
I/O
VDDIOM
PC12(1)
IRQ0
NCS7
I/O
VDDIOM
PC13
FIQ
NCS6
I/O
VDDIOM
PC14
NCS3/NANDCS
IRQ2
I/O
VDDIOM
PC15
NWAIT
IRQ1
I/O
VDDIOM
PC16
D16
SPI0_NPCS2
I/O
VDDIOM
PC17
D17
SPI0_NPCS3
I/O
VDDIOM
PC18
D18
SPI1_NPCS1
I/O
VDDIOM
PC19
D19
SPI1_NPCS2
I/O
VDDIOM
PC20
D20
SPI1_NPCS3
I/O
VDDIOM
PC21
D21
EF100
I/O
VDDIOM
PC22
D22
TCLK5
I/O
VDDIOM
PC23
D23
I/O
VDDIOM
PC24
D24
I/O
VDDIOM
PC25
D25
I/O
VDDIOM
PC26
D26
I/O
VDDIOM
PC27
D27
I/O
VDDIOM
PC28
D28
I/O
VDDIOM
PC29
D29
I/O
VDDIOM
PC30
D30
I/O
VDDIOM
PC31
D31
I/O
VDDIOM
Note:
Function
Comments
1. Not available in the 208-lead PQFP package.
41
6254AS–ATARM–14-Feb-08
10.4
10.4.1
Embedded Peripherals
Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.4.2
Two-wire Interface
• Master, Multi-master and Slave modes supported
• General call supported in Slave mode
• Connection to PDC Channel
10.4.3
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by 16 oversampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
42
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.4.4
Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
10.4.5
Timer Counter
• Six 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
10.4.6
Multimedia Card Interface
• One double-channel Multimedia Card Interface
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Compatibility with SDIO Specification Version V1.0.
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• MCI has two slots, each supporting
– One slot for one MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
• Support for stream, block and multi-block data read and write
43
6254AS–ATARM–14-Feb-08
10.4.7
USB Host Port
• Compliance with Open HCI Rev 1.0 Specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
• Root hub integrated with two downstream USB ports in the 217-LFBGA package
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Matrix
10.4.8
USB Device Port
• USB V2.0 full-speed compliant, 12 MBits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 2,688-byte dual-port RAM for endpoints
• Suspend/Resume logic
• Ping-pong mode (two memory banks) for isochronous and bulk endpoints
• Eight general-purpose endpoints
– Endpoint 0 and 3: 64 bytes, no ping-pong mode
– Endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode
– Endpoint 4 and 5: 512 bytes, ping-pong mode
• Embedded pad pull-up
10.4.9
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface control of alarm and update
time/calendar data in
10.4.10
Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
44
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
• Preview scaler to generate smaller size image
10.4.11
Analog-to-digital Converter
• 4-channel ADC
• 10-bit 312K samples/sec. Successive Approximation Register ADC
• -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
• Individual enable and disable of each channel
• External voltage reference for better accuracy on low voltage inputs
• Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter
0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep
mode after conversions of all enabled channels
• Four analog inputs shared with digital signals
45
6254AS–ATARM–14-Feb-08
11. Package Drawings
Figure 11-1. 208-pin PQFP Package Drawing
46
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
Figure 11-2. 217-ball LFBGA Package Drawing
47
6254AS–ATARM–14-Feb-08
12. AT911SAM9XE128/256/512 Ordering Information
Table 12-1.
48
AT91SAM9XE128/256/512 Ordering Information
Ordering Code
Package
Package Type
Temperature Operating Range
AT91SAM9XE128-QU
PQFP208
Green
AT91SAM9XE128-CU
BGA217
Green
Industrial
-40°C to 85°C
AT91SAM9XE256-QU
PQFP208
Green
AT91SAM9XE256-CU
BGA217
Green
AT91SAM9XE512-QU
PQFP208
Green
AT91SAM9XE512-CU
BGA217
Green
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
AT91SAM9XE128/256/512 Preliminary
6254AS–ATARM–14-Feb-08
AT91SAM9XE128/256/512 Preliminary
13. Revision History
Table 13-1.
Document Ref.
Comments
6254AS
First issue.
Change Request Ref.
49
6254AS–ATARM–14-Feb-08
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6254AS–ATARM–14-Feb-08
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