HP ACPM-7833-TR1 Cdma1900 (pcs) power amplifier module Datasheet

Agilent ACPM-7833
CDMA1900 (PCS)
Power Amplifier Module
Data Sheet
Features
• Operating frequency:
1850 – 1910 MHz
• 28.5 dBm linear output power
@ 3.4 V
• High efficiency: 40% PAE
Description
The ACPM-7833 is a fully
matched CDMA Power amplifier
module. Designed around Agilent
Technologies’ new Enhancement
Mode pHEMT process, the
ACPM-7833 offers premium
performance in a very small form
factor. Fully matched to 50 Ohms
on the input and output.
The amplifier has excellent ACPR
and efficiency performance at
max Pout and low quiescent
• Dynamic bias control for low
midpower Idd
current with a single bias control
voltage. For even lower quiescent
current, a dynamic bias control
circuit can be used by varying
the voltage on the Vcntl pin
between 1.2V to 2.5V.
Designed in a surface mount RF
package, the ACPM-7833 is cost
and size competitive.
The ACPM-7833 is another key
component of the Agilent
CDMAdvantage RF chipset.
• Very low quiescent current with
single control voltage
• Internal 50 ohm matching networks
for both RF IN/OUT
• 3.2 – 4.2 V linear operation
• cdma2000 1xRTT capable
• Only 3 SMT parts needed
• 4.0 x 4.0 x 1.1 mm SMT package
Applications
• CDMA handsets
• Datacards
• PDAs
Vdd1
Vbias
Vdd2
Bias Circuit
Input
Power
Input
Match
On Chip
Inter-stage
Match
Passive
Output
Match
Output
Vcntl
Single control bias setting for low Idq
and 40% PAE at Pout = 28.5 dBm
Maximum Ratings [1]
Parameter
Min.
Max.
Vdd Supply Voltage
6.0 V
Power Dissipation [2]
2.5 W
Bias Current
1.5 A
Control Voltage (Vcntl)
3.0 V
Amplifier Input RF Power
10 dBm
Junction Temperature
+150°C
Storage Temperature (case temperature)
-40°C
Thermal Resistance[2] θjc = 22.3°C/W
Recommended operating range of Vdd = 3.2 to
4.2 V, Ta = -30 to +85°C
+100°C
Notes:
1. Operation of this device in excess of any of these limits may cause permanent damage.
2. Tcase = 25°C
Package Marking and Dimensions
Vdd2
(Pin 10)
Agilent
ACPM-7833
YYWWDD
XXXX
Vdd1 (Pin 1)
Gnd
RFin
RFout
Gnd
Vcntl
Gnd
Gnd
4.0 mm (sq)
Gnd
Vbias
1.1 mm
Top View
Side View
Bottom View
Note:
YYWWDD: year – work week – day
XXXX: lot code
0.400±0.076
0.850±0.076
2.000±0.076
0.850±0.076
0.850±0.076
4.000±0.076
0.850±0.076
3.80±0.076
2.000±0.076
3.400±0.076
4.000±0.076
1.100±0.076
All units are in mm
2
Electrical Characterization Information
All tests are done in 50Ω system at Vdd1=Vdd2=Vbias = 3.4V, 25°C, unless noted otherwise.
Parameter
Units
Min
Typ
Max
Comments
MHz
1850
dB
25.5
27.5
29.5
Vcntl= 2.5V
24
26
28
Vcntl= 1.8V
PCS CDMA
Frequency Range
1910
Gain (Fixed Cntl Voltage)
Pout = 28.5 dBm
Pout = 16 dBm
Power Added Efficiency
Pout = 28.5 dBm
%
38
40
Vcntl= 2.5V
Pout = 16 dBm
%
7.5
8.5
Vcntl= 1.8V
Total Supply Current
mA
mA
mA
520
135
31
ACPR @ ± 1.25 MHz offset
dBc/30 kHz
-45
-48
Pout ≤ 28.5 dBm
ACPR @ ± 1.98 MHz offset
dBc/30 kHz
-53
-55
Pout ≤ 28.5 dBm
Quiescent Current
mA
mA
mA
62
47
25
80
60
Pout ≤ 28.5 dBm, Vcntl= 2.5V
Vcntl = 1.8V
Vcntl = 1.2V
Vcntl Current
mA
2.0
2.7
Vcntl = 2.5V
Input VSWR (Pout = 28.5 dBm)
3
550
156
Pout = 28.5 dBm, Vcntl= 2.5V
Pout =16 dBm, Vcntl= 1.8V
Pout = -5 dBm, Vcntl = 1.2V
2.0:1
Noise Figure
dB
4.5
Noise Power @ 80 MHz offset in 1930– 1990 MHz
dBm/Hz
-141
Stability (Spurious): Load VSWR 5:1
dBc
-50
Harmonic Suppression: 2Fo
dBc
-30
-138
All phases
-38
Typical Performance, data measured in 50Ω system, Vdd1=Vdd2=Vbias = 3.4V, Vcntl = 2.5 V, T = 25°C and Freq = 1880 MHz unless
noted otherwise.
50
40
30
29
40
28
20
26
25
24
PAE (%)
GAIN (dB)
GAIN (dB)
27
0
30
20
23
-20
Vcntl=2.5V
Vcntl=1.6V
Vcntl=1.2V
22
21
10
-40
20
0
5
10
15
20
25
0
0
30
0.4
0.8
1.2
1.6
2.0
2.4
2.8
0
5
10
Vcntl (V)
Pout (dBm)
Figure 1. Gain vs. Pout.
Figure 2. Gain vs. Vcntl.
500
15
20
25
30
Pout (dBm)
Figure 3. PAE vs. Pout.
-40
160
140
-45
300
200
ACPR1 (dBc)
120
Idd (mA)
Idd (mA)
400
100
80
60
Vcntl=2.5V
Vcntl=1.6V
Vcntl=1.2V
40
100
20
0
5
10
15
20
25
30
-65
0
5
Pout (dBm)
15
20
HARMONIC SUPPRESSION (dBc)
-60
-65
-70
-75
-80
2nd
3rd
-35
-40
-45
-85
-90
0
5
10
15
20
25
30
Pout (dBm)
Figure 7. ACPR (1.98 MHz offset) vs. Pout.
4
-50
10
15
20
0
5
10
15
20
25
30
Figure 6. ACPR (1.25 MHz offset) vs. Pout.
-30
-55
Vcntl=1.2V
Vcntl=1.6V
Vcntl=2.5V
Pout (dBm)
Figure 5. Idd vs. Output Power.
-50
ACPR2 (dBc)
10
Pout (dBm)
Figure 4. Idd vs. Output Power.
-55
-60
0
0
-50
25
Pout (dBm)
Figure 8. 2nd/3rd Harmonics vs. Pout.
30
Ordering Information
Part Number
No. of Devices
Container
ACPM-7833-BLK
10
Bulk
ACPM-7833-TR1
1000
7” Tape and Reel
Tape Dimensions and Orientation
0.30 ± 0.05
4.00 ± 0.10[2]
2.00 ± 0.05[1]
1.75 ± 0.10
φ1.55 ± 0.05
5.50 ± 0.05[3]
CL
12.00 ± 0.30
4.38 ± 0.10
4.38 ± 0.10
φ1.50 (MIN)
1.80 ± 0.10
8.00 ± 0.10
4.38 ± 0.10
Notes:
1. Measured from centerline of sprocket hole to centerline of pocket
2. Cumulative tolerance of 10 sprocket holes is ±0.2 mm
3. All dimensions in millimeters unless otherwise stated.
Agilent
ACPM-7833
YYWWDD
XXXX
5
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
–0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
–0.0
FRONT VIEW
1.5 min.
13.0±0.2
21.0±0.8
6
NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Agilent Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
be issued and accompany each shipment
of product.
3. Reel must not be made with or contain
ozone depleting materials.
4. All dimensions in millimeters (mm)
Application Information
The
•
•
•
•
•
•
following material is presented to assist in general design and use of the APCM-7833.
3.0V Characterization, for use in Data Card Applications
cdma2000 1XRTT Description and Characterization data
Design tips on various methods to control the bias on Vcntl pin
Description of ACPR measurement methods
Description of Agilent evaluation demoboard for ACPM-7833
IR Reflow Profile (applicable for all Agilent E-pHEMT PAs)
3.0 V Characterization, Data Card Applications
Electrical Data
All tests are done in 50Ω system at Vdd1=Vdd2=Vbias = 3.0V, 25°C, unless noted otherwise.
Parameter
Units
Min
MHz
1850
Typ
Max
Comments
1900 MHz CDMA
Frequency Range
1910
Gain (Fixed Cntl Voltage)
(Pout = 28.5 dBm)
dB
26
Vcntl = 2.5V
(Pout = 13 dBm)
dB
28
Vcntl = 2.5V
(Pout = -5 dBm)
dB
28
Vcntl = 2.5V
Power Added Efficiency
Pout = 28.0 dBm
%
42
Vcntl = 2.5V
Pout = 16 dBm
%
8.5
Vcntl = 2.5V
Total Supply Current
mA
500
Pout = 28.0 dBm, Vcntl= 2.5V
100
Pout = 13 dBm, Vcntl= 1.6V
30
Pout = -5 dBm, Vcntl= 1.2V
ACPR @ ± 1.25 MHz offset
dBc/30 kHz
-43
Pout ≤ 28.5 dBm
ACPR @ ± 1.98 MHz offset
dBc/30 kHz
-56
Pout ≤ 28.5 dBm
Quiescent Current
mA
60
Pout ≤ 28.5 dBm, Vcntl = 2.5V
Input VSWR
(Pout = 28.5 dBm)
2.0:1
(Pout = 16 dBm)
2.5:1
Noise Figure
dB
4.5
Noise Power @ 80 MHz offset in 1930 - 1990 MHz
dBm/Hz
-141
Stability (Spurious): Load VSWR 5:1
dBc
-50
2Fo
dBc
-40
3Fo
dBc
-40
Harmonic Suppression
7
All phases
50
500
29
40
400
28
30
300
27
20
26
10
Idd (mA)
30
PAE (%)
GAIN (dB)
Typical Performance, data measured in 50Ω system, Vdd1=Vdd2=Vbias = 3.0V, Vcntl = 2.5 V, T = 25°C and Freq =1880 MHz.
100
0
25
0
5
10
15
20
25
0
0
30
5
10
15
20
25
30
0
5
10
Pout (dBm)
Pout (dBm)
Figure 9. Gain vs. Pout.
HARMONIC SUPPRESSION (dBc)
ACPR2 (dBc)
-60
-55
-65
-70
-75
-80
-60
-90
0
5
10
15
20
25
30
Pout (dBm)
40
GAIN (dB)
20
0
-20
-40
0
0.4
0.8
1.2
1.6
Vcntl (V)
Figure 15. Gain vs. Vcntl.
8
0
5
10
15
20
25
30
Pout (dBm)
Figure 12. ACPR (1.25 MHz offset) vs. Pout.
2.0
2.4
2.8
30
-35
-40
-45
2nd
3rd
-85
-65
25
-30
-55
-50
20
Figure 11. Idd vs. Pout.
-50
-45
15
Pout (dBm)
Figure 10. PAE vs. Pout.
-40
ACPR1 (dBc)
200
Figure 13. ACPR (1.98 MHz offset) vs. Pout.
-50
10
15
20
25
30
Pout (dBm)
Figure 14. Harmonic Suppression vs. Pout.
cdma 2000 1xRTT Characterization
System Description
standard, has a chip rate of
1.2288Mchip/s. However, in
1xRTT, the reverse link transmits
more than one code channel to
accommodate the high data
rates. The minimum configuration consists of a reverse pilot
(R-Pilot) channel for synchronous detection by the Base
Transceiver System (BTS) and a
reverse fundamental channel
(R-FCH) for voice. Additional
CDMA2000 is the TIA’s standard
for third generation (3G) technology and is an evolution of the IS95 CDMA format. CDMA2000
includes 1X RTT in the singlecarrier mode and 3X RTT in the
multi-carrier mode. This paper
describes the CDMA2000 1X RTT
approach and its performance
with Agilent 4x4 CDMA PAs,
ACPM-7833. CDMA2000 1X RTT,
being an extension of the IS-95
channels such as the reverse
supplemental channels (R-SCHs)
and the reverse dedicated
channel (R-DCCH) are used to
send data or signaling information. Channels can exist at
different rates and power levels.
Table 1 shows the transmitter
specification in CDMA2000
reverse link.
Table 1. Transmitter Specification in Reverse Link.
Specification
Spread Rate1
ERP at Maximum Output Power
Lower limit +23 dBm
Upper limit +30 dBm
Minimum Controlled Output Power
-50 dBm/1.23 MHz
Waveform Quality Factor and Frequency Accuracy
>0.944
Spurious Emission at
Maximum RF output
power offset frequency
within the range
SR1, Band Class 0(Cellular band)
SR1, Band Class1(PCS band)
885 kHz to 1.98 MHz
Less stringent of -42 dBc/30 kHz
or -54 dBm/1.23 MHz
1.25 MHz to 1.98 MHz
Less stringent of -42 dBc/30 kHz
or -54 dBm/1.23 MHz
1.98 MHz to 3.125 MHz
Less stringent of -54 dBc/30 kHz
or -54 dBm/1.23 MHz
1.98 MHz to 2.25 MHz
Less stringent of -50 dBc/30 kHz
or -54 dBm/1.23 MHz
3.125 MHz to 5.625 MHz
-13 dBm/100 kHz
2.25 MHz to 6.25 MHz
-13 dBm/1 MHz
Typical channel configurations below are based on the transmitter test condition in the reverse link.
1) “Basic” Voice only configuration
– R-PICH @ -5.3 dB
– R-FCH @ -1.5 dB 9.6 kbps
– R-FCH @ -3.85 dB 9.6 kbps
2) Voice and Data configuration
– R-PICH @ -5.3 dB
9
3) Voice and Control configuration
– R-PICH @ -5.3 dB
– R-DCCH @ -3.85 dB 9.6 kbps
4) Control channel only configuration
– R-FCH @ -4.54 dB 9.6 kbps
– R-PICH @ -5.3 dB
– R-SCH1 @ -4.54 dB 9.6 kbps
– R-DCCH @ -1.5 dB 9.6 kbps
Combinations of these channels
will increase the peak to average
power ratio for higher data rates.
The complementary cumulative
distribution function (CCDF)
measurement characterizes the
peak to average power statistics
of CDMA2000 reverse link. For
reference, the system specifications of peak to average power
ratio of IS-95 and CDMA2000 IX
RTT are 3.9 dB and 5.4 dB at
1% CCDF respectively.
Higher peak to average power
ratio requires a higher margin,
both in higher power gain and in
improved thermal stability for PA
linearity to meet the minimum
system specifications.
The test results below for the
ACPM-7833 show the compliance
to the system linearity specifications with 4 channel configurations, representing a broad crosssection of CDMA2000 1X RTT
environments.
Test result of ACPM-7833 using CDMA2000 1X RTT signal
Test condition - PA Evaluation board with Vdd1=Vdd2=Vbias = 3.4V, Vcntl = 2.5V, Frequency = 1880 MHz. Test result with each channel configuration.
Channel
IVdd(mA)
Pin(dBm)
1.25 MHz
ACPR(dBc)
1.25 MHz
ACPR(dBc)
-1.98 MHz
ACPR(dBc)
+1.98 MHz
ACPR(dBc)
Pout(dBm)
Basic
451.0
-0.14
-52.6
-51.5
-60.2
-60
28
Voice+Data
435.0
0.52
-46.2
-45.7
-58.0
-58.3
28
Voice+Cntl
439.0
0.50
-45.5
-44.9
-60.1
-60
28
Cntl only
299.0
-2.56
-49.1
-48.8
-57.7
-57.5
25.5
EIA/TIA-98-D indicates a 2.5 dB allowed back off in power for control channel only configuration.
Peak to average power ration (Pout = 16 dBm)
CCDF(%)
Basic
Voice + Data
Voice + CNTL
CNTL only
10
2.11
3.37
3.44
4.00
1
3.74
4.83
5.21
5.75
0.1
4.68
5.68
6.24
6.73
0.01
5.15
6.20
6.76
7.18
0.001
5.36
6.53
7.11
7.39
0.0001
5.48
6.63
7.17
7.45
10
Design Tips to use Vcntl pin
Power Amplifier Control Using Vcntl
Pin on ACPM-7833
Power amplifier control scheme
in CDMA systems is one of the
important and challenging
aspects of CDMA-based handset
design. Handset designers must
balance maintaining adequate
linearity while optimizing
efficiency at high, medium and
low output power levels. The
primary method to achieve these
goals is to adjust the bias of the
PA as a function of output power.
Theoretically, the best efficiency
would be achieved when the bias
of the PA is continually adjusted
based on the output power
requirement of the PA. However,
implementing this type of circuit
can be complex and costly.
Therefore several different
approaches have been developed
to provide an acceptable tradeoff between optimum efficiency
and optimum manufacturability.
This application section reviews
four methods of controlling the
bias of a CDMA power amplifier:
fixed, step, logical and dynamic.
1. Fixed Bias Control
Using a fixed bias point on the
PA is the traditional method, and
it is the simplest. For example,
the recommended value of the
fixed control voltage on the Vcntl
pin for the ACPM-7833 is 2.5V.
The Vcntl pin on the PA is
controlled by PA_ON pin of the
baseband IC. When PA_ON is
HIGH, the output RF signal of the
PA is enabled, enabling the
subscriber unit to transmit the
required data. The switch circuit
also controls the on/off state of
the PA.
Below is an example of how to
control the the output of the PA
using PA_ON and Vcntl pins.
Power Mode
PA_ON
Vcntl
Power Range
Shut Down
LOW
0V
—
High Power
HIGH
2.5V
≤ 28.5 dBm
Battery
To Duplexer
Vbias
Vdd2
Vdd1 PA
Vcntl
TxIC
Enable
Baseband
IC
PA_ON
Switch Circuit for PA
Vcntl
PMIC or LDO
11
Note: PMIC: Power Management IC
LDO: Low Drop Output (Regulator)
2. Step Bias Control and Dynamic
Bias Control (if controled PDM1)
The PDM1 output from the
baseband IC can be used to
create a software-programmable
voltage, to be used at the phone
designer’s discretion. To get high
efficiency and better ACPR, the
phone designers can change
control voltage of the PA by
adjusting PDM1 voltage according to output power of PA. A
caution when using this
approach—careful consideration
must be made to to avoid an
abrupt discontinuity in the
output signal when the step bias
control voltage is applied.
The figure below is an example of
how to control the PA for
multiple bias points using the
PA_ON and Vcntl pins.
Power Mode
PA_ON
Vcntl
Power Range
Shut Down
LOW
0V
—
Low Power
HIGH
1.2V
~ -5 dBm
Mid Power
HIGH
1.6V
-5 dBm ~ 13 dBm
High Power
HIGH
2.5V
13 dBm ~ 28.5 dBm
Battery
To Duplexer
Vbias
Vdd2
Vdd1
PA
Baseband
IC
TxIC
Vcntl
PA_ON
Enable
R1
Switch Circuit for PA
C1
PDM1
If PDM1 can be controlled then same circuit can be used for Dynamic bias control
12
3. Dynamic Bias Control Alternate
Implementation
Phone designers can use
TX_ADC_ADJ pin of the
baseband IC to get dynamic bias
control with Vcntl pin of PA.
TX_ADC_ADJ is a PDM output
pin produced by the TX AGC
subsystem and used to control
the gain of the Tx signal prior to
the PA. The variable output levels
from two inverting operational
amplifiers, generated and
compared by TX_ADC_ADJ,
provide dynamic control voltages
for the Vcntl of 1.0V ~ 2.7V with
a 0.1V step.
Battery
To Duplexer
Vbias
Vdd2
Vdd1 PA
Vcntl
TxIC
Baseband IC
Vcontrol
Enable
Switch Circuit
PA_ON
R5
R3
R4
V1
R1
_
_
+
R2 Vin
C1
TX_ADC_ADJ
Av = -(V1/Vin) = -R3/R2,
V1 = -(R3/R2)Vin,
Vo = -(R5/R4)V1= [(R5*R3)/(R4*R2)]*Vin
The using of combination of two
pins, PDM1 and TX_ADC_ADJ, is
another method of realizing a
dynamic bias control scheme.
The two OP Amps control the
Vcntl voltage levels with compared and integrated circuits.
Battery
To Duplexer
Vbias
Vdd2
Vdd1 PA
Vcntl
TxIC
Baseband IC
Vcontrol
PA_ON
Enable
Switch Circuit
_
_
TX_ADC_ADJ
+
+
PDM1
13
ACPR Measurement Method
Adjacent-channel power ratio
(ACPR) is used to characterize
the distortion of power amplifiers
and other subsystems for their
tendency to cause interference
with neighboring radio channels
or systems. The ACPR measurement often is specified as the
ratio of the power spectral
density (PSD) of the CDMA main
channel to the PSD measured at
several offset frequencies. For the
Cellular band (824 ~ 849 MHz
transmitter channel), the two
offsets are at ±885 kHz and
±1.98 MHz and the measurement
resolution bandwidth specified is
30 kHz. These offsets are at
±1.25 MHz and ±1.98 MHz for the
PCS band (1850 ~ 1910 MHz
transmitter channel).
1.23 MHz
0
-10
1st ACPR (dBc)
-20
30 kHz
-40
-50
2nd ACPR (dBc)
30 kHz
-30
30 kHz
1st ACPR-L
1st ACPR-U
Offset frequency
-60
-70
-80
2nd ACPR-L
= 1.98 MHz
2nd ACPR-U
= 1.98 MHz
FREQUENCY (MHz)
Figure 16. CDMA Adjacent-Channel Power Ratio Measurement.
14
30 kHz
ACPR Testing Diagram Test
PA Test Setup
DC Power Supply
CH1 CH2 CH3 CH4
8593E
Spectrum
Analyzer
Vbias
Vcntl
Power
Divider
20 dB
Attenuator
E4406A
VSA Transmitter
Tester
CDMA PA
ACPM-7833
Figure 17. ACPR test equipment setup.
ACPM-7833 Test Result using VSA Transmitter Tester
Figure 18. ACPR measurement using VSA Transmitter tester.
15
Vdd2
Vdd1
3 dB
Attenuator
E4437B
CDMA Signal
Generator
ACPR Test Results using Spectrum Analyzer
REF 42.8 dBm
Mkr 836 MHz
35.42 dBm
AT 30 dB
RBW = 1.0 MHz
RBW = 300 kHz
RBW = 30 kHz
Center 836 MHz
Span 5.000 MHz
SWP 2.00 sec
VBW 100 kHz
Figure 19. Example ACPR measurement using Spectrum Analyzer.
The meaning of 16 dB
The accurate ACPR measurement
using Spectrum Analyzer needs
to consider the normalization
factor that is dependent on the
Resolution Bandwidth, RBW,
settings. The above figure (measurement shown at 836 MHz for
general example) shows a comparison of the different ACPR
measurement results as a function of various RBW values. As
the RBW is reduced, less power is
captured during the measurement and consequently the
channel power is recorded as a
16
smaller value. For example, if the
main channel power is measured
as 28 dBm in a 1.23 MHz bandwidth, its power spectral density
is 28 dBm/1.23 MHz, which can
be normalized to 11.87 dBm/
30 kHz. The equation used to
calculate the normalization factor
of power spectral density is:
Normalization Factor =
10log[Normalization BW/Current BW
(Spectrum Analyzer RBW)]
= 10log[1.23X106/30X103]
= 16.13 dB
Since the ACPR in an IS95
system is specified in a 1.23 MHz
bandwidth, a channel power that
is measured using a different
RBW, can be normalized to
reflect the channel power as if it
was measured in a 1.23 MHz
bandwidth. The difference in
channel power measured in
30 kHz bandwidth and the
channel power measured in a
1.23 MHz bandwidth is 16 dB.
ACPM-7833 Demoboard
Operation Instructions
1) Module Description
The ACPM-7833 is a fully matched
Power Amplifier. The sample
devices are provided on a demonstration PC Board with SMA
connectors for RF inputs and
outputs, and a DC connector for
all bias and control I/O’s. Please
refer to Figures 20 through 23 and
the Pin configuration table for I/O
descriptions and connections.
2.2 µF
Vdd2
RF Out
Vdd2
Vdd1
GND
RFin
4700 pF
4700 pF
Vdd1
RFin
RFout
GND
GND
Vcntl
4700 pF
GND
GND
Vbias
Vcntl
4700 pF
Vbias
Vdd2 (f)
GND
Vdd1 (f)
Vbias (f)
GND
Figure 20. ACPM-7833 Evaluation Board Schematic and Layout.
C3
RF in
C2
C1
C4
RF out
C5
PCS
4x4 v2
Figure 21. Layer 1 – Top Metal & Solder Mask.
17
C1 = 4700 pF
C2 = 4700 pF
C3 = 2.2 µF
C4 = 4700 pF
C5 = 4700 pF
Figure 22. Layer 2 – Ground.
Figure 23. Layer 3 – Bottom Metal & Solder Mask.
PIN Configuration Table
Top side
Back side
1
GND
1b Vdd2 (s)
2
Vbias
2b GND
3
Vdd1
3b Vdd1 (s)
4
GND
4b Vcntl
5
Vdd2
5b Vbias (s)
18
2) Circuit Operation
5) Testing
The design of the power module
(PAM) provide bias control via
Vcntl to achieve optimal RF
performance and power control.
The control pin is labeled Vcntl.
Please refer to for the block
diagram of this PAM.
- Signal Source
The CDMA modulated signal for
the test is generated using an
Agilent ESG-D4000A (or ESGD3000A) Digital Signal Generator
with the following settings:
CDMA Setup : Reverse
Spreading: On
Bits/Symbol: 1
Data: PN15
Modulation: OQPSK
Chip Rate: 1.2288 Mcps
High Crest: On
Filter: Std
Phase Polarity: Invert
Typical Operation Conditions
(Vdd1=Vdd2=Vbias = 3.4V)
Parameter
ACPM-7833
Frequency Range
1850 – 1910 MHz
Output Power
28.5 dBm
Vcntl
2.5 V
- ACPR Measurement
The ACPR (and channel power) is
measured using an Agilent 4406
VSA with corresponding ACPR
offsets for IS-98c and JSTD-8.
Averaging of 10 is used for ACPR
measurements.
3) Maximum Ratings
Vdd
5.0V
Drain Current
1.5A
Vcntl
3V
RF input
10 dBm
Temperature
-30 to 85°C
Please Note: Avoid Electrostatic Discharge
on all I/O’s.
4) Heat Sinking
The demonstration PC Board
provides an adequate heat sink.
Maximum device dissipation
should be kept below 2.5 Watts.
Vdd1
- DC Connection
A DC connector is provided to
allow ease of connection to the
I/Os. Wires can be soldered to
the connector pins, or the
connector can be removed and
I/Os contacted via clip leads or
direct soldered connections. The
wiring of I/Os are listed in
Figures 20 through 23 and the
Pin configuration table. The Vdd
Vbias
Vdd2
Bias Circuit
Input
Passive
Input
Match
On Chip
Inter-stage
Match
Passive
Output
Match
Output
Vcntl
Single control bias setting for low Idq
and 40% PAE at Pout = 28.5 dBm
Figure 24. Power Module Block Diagram.
19
sense connections are provided
to allow the use of remotesensing power supplies of
compensation for PCB traces and
cable resistance.
- Device Operation
1) Connect RF Input and Output
for the band under test.
2) Terminate all unused RF
ports into 50 Ohms.
3) Connect Vdd1, Vdd2 and
Vdd3 supplies (including
remote sensing labeled
Vdd1 S, Vdd2 S and Vbias S
on the board). Nominal
voltage is 3.4V.
4) Connect Vcntl supply and set
reference voltage to the
voltage shown in the data
packet. Note that the Vcntl pin
is on the back side of the
demonstration board. Please
limit Vcntl to not exceed the
corresponding listed “DC
Biasing Condition” in the Data
Packet. Note that increasing
Vcntl over the corresponding
listed “DC Biasing Condition”
can result in power decrease
and current can exceed the
rated limit.
5) Apply RF input power according to the values listed in
“Operation Data” in Data
Packet.
6) Power down in opposite
sequence.
IR Reflow Soldering
Figure 25 is a straight-line
representation of the recommended nominal time-temperature profile from JESD22-A113-B
IR reflow.
TEMPERATURE (°C)
235
200
183
150
60 to 150s
above 183°C
100
50
0
30
60
Preheat
Zone
90
120
150
180
TIME (seconds)
Soak
Zone
210
Reflow
Zone
Figure 25. Time-temperature Profile for IR Reflow Soldering Process.
Table 2. IR Reflow Process Zone.
Process Zone
∆Temperature
∆Temperature/∆Time
Preheat Zone
25°C to 100°C
3°C/s MAX
Soak Zone
100°C to 150°C
0.5°C/s MAX (120s MAX)
Reflow Zone
150°C to 235°C (240°C MAX)
235°C to 150°C
4.5°C/s TYP
-4.5°C/s TYP
Cooling Zone
150°C to 25°C
-6°C/s MAX
Table 3. Classification Reflow Profiles.
Convection or IR/Convection
Average ramp-up rate (183°C to peak)
3°C/second max.
Preheat temperature 125 (± 25)°C
120 seconds max.
Temperature maintained above 183°C
60 – 150 seconds
Time within 5°C of actual peak temperature
10 – 20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6°C/second max.
Time 25°C to peak temperature
6 minutes max.
Note:
All temperatures measured refer to the package body surface.
20
240
270
Cooling
Zone
300
Zone 1 – Preheat Zone
The average heat up rate for
surface-mount component on
PCB shall be less than 3°C/
second to allow even heating for
both the component and PCB.
This ramp is maintained until it
reaches 100°C where flux
activation starts.
Zone 2 – Soak Zone
The flux is being activated here
to prepare for even and smooth
solder joint in subsequent zone.
The temperature ramp is kept
gradual to minimize thermal
mismatch between solder, PC
Board and components. Overramp rate here can cause solder
splatter due to excessive oxidation of paste.
Zone 3 – Reflow Zone
The third process zone is the
solder reflow zone. The temperature in this zone rises rapidly
from 183°C to peak temperature
of 235°C for the solder to trans-
form its phase from solid to
liquids. The dwell time at melting
point 183°C shall maintain at
between 60 to 150 seconds. Upon
the duration of 10-20 seconds at
peak temperature, it is then
cooled down rapidly to allow the
solder to freeze and form solid.
Extended duration above the
solder melting point can potentially damage temperature
sensitive components and result
in excessive inter-metallic growth
that causes brittle solder joint,
weak and unreliable connections.
It can lead to unnecessary damage to the PC Board and discoloration to component’s leads.
Zone 4 – Cooling Zone
The temperature ramp down rate
is 6°C/second maximum. It is
important to control the cooling
rate as fast as possible in order
to achieve the smaller grain size
for solder and increase fatigue
resistance of solder joint.
Nominal stencil thickness
Component lead pitch
0.102 mm (0.004 in)
Lead pitch less than 0.508 mm (0.020 in)
0.152 mm (0.006 in)
0.508 mm to 0.635 mm (0.02 in to 0.025 in)
0.203 mm (0.008 in)
Lead pitch greater than 0.635 mm (0.025 in)
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(916) 788-6763
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (65) 6756 2394
India, Australia, New Zealand: (65) 6755 1939
Japan: (+81 3) 3335-8152(Domestic/International), or
0120-61-1280(Domestic Only)
Korea: (65) 6755 1989
Singapore, Malaysia, Vietnam, Thailand, Philippines,
Indonesia: (65) 6755 2044
Taiwan: (65) 6755 1843
Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5989-0403EN
November 10, 2004
5989-1899EN
Solder Paste
The recommended solder paste is
type Sn6337A or Sn60Pb40A of
J-STD-006.
Note: Solder paste storage and shelf
life shall be in accordance with
manufacturer’s specifications.
Stencil or Screen
The solder paste may be deposited onto PCB by either screen
printing, using a stencil or
syringe dispensing. The recommended stencil thickness is in
accordance to JESD22-B102-C.
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