AD AD5535ABC 32-channel, 14-bit dac with full-scale output voltage programmable from 50 v to 200 v Datasheet

32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
AD5535
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
High integration: 32-channel, 14-bit DAC with integrated,
high voltage output amplifier
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high
voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REFIN pin. Output range is 0 V to 50 V
with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each
amplifier can source 700 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
Guaranteed monotonic
Housed in 15 × 15 mm CSP-BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
700 µA drive capability
The selected DAC register is written to via the 3-wire interface.
The serial interface operates at clock rates of up to 30 MHz and
is compatible with DSP and microcontroller interface standards.
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
Channel update rate: 1.2 MHz
The device is operated with AVCC = 4.75 to 5.25 V, DVCC = 2.7 V
to 5.25 V, V– = −4.75 V to −5.25 V, V+ = +4.75 V to +5.25 V, VPP
= 210 V. REF_IN is buffered internally on the AD5535 and
should be driven from a stable reference source.
Asynchronous RESET facility
Temperature range: –10°C to +85°C
APPLICATIONS
Optical micro-electromechanical systems (MEMS)
Optical cross-point switches
Micropositioning applications using Piezo Flextures
Level setting in automotive test and measurement
FUNCTIONAL BLOCK DIAGRAM
DVCC
RESET
AVCC
REF_IN
VPP
PGND
V–
V+
ANODE
AD5535
CATHODE
DAC
R1
VOUT0
RF
14-BIT BUS
DAC
R1
DAC_GND
DAC
R1
AGND
VOUT30
RF
DAC
R1
INTERFACE
CONTROL
LOGIC
SCLK
DIN
VOUT31
RF
05068-001
DGND
VOUT1
RF
SYNC
Figure 1.
Rev. PrE
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5535
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Microprocessor Interfacing....................................................... 11
Timing Characteristics ................................................................ 5
Applications Information .............................................................. 13
Absolute Maximum Ratings............................................................ 6
MEMS Mirror Control Application......................................... 13
ESD Caution.................................................................................. 6
AD5535 Board Layout to Ensure Compliance with IPC-221
Specification................................................................................ 13
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description .................................................................. 11
Digital-to-Analog Section ......................................................... 11
Reset Function ............................................................................ 11
Power Supply Sequencing and Decoupling Recommendations
....................................................................................................... 14
Guidelines for Printed Circuit Board Layout ......................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Serial Interface ............................................................................ 11
REVISION HISTORY
10/04—Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 16
Preliminary Technical Data
AD5535
SPECIFICATIONS
VPP = 210 V, V− = −5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
1
Parameter
DC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero Code Voltage
Offset Error
Offset Drift
Voltage Gain
Gain Temperature Coefficient
Channel-to-Channel Gain Match
Full-Scale Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage Range3
Output Impedance
Resistive Load4, 5
Capacitive Load4
Short-Circuit Current
DC Crosstalk4
DC Power Supply Rejection (PSRR), VPP
AC CHARACTERISTICS
Settling Time
1/4 to 3/4 Scale Step
Min
14
±0.1
±0.5
–45
47.5
Max
±1
2
+45
52.5
VPP – 10
50
1
200
0.7
3
70
30
100
10
10
10
3
Slew Rate
0.1 Hz to 10 Hz Output Noise Voltage
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
VOLTAGE REFERENCE, REF_IN6
Input Voltage Range4
Input Current
TEMPERATURE MEASUREMENT DIODE4
Peak Inverse Voltage, PIV
Forward Diode Drop, VF
Forward Diode Current, IF
VF Temperature Coefficient, TC
0.09
50
TBD
5
8
0
1 LSB Step
–3 dB Bandwidth
Output Noise Spectral Density
A Grade2
Typ
Unit
Bits
% of FSR
LSB
V
mV
LSB/°C
V/V
ppm/°C
%
ppm/°C
TBD
TBD
TBD
TBD
13
TBD
Guaranteed monotonic
V
Ω
MΩ
pF
mA
LSB
dB
µs
µs
µs
µs
V/µs
V/µs
kHz
nV/√Hz
µV p-p
nV–s typ
nV–s typ
µV–s typ
nV–s typ
5
Conditions/Comments
No load
200 pF load
No load
200 pF load
No load
200 pF load
Measured at 1 kHz
1 LSB change around major carry
AVCC must exceed REFIN by 1.25 V min
1
4.096
1
V
µA
5
0.8
2
V
V
mA
mV/°C
–1.44
Rev. PrE | Page 3 of 16
Cathode to anode
IF = 2 mA, anode to cathode
Anode to cathode
IF = 250 µA
AD5535
Preliminary Technical Data
1
Parameter
DIGITAL INPUTS4
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis (SCLK and SYNC only)
Input Capacitance
POWER-SUPPLY VOLTAGES
VPP
V–
V+
AVCC
DVCC
POWER-SUPPLY CURRENTS7
IPP
I−
I+
AICC
DICC
POWER DISSIPATION
7
Min
A Grade2
Typ
Max
Unit
±10
0.8
10
µA
V
V
mV
pF
210
225
–4.75
5.25
5.25
5.25
V
V
V
V
V
75
2.5
2.5
16
0.1
609
110
3.5
3.5
20
0.5
µA/channel
mA
mA
mA
mA
mW
±5
2.0
200
(50 × REF_IN) +10
–5.25
4.75
4.75
2.7
1
Conditions/Comments
DVCC = 3 V to 5 V
DVCC = 3 V to 5 V
See Terminology.
A Grade temperature range: −10°C to +85°C; typically +25°C.
3
Linear output voltage range: +7 V to VPP − 10 V.
4
Guaranteed by design and characterization, not production tested.
5
Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section.
6
Reference input determines output voltage range. Using a 4.096 V reference (REF 198) gives an output voltage range of 0 V to 200 V. Output range is programmable
via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to VPP − 10 V.
7
Outputs unloaded.
2
Rev. PrE | Page 4 of 16
Preliminary Technical Data
AD5535
TIMING CHARACTERISTICS
VPP = 210 V, V− = –5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V.
All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2, 3
fUPDATE
fCLKIN
t1
t2
t3
t4
t5
t6
t7
t8
t9
A Grade
1.2
30
13
13
15
50
10
10
5
200
20
Unit
MHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Channel Update Rate
SCLK Frequency
SCLK High Pulse Width
SCLK Low Pulse Width
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
SYNC High Time
DIN Setup Time
DIN Hold Time
19th SCLK Falling Edge to SYNC Falling Edge for Next Write
RESET Pulse Width
1
See timing diagrams in Figure 2.
Guaranteed by design and characterization, not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
2
t1
SCLK
1
5
4
16
17
18
1
19
t2
t5
SYNC
3
2
t3
t4
t6
t8
t7
DIN
MSB
LSB
05068-002
RESET
t9
Figure 2. Serial Interface Timing Diagram
Rev. PrE | Page 5 of 16
AD5535
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VPP to AGND
Rating
0.3 V to 225 V
V− to AGND
V+ to AGND
AVCC to AGND, DAC_GND
DVCC to DGND
Digital Inputs to DGND
REF_IN to AGND, DAC_GND
VOUT 0–31 to AGND
Anode/Cathode to AGND, DAC_GND
AGND to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
124-Lead CSP-BGA Package,
θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
+0.3 V to −6 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V
−0.3 V to AVCC + 0.3 V
V– to VPP
−0.3 V to +7 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents up to 100 mA do not cause SCR latch-up.
This device is a voltage-integrated circuit with an ESD rating of
<2 kV and it is ESD sensitive. Proper precautions should be
taken for handling and assembly.
−10°C to +85°C
−65°C to +150°C
150°C
40°C/W
220°C
10 s to 40 s
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 6 of 16
Preliminary Technical Data
AD5535
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4
5 6
7 8 9 10 11 12 13 14
A
A
B
B
C
C
D
D
E
F
E
F
G
G
H
H
J
J
K
K
L
L
M
N
M
P
1 2 3 4
5 6
7 8 9 10 11 12 13 14
05068-003
N
P
Figure 3. Pin Configuration
Table 4. 124-Lead CSP-BGA Ball Configuration
CSP-BGA
Number
A1
A2
A4
A6
A8
A10
A12
A14
B1
B3
B5
B7
B9
B11
B13
C2
C12
Ball Name
N/C
VOUT 1
VOUT 7
VOUT 11
VOUT 16
VOUT 20
VOUT 25
N/C
VOUT 0
VOUT 4
VOUT 9
VOUT 13
VOUT 17
VOUT 21
VOUT 26
VOUT 3
VOUT 22
CSP-BGA
Number
C14
D1
D13
E2
E4
E6
E8
E10
E12
E14
F3
F5
F7
F9
F13
G14
H1
Ball Name
VOUT 29
VOUT 2
VOUT 23
VOUT 5
VOUT 8
VOUT 12
VOUT 15
VOUT 19
VOUT 24
VOUT 31
VOUT 6
VOUT 10
VOUT 14
VOUT 18
VOUT 30
VOUT 28
VPP
CSP-BGA
Number
H2
H13
J3–J12
K1
K2
K3–K14
L1
L2
L3–L13
L14
M1
M2
M3–12
M13
M14
N1
N2
Rev. PrE | Page 7 of 16
Ball Name
VPP
VOUT 27
AGND
V+
V+
AGND
V–
V–
AGND
DAC_GND
AGND
AGND
AGND
AVCC
AVCC
PGND
PGND
CSP-BGA
Number
N3
N4
N5–N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11–P13
P14
Ball Name
CATHODE
ANODE
AGND
N/C
REF_IN
DAC_GND
RESET
DVCC
DGND
TEST
DIN
SCLK
SYNC
AGND
N/C
AD5535
Preliminary Technical Data
Table 5. Pin Function Descriptions
Pin
AGND
AVCC
VPP
V+
V–
PGND
DGND
DVCC
DAC_GND
REF_IN
VOUT (0–31)
ANODE
CATHODE
SYNC
SCLK1
DIN1
TEST
RESET1
1
Function
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 10 V to 225 V.
V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V.
V– Amplifier Supply Pins. Voltage range from −4.75 V to −5.25 V.
Output Amplifier Ground Reference Pins.
Digital GND Pins.
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for All the DACs.
Reference Voltage for Channels 0–31. Reference input range is 1 V to 4 V and can be used to program the full-scale
output voltage from 50 V to 200 V.
Analog Output Voltages from the 32 Channels.
Anode of Internal Diode for Diode Temperature Measurement.
Cathode of Internal Diode for Diode Temperature Measurement.
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in
on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to
30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Allows the same data to be simultaneously loaded to all channels of the AD5535. This pin is used for calibration purposes
when loading zero scale and full scale to all channels. To invoke this feature, take the TEST pin high. In normal operation,
TEST should be tied low.
Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is
loaded to the DACs.
Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrE | Page 8 of 16
Preliminary Technical Data
AD5535
TERMINOLOGY
Integral Nonlinearity (INL)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is expressed as a percentage of full-scale range.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified DNL
of ±1 LSB maximum ensures monotonicity.
Zero-Code Voltage
A measure of the output voltage present at the device output
with all 0s loaded to the DAC. It includes the offset of the DAC
and the output amplifier. It is expressed in V.
Offset Error
Calculated by taking two points in the linear region of the
transfer function, drawing a line through these points, and
extrapolating back to the Y axis. It is expressed in mV.
Voltage Gain
Calculated from the change in output voltage for a change in
code multiplied by 16,384 and divided by the REF_IN voltage.
This is calculated between two points in the linear section of the
transfer function.
Gain Error
A measure of the output error with all 1s loaded to the DAC,
and is the difference between the ideal and actual analog output
range. Ideally, the output should be 50 × REF_IN. It is expressed
as a percentage of full-scale range.
DC Power-Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in VPP
supply voltage. It is expressed in dB. VPP is varied ±5%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and the output change of all other DACs. It is expressed
in LSB.
Output Temperature Coefficient
A measure of the change in analog output with changes in
temperature. It is expressed in ppm/°C.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within ±0.5 LSB of its final
value.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when the
code in the DAC register changes state. It is specified as the area
of the glitch in nV–s, when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . .
00 to 011 . . . 11).
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and
vice versa) is being written to another DAC. It is expressed
in nV–s.
Analog Crosstalk
The area of the glitch transferred to the output (VOUT) of one
DAC due to a full-scale change in the output (VOUT) of another
DAC. The area of the glitch is expressed in nV–s.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from
the digital control inputs when the part is not being written to
(SYNC is high). It is specified in nV–s and is measured with a
worst-case change on the digital input pins, for example, from
all 0s to all 1s and vice versa.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise
is characterized as a spectral density (voltage per √Hz). It is
measured by loading all DACs to midscale and measuring noise
at the output. It is measured in nV/(Hz)1/2.
Rev. PrE | Page 9 of 16
AD5535
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
16
1.00
VOUT = 200V
0.75
8
0.50
4
0
–4
0.25
0
–0.25
–8
–0.50
–12
–0.75
–16
0
2048
4096
6144
8192 10240 12288
CODE
05068-007
DNL ERROR (LSB)
12
05068-004
INL ERROR (LSB)
VOUT = 50V
–1.00
14336 16384
0
Figure 4. Integral Linearity with VPP = 60 V, VOUT Full Scale = 50 V
2048
4096
6144 8192 10240 12288
INPUT CODE
14336 16384
Figure 7. DNL with VPP = 210 V, VOUT Full Scale = 200 V
1.00
1.00
0.75
0.50
0.50
0.25
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
0
2048
4096
6144 8192 10240 12288
INPUT CODE
T
05068-008
DNL ERROR (LSB)
0.75
05068-005
DNL ERROR (LSB)
VOUT = 50V
–1.00
0CH1 5V
2048
14336 16384
CH2
M 500ns
4096 5V 6144 8192
10240 12288CH1
1433621.6V
16384
INPUT CODE
Figure 8. Short-Circuit Current Limit Timing
Figure 5.DNL with VPP = 60 V, VOUT Full Scale = 50 V
1.00
16
VOUT = 200V
12
0.75
8
0.50
0
–4
0.25
20
–0.25
–8
–0.50
1
–12
–0.75
–16
0
2048
4096
6144 8192 10240 12288
INPUT CODE
14336 16384
T
05068-009
DNL ERROR (LSB)
4
05068-006
INL ERROR (LSB)
T
–1.00
0CH1 50V
2048
CH2
M 10µ10240
s
4096 200mV
6144 8192
12288 CH1
14336 83V
16384
INPUT CODE
Figure 9. Worst-Case Adjacent Channel Crosstalk
Figure 6. Integral Linearity with VPP = 210 V, VOUT Full Scale = 200 V
Rev. PrE | Page 10 of 16
Preliminary Technical Data
AD5535
FUNCTIONAL DESCRIPTION
At power-on, all the DAC registers are loaded with 0s.
DIGITAL-TO-ANALOG SECTION
The architecture of each DAC channel consists of a resistor
string DAC followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary and the ideal DAC
output voltage is given by
VOUT =
A4 to A0 Bits
These bits can address any one of the 32 channels. A4 is the
MSB of the address; A0 is the LSB.
DB13 to DB0 Bits
These bits are used to write a 14-bit word into the addressed
DAC register.
Figure 2 is the timing diagram for a serial write to the AD5535.
The serial interface works with both a continuous and a discontinuous serial clock. The first falling edge of SYNC resets a
counter that counts the number of serial clocks to ensure that
the correct number of bits are shifted into the serial shift
register. Any further edges on SYNC are ignored until the
correct number of bits are shifted in. Once 19 bits have been
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
SYNC. The user must allow 200 ns (minimum) between
successive writes.
LSB
MSB
A4
50 × VREF _ IN × D
A3
A2
A1
A0
DB13–DB0
05068-010
The AD5535 consists of 32 14-bit DACs with 200 V high voltage
amplifiers in a single 15 mm × 15 mm CSP-BGA package. The
output voltage range is programmable via the REFIN pin.
Output range is 0 V to 50 V with REFIN = 1 V, and 0 V to 200 V
with REFIN = 4 V. Communication to the device is through a
serial interface operating at clock rates of up to 30 MHz and is
compatible with DSP and microcontroller interface standards. A
5-bit address and a 14-bit data-word are loaded into the
AD5535 input register via the serial interface. The channel
address is decoded, and the data-word is converted into an
analog output voltage for this channel.
Figure 10. Serial Data Format
214
where D is the decimal equivalent of the binary code, which is
loaded to the DAC register (0 to 16,383).
MICROPROCESSOR INTERFACING
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output
amplifier is from 7 V to VPP − 10V. The amplifier output bandwidth is typically 5 kHz, and is capable of sourcing 700 µA and
sinking 2.8mA. Settling time for a full-scale step is typically
30 µs with no load and 110 µs with a 200 pF load.
The ADSP-21xx family of DSPs is easily interfaced to the
AD5535 without the need for extra logic. A data transfer is
initiated by writing a word to the TX register after the SPORT
has been enabled. In a write sequence, data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
AD5535 on the falling edge of its SCLK. The easiest way to
provide the 19-bit data-word required by the AD5535, is to
transmit two 10-bit data-words from the ADSP-21xx. Ensure
that the data is positioned correctly in the TX register so that
the first 19 bits transmitted contain valid data.
RESET FUNCTION
The reset function on the AD5535 can be used to reset all nodes
on the device to their power-on reset condition. All the DACs
are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
SERIAL INTERFACE
AD5535 to ADSP-21xx Interface
Set up the SPORT control register as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
The serial interface is controlled by three pins:
DTYPE = 00, Right Justify Data
•
SYNC is the frame synchronization pin for the serial
interface.
ISCLK = 1, Internal Serial Clock
•
SCLK is the serial clock input. This pin operates at clock
speeds of up to 30 MHz.
ITFS = 1, Internal Framing Signal
•
DIN is the serial data input. Data must be valid on the falling
edge of SCLK.
TFSR = 1, Frame Every Word
SLEN = 1001, 10-Bit Data Word
Figure 11 shows the connection diagram.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535 input register.
Rev. PrE | Page 11 of 16
AD5535
Preliminary Technical Data
AD5535 to PIC16C6X/7X
DIN
SYNC
SCLK
DT
TFS
05068-011
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD5535 to ADSP-2101/ADSP-2103 Interface
AD5535 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5535 and the MOSI output drives the serial data line
(DIN) of the AD5535. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5535, the
SYNC line is taken low (PC7).
Data appearing on the MOSI output is valid on the falling edge
of SCK. The 68HC11 transfers only eight bits of data during
each serial transfer operation; therefore, three consecutive write
operations are necessary to transmit 19 bits of data. Data is
transmitted MSB first. It is important to left-justify the data in
the SPDR register so that the first 19 bits transmitted contain
valid data. PC7 must be pulled low to start a transfer. It is taken
high and pulled low again before any further write cycles can
take place. See Figure 12.
AD5535*
MC68HC11*
DIN
SYNC
SCK
MOSI
PC7
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD5535 to MC68HC11 Interface
05068-012
SCLK
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5535. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left-justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1 must
be pulled low to start a transfer. It is taken high and pulled low
again before any further write cycles can take place. Figure 13
shows the connection diagram.
AD5535*
PIC16C6x/7x*
SCLK
DIN
SYNC
SCK/RC3
SDI/RC4
RA1
05068-013
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD5535 to PIC16C6x/7x Interface
AD5535 to 8051
The AD5535 requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in
Mode 0. In this mode, serial data exits the 8051 through RxD,
and a shift clock is output on TxD. The SYNC signal is derived
from a port line (P1.1). Figure 14 shows how the 8051 is
connected to the AD5535. Because the AD5535 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. Note also that the
AD5535 requires its data with the MSB first. Because the 8051
outputs the LSB first, the transmit routine must take this into
account.
AD5535*
8051*
SCLK
TxD
DIN
RxD
SYNC
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD5535 to 8051 Interface
Rev. PrE | Page 12 of 16
05068-014
AD5535*
Preliminary Technical Data
AD5535
APPLICATIONS INFORMATION
REF198 +5V +210V
(4.096V)
OUTPUT RANGE
0V TO 200V
V
V
REF_IN
+
PP
MEMS MIRROR CONTROL APPLICATION
The AD5535 is targeted to all optical switching control systems
based on micro-electromechanical systems (MEMS)
technology. The AD5535 is a 32-channel, 14-bit DAC with
integrated high voltage amplifiers. The output amplifiers are
capable of generating an output range of 0 V to 200 V when
using a 4 V reference. The full-scale output voltage is
programmable from 50 V to 200 V using reference voltages
from 1 V to 4V. Each amplifier can output 700 µA and directly
drives the control actuators, which determine the position of
MEMS mirrors in optical switch applications.
SENSOR
+
4 TO 1 MUX
(ADG739)
14-BIT DAC
VO1
VO32
14-BIT DAC
ACTUATORS
FOR
MEMS
MIRROR
ARRAY
OR
32 TO 1 MUX
(ADG732)
AD5535
8-CHANNEL
ADC (AD7856)
OR
SINGLE
CHANNEL
ADC (AD7671)
V–
05068-015
–5V
ADSP21065L
The AD5535 is generally used in a closed-loop feedback system,
as shown in Figure 15, with a high resolution ADC and DSP.
The exact position of each mirror is measured using capacitive
sensors. The sensor outputs are multiplexed using an ADG739
to an 8-channel 14-bit ADC (AD7856). An alternative solution
is to multiplex using a 32-to-1 multiplexer (ADG732) into a
single-channel ADC (AD7671). The control loop is driven by an
ADSP-21065L, a 32-bit SHARC DSP with an SPI-compatible
SPORT interface. With its 14-bit monotonic behavior and 0 V to
200 V output range coupled with its fast serial interface, the
AD5535 is ideally suited for controlling a cluster of MEMSbased mirrors.
Figure 15. AD5535 in a MEMS-Based Optical Switch
AD5535 BOARD LAYOUT TO ENSURE
COMPLIANCE WITH IPC-221 SPECIFICATION
The diagram in Figure 16 is a typical 2-layer printed circuit
board layout for the AD5535 complying with the specifications
outlined in IPC221. The four corner balls labeled as original noconnects must remain, because no connections and no signals
should be connected to these balls. Balls labeled as additional
no-connects should be connected to AGND.
The routing shown in Figure 16 shows the feasibility of
connecting to the high voltage balls while complying with the
spacing requirements of IPC-221. Figure 17 shows the physical
distances that are available.
A1 BALL PAD CORNER
1 2 3 4
5 6
7 8 9 10 11 12 13 14
C
D
ORIGINAL
NO-CONNECTS
E
F
G
ADDITIONAL
NO-CONNECTS
J
H
1.414mm
m
m
5µ
5µ
D
40 AD
40
A
=
=
R
R
E
E
m
C
C µm
A
A
0
0µ
25
SP µm SP 25
0
10
A
B
DETAIL A
250µm RAD
SPACE = 433µm
100µm
K
L
1
1
100µm
M
N
SPACE = 433µm
P
250µm RAD
1
Figure 16. Layout Guidelines to Comply with IPC-221
Rev. PrE | Page 13 of 16
2mm
SPACE = 433µm
05068-016
1
AD5535
Preliminary Technical Data
POWER SUPPLY SEQUENCING AND DECOUPLING
RECOMMENDATIONS
The diagram in Figure 17 shows the recommended decoupling,
and power supply protection for the AD5535. On the AD5535 it
is recommended that all grounds be tied together as close to the
device as possible. All supplies should be brought back
separately and a provision be made on the board via a link
option to drive the AVCC and V+ from the same supply if
required to reduce the number of supplies. All power supplies
should be adequately decoupled with 10 uF tantalum and 0.1 uF
ceramic capacitors. Note that the capacitors on the VPP supply
must be rated at greater than 210 V. To overcome issues
associated with power supply sequencing when using high
voltage supplies, the use of protection diodes as indicated in
Figure 17 is recommended.
V– = –5V V+ = +5V VPP = +210V
10µF
10µF
SCHOTTKY DIODE
MFTR: ITT
HIGH VOLTAGE DIODE
MFTR: GS
0.1µF
0.1µF
SD103C
PGND
RS1G
V–
V+
10µF
0.1µF
VPP
AGND
AVCC
DACGND
10µF
AVCC = +5V
0.1µF
AD5535
DGND
10µF
DVCC = +5V
0.1µF
05068-017
DVCC
Figure 17. Recommended Power Supply Sequencing and Decoupling
GUIDELINES FOR PRINTED CIRCUIT BOARD
LAYOUT
Printed circuit boards should be designed such that the analog
and digital sections are separated and confined to designated
analog and digital sections of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally found to be the best for ground planes,
because this optimizes shielding of sensitive signal lines. Digital
and analog grounds planes should be joined only in one place,
at the AGND and DGND pins of the high resolution converter.
Data and address busses on the board should be buffered or
latched to isolate the high frequency bus of the processor from
the bus of the high-resolution converters. These act as a faraday
shield and increase the signal-to-noise performance of the
converters by reducing the amount of high frequency digital
coupling. Avoid running digital lines under the device, because
they couple noise onto the die. The ground plane should be
allowed to run under the IC to avoid noise coupling.
As large a trace as possible should be used for the supply lines to
the device to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to
avoid radiating noise to other sections of the board, and clock
signals should never be run near analog inputs of devices. Avoid
crossovers of digital and analog signals. Traces for analog inputs
should be kept as wide and as short as possible and should be
shielded with analog ground where possible. Traces on opposite
sides of a 2-layer printed circuit board should run at right
angles to each other to reduce the effects of feedthrough
through the board.
A microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique the component
side of the board is dedicated to ground planes, and signals are
placed on the solder side. Multilayer printed circuit boards with
dedicated ground, power, and tracking layers offer the optimum
solution in terms of obtaining analog performance but at
increased manufacturing costs.
Good decoupling is vitally important when using high resolution converters. All analog supplies should be decoupled with
10 µF tantalum in parallel with 0.1 µF ceramic capacitors to
analog ground. To achieve the best from the decoupling
components, these have to be placed as close to the device as
possible ideally right up against the IC or IC socket. The main
aim of a bypassing element is to maximize the charge stored in
the bypass loop while simultaneously minimizing the
inductance of this loop. Inductance in the loop acts as an
impedance to high frequency transients and results in power
supply spiking. By keeping the decoupling as close to the device
as possible, the loop area is kept as small as possible, thereby
reducing the possibility of power-supply spikes. Digital supplies
of high resolution converters should be decoupled with 10 µF
tantalum and 0.1 µF ceramic to the digital ground plane. VDD
and VSS supplies of amplifiers should be decoupled again with
10 µF and 0.1 µF to AGND.
All logic chips should be decoupled with 0.1µF to digital
ground to decouple high frequency effects associated with
digital circuitry.
Rev. PrE | Page 14 of 16
Preliminary Technical Data
AD5535
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
15.00
BSC SQ
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
TOP VIEW
1.00 BSC
BOTTOM VIEW
DETAIL A
1.70 MAX
DETAIL A
*1.25 MAX
0.85 MIN
*0.41
*COMPLIANT WITH JEDEC STANDARDS
MO-192-AAE-1 EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL. NOMINAL BALL
SIZE IS REDUCED FROM 0.60mm TO 0.46mm.
0.36
0.31
SEATING
PLANE
*0.46 NOM
0.12 NOM
COPLANARITY
BALL DIAMETER
Figure 18. 124-Lead CSB-BGA Package [CSP-BGA]
(BC-124)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5535ABC
Function
32 DACs
Output Voltage Span
0 to 200 V maximum
Temperature Range
−10°C to +85°C
Rev. PrE | Page 15 of 16
Package Description
124-Lead CSP-BGA
Package Option
BC-124
AD5535
Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05068–0–10/04(PrE)
Rev. PrE | Page 16 of 16
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