TI1 DRV632PWR Audio line driver with adjustable gain Datasheet

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DRV632
SLOS681B – JANUARY 2011 – REVISED AUGUST 2015
DRV632 DirectPath™, 2-VRMS Audio Line Driver With Adjustable Gain
1 Features
3 Description
•
The DRV632 is a 2-VRMS pop-free stereo line driver
designed to allow the removal of the output dcblocking capacitors for reduced component count and
cost. The device is ideal for single-supply electronics
where size and cost are critical design parameters.
1
•
•
•
•
•
•
•
•
•
•
•
•
Stereo DirectPath™ Audio Line Driver
– 2 Vrms Into 10 kΩ With 3.3-V Supply
Low THD+N < 0.01% at 2 Vrms Into 10 kΩ
High SNR, >90 dB
600-Ω Output Load Compliant
Differential Input and Single-Ended Output
Adjustable Gain by External Gain-Setting
Resistors
Low DC Offset, <1 mV
Ground-Referenced Outputs Eliminate DCBlocking Capacitors
– Reduce Board Area
– Reduce Component Cost
– Improve THD+N Performance
– No Degradation of Low-Frequency Response
Due to Output Capacitors
Short-Circuit Protection
Click- and Pop-Reduction Circuitry
External Undervoltage Mute
Active Mute Control for Pop-Free Audio On/Off
Control
Space-Saving TSSOP Package
Using the DRV632 in audio products can reduce
component count considerably compared to
traditional methods of generating a 2-VRMS output.
The DRV632 does not require a power supply greater
than 3.3 V to generate its 5.6-Vpp output, nor does it
require a split-rail power supply. The DRV632
integrates its own charge pump to generate a
negative supply rail that provides a clean, pop-free
ground-biased 2-VRMS output.
The DRV632 is available in a 14-pin TSSOP.
2 Applications
•
•
•
•
•
•
Designed
using
TI’s
patented
DirectPath™
technology, The DRV632 is capable of driving 2 VRMS
into a 10-kΩ load with 3.3-V supply voltage. The
device has differential inputs and uses external gainsetting resistors to support a gain range of ±1 V/V to
±10 V/V, and gain can be configured individually for
each channel. Line outputs have ±8-kV IEC ESD
protection, requiring just a simple resistor-capacitor
ESD protection circuit. The DRV632 has built-in
active-mute control for pop-free audio on/off control.
The DRV632 has an external undervoltage detector
that mutes the output when the power supply is
removed, ensuring a pop-free shutdown.
Set-Top Boxes
Blu-ray Disc™, DVD Players
LCD and PDP TV
Mini/Micro Combo Systems
Sound Cards
Laptops
Device Information(1)
PART NUMBER
DRV632
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Diagram
±
RIGHT
DAC
+
DRV632
+
LEFT
DAC
±
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV632
SLOS681B – JANUARY 2011 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
5
5
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 14
12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
12.2 Layout Example .................................................... 15
13 Device and Documentation Support ................. 16
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
14 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2013) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added Device Comparison table. .......................................................................................................................................... 3
Changes from Original (January 2011) to Revision A
Page
•
Changed description of UVP in PIN FUNCTIONS table ........................................................................................................ 4
•
Deleted min value for SNR and DNR in OPERATING CHARACTERISTICS table ............................................................... 6
2
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5 Device Comparison Table
DEVICE
INPUT OFFSET (±µV)
OUTPUT VOLTAGE (TYP) (VRMS)
MINIMUM LOAD
IMPEDANCE (Ω)
DRV632
1000
2.4
600
DRV612
1000
2.2
600
DRV604
500
2.1
1000 (line output) / 8
(headphone output)
DRV603
1000
2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V)
600
DRV602
5000
2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V)
600
DRV601
8000
2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V)
100
DRV600
8000
2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V)
100
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6 Pin Configuration and Functions
PW Package
14-Pin TSSOP
(Top View)
+INR
1
14
+INL
–INR
2
13
–INL
OUTR
3
12
OUTL
11
UVP
External
UnderVoltage
Detector
GND
4
Mute
5
10
GND
VSS
6
9
VDD
CN
7
8
CP
Charge Pump
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
CN
7
I/O
Charge-pump flying capacitor negative connection
CP
8
I/O
Charge-pump flying capacitor positive connection
GND
4, 10
P
Ground
–INL
13
I
Left-channel OPAMP negative input
+INL
14
I
Left-channel OPAMP positive input
–INR
2
I
Right-channel OPAMP negative input
+INR
1
I
Right-channel OPAMP positive input
Mute
5
I
Mute, active-low
OUTL
12
O
Left-channel OPAMP output
OUTR
3
O
Right-channel OPAMP output
UVP
11
I
Undervoltage protection, internal pullup; unconnected if UVP function is unused.
VDD
9
P
Positive supply
VSS
6
P
Supply voltage
(1)
I = input, O = output, P = power
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range
(1)
Supply voltage, VDD to GND
VI
Input voltage
RL
Minimum load impedance – line outputs – OUTL, OUTR
MIN
MAX
UNIT
–0.3
4
V
VSS – 0.3
VDD + 0.3
V
600
Ω
Mute to GND, UVP to GND
–0.3
VDD + 0.3
V
TJ
Maximum operating junction temperature
–40
150
°C
Tstg
Storage temperature
–40
150
°C
(1)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±4000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VDD
Supply voltage
RL
Load impedance
VIL
Low-level input voltage
VIH
High-level input voltage
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
0.6
10
kΩ
Mute
40
% of VDD
Mute
60
DC supply voltage
–40
UNIT
V
% of VDD
25
85
°C
7.4 Thermal Information
DRV632
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
130
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49
°C/W
RθJB
Junction-to-board thermal resistance
63
°C/W
ψJT
Junction-to-top characterization parameter
3.6
°C/W
ψJB
Junction-to-board characterization parameter
62
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDD = 3.3 V
TYP MAX
0.5
1
UNIT
|VOS|
Output offset voltage
PSRR
Power-supply rejection ratio
VOH
High-level output voltage
VDD = 3.3 V
VOL
Low-level output voltage
VDD = 3.3 V
VUVP_EX
External UVP detect voltage
VUVP_EX_HYSTERESIS
External UVP detect hysteresis current
fCP
Charge pump switching frequency
400
kHz
|IIH|
High-level input current, Mute
VDD = 3.3 V, VIH = VDD
1
µA
|IIL|
Low-level input current, Mute
VDD = 3.3 V, VIL = 0 V
1
µA
IDD
Supply current
80
dB
3.1
V
–3.0
5
200
VDD = 3.3 V, no load, Mute = VDD
VDD = 3.3 V, no load, Mute = GND,
disabled
5
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V
1.25
V
5
µA
300
14
25
14
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mV
mA
5
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7.6 Operating Characteristics
VDD = 3.3 V, RDL = 10 kΩ, RFB = 30 kΩ, RIN = 15 kΩ, TA = 25°C, Charge pump: CP = 1 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Output voltage, outputs in phase
THD+N = 1%, VDD = 3.3 V, f = 1 kHz, RL = 10 kΩ
THD+N
Total harmonic distortion plus noise
VO = 2 VRMS, f = 1 kHz
SNR
Signal-to-noise ratio (1)
A-weighted
105
dB
DNR
Dynamic range
A-weighted
105
dB
VN
Noise voltage
A-weighted
ZO
Output Impedance when muted
Mute = GND
Input-to-output attenuation when
muted
Mute = GND
Crosstalk—L to R, R to L
VO = 1 Vrms
(1)
6
Current limit
2.4
UNIT
VO
ILIMIT
2
TYP MAX
Vrms
0.002%
11
μV
110
mΩ
80
dB
–110
dB
25
mA
SNR is calculated relative to 2-Vrms output.
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7.7 Typical Characteristics
VDD = 3.3 V , TA = 25°C, C(PUMP) = C(VSS) = 1 µF , CIN = 2.2 µF, RIN = 15 kΩ, Rfb = 30 kΩ, ROUT = 32 Ω, COUT = 1 nF (unless
otherwise noted)
10
10
Active Filter
Gain = 2V/V
RL = 600Ω
1
1
0.1
0.1
THD+N (%)
THD+N (%)
Active Filter
Gain = 2V/V
RL = 10 kΩ
0.01
0.01
0.001
0.001
100 Hz
1 kHz
10 kHz
100 Hz
1 kHz
10 kHz
0.0001
0.1
1
0.0001
0.1
3
1
3
Output Voltage (V)
Output Voltage (V)
Figure 1. Total Harmonic Distortion and Noise vs Output
Voltage
Figure 2. Total Harmonic Distortion and Noise vs Output
Voltage
10
10
Active Filter
Gain = 2V/V
RL = 600 Ω
Ch1 1 Vrms
Ch1 2 Vrms
1
1
0.1
0.1
THD+N (%)
THD+N (%)
Active Filter
Gain = 2V/V
RL = 10 kΩ
0.01
0.01
0.001
0.0001
Ch1 1 Vrms
Ch1 2 Vrms
0.001
20
100
1k
Frequency (Hz)
10k
0.0001
20k
Figure 3. Total Harmonic Distortion and Noise vs Frequency
20
100
1k
Frequency (Hz)
10k
20k
Figure 4. Total Harmonic Distortion and Noise vs Frequency
0
RL = 10 kΩ
VO = 1 Vrms
VREF = 1 V
−20
Left to Right
Right to Left
Crosstalk (dBrA)
−40
−60
−80
−100
−120
−140
20
100
1k
Frequency (Hz)
10k
20k
Figure 5. Crosstalk vs Frequency
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications.
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9 Detailed Description
9.1 Overview
Combining the TI's patented DirectPath technology with the built-in click and pop reduction circuit, the DRV632 is
a 2-VRMS pop-free stereo line driver designed to avoid the use of the output DC-blocking capacitors, resulting in
reduced component count and cost. The DRV632 is capable of driving 2-VRMS into a line load of 600 Ω to 10
kΩ with a 3.3-V supply voltage. The use of charge-pump flying, PVSS, and decoupling capacitors ensure the
performance of the amplifier. The device has two channels with differential inputs that require DC input-blocking
capacitors to block the DC portion of the audio source. These allow the DRV632 inputs to be properly biased to
provide maximum performance. The DRV632 allows external gain-setting resistors to support a gain range of ±1
V/V to ±10 V/V. The gain can be configured individually for each channel. Additionally, both channels can be
used as a second-order filter when the removal of out-of-band noise is required. The DRV632 has a built-in
active-mute control for pop-free audio on/off, and avoids the click and pop generation by using external
undervoltage detection. The device does not generate a pop or click when the power supply is removed or
placed.
9.2 Functional Block Diagram
+INL
–INL
+INR
Line
Driver
Line
Driver
OUTL
OUTR
UVP
GND
Click and Pop
Suppression
Short-Circuit
Protection
GND
Mute
VSS
Bias
Circuitry
CN
8
–INR
VDD
CP
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9.3 Feature Description
9.3.1 Line Driver Amplifiers
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 6 illustrates
the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often
large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors
to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor
(CO), and the cutoff frequency (fC).
1
fc =
2p R L CO
(1)
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.
1
CO =
2p R L f c
(2)
If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
9 V–12 V
Conventional Solution
VDD
+
+
OPAMP
Mute Circuit
Co
+
Output
VDD/2
–
GND
Enable
3.3 V
DirectPath
DRV632 Solution
VDD
Mute Circuit
+
DRV632
Output
GND
–
VSS
Enable
Figure 6. Conventional and DirectPath Line Drivers
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the
IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero
volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop
reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram
and waveform of Figure 6 illustrate the ground-referenced line-driver architecture. This is the architecture of the
DRV632.
9.3.2 Charge-Pump Flying Capacitor and PVSS Capacitor
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are
smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications. If the DRV632 is used in highly noise-sensitive circuits, TI recommends adding a small
LC filter on the VDD connection.
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Feature Description (continued)
9.3.3 Decoupling Capacitors
The DRV632 is a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV632 is important for the performance of the amplifier. For filtering lower-frequency
noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
9.3.4 Gain-Setting Resistor Ranges
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
DRV632 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different invertinginput gain settings.
Table 1. Recommended Resistor Values
GAIN
INPUT RESISTOR VALUE, RIN
FEEDBACK RESISTOR VALUE, Rfb
–1 V/V
10 kΩ
10 kΩ
–1.5 V/V
8.2 kΩ
12 kΩ
–2 V/V
15 kΩ
30 kΩ
–10 V/V
4.7 kΩ
47 kΩ
9.3.5 Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV632. These capacitors block the dc portion of the audio source and allow the DRV632 inputs to be properly
biased to provide maximum performance.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 3. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the
input resistor chosen from Table 1; then the frequency and/or capacitance can be determined when one of the
two values is given.
It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to
ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is
commonly seen in ceramic capacitors and can increase low-frequency audio distortion.
1
1
fcIN =
or
CIN =
2p R INCIN
2p fcIN R IN
(3)
9.3.6 DRV632 UVP Operation
The shutdown threshold at the UVP pin is 1.25 V. The customer must use a resistor divider to obtain the
shutdown threshold and hysteresis desired for a particular application. The customer-selected thresholds can be
determined as follows:
9.3.7 External Undervoltage Detection
External undervoltage detection can be used to mute/shut down the DRV632 before an input device can
generate a pop.
The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown
threshold and hysteresis for the specific application. The thresholds can be determined as follows:
VUVP = (1.25 – 6 μA × R3) × (R1 + R2) / R2
Hysteresis = 5 μA × R3 × (R1 + R2) / R2
For example, to obtain VUVP = 3.8 V and 1-V hysteresis, use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.
10
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VSUP_MO
R1
R3
UVP
R2
Figure 7. UVP Resistor Divider
9.4 Device Functional Modes
9.4.1 Using the DRV632 as a Second-Order Filter
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the DRV632, as it can be used like a standard operational amplifier. Several filter topologies can be
implemented, both single-ended and differential. In Figure 8, multi-feedback (MFB) with differential input and
single-ended input are shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.
To calculate the component values, use the TI WEBENCH® Filter Designer (www.ti.com/filterdesigner).
Inverting Input
Differential Input
R2
C3
R1
R2
C3
C1
R3
–IN
R3
R1
C1
–IN
–
DRV632
+
C2
–
DRV632
+
C2
+IN
C3
R1
R3
C1
R2
Figure 8. Second-Order Active Low-Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a
dynamic range (DYR) of 106 dB can be achieved with a 1-μF input ac-coupling capacitor.
9.4.2 Mute Mode
The DRV632 can be muted using the low-active Mute pin (pin 5). The click-and-pop suppression capacity
ensures that when the mute mode is used, it does not generate an additional click or pop.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This typical connection diagram highlights the required external components and system-level connections for
proper operation of the device. This configuration can be realized using the Evaluation Module (EVM) of the
device. This flexible module allows full evaluation of the device in all available modes of operation. Also see the
DRV632 product page for information on ordering the EVM.
10.2 Typical Application
R1
C3
C3
R1
R2
R2
C2
R3
C3
R1
R1
C2
R3
R3
R3
+
C3
LEFT
– INPUT
+
RIGHT
– INPUT
+
C1
C1
R2
R2
DRV632
+INR
–INR
+INL
Line
Driver
Line
Driver
–INL
C1
C1
RIGHT OUTPUT
OUTR
UVP
GND
Click and Pop
Suppression
Short-Circuit
Protection
R11
GND
EN
VSS
LEFT OUTPUT
OUTL
3.3-V Supply
Bias
Circuitry
R12
VDD
1mF
1mF
CN
CP
Linear
Low-Dropout
Regulator
1mF
System Supply
10 mF
R1 = 15 kΩ, R2 = 30 kΩ, R3 = 43 kΩ, C1 = 47 pF, C2 = 180 pF
Differential-input, single-ended output, second-order filter
Figure 9. Typical Application Schematic
12
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SLOS681B – JANUARY 2011 – REVISED AUGUST 2015
Typical Application (continued)
10.2.1 Design Requirements
In this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
KEY PARAMETERS
VALUE
Supply Voltage
3.3 V
Supply Current
0.10 A
Load Impedance
600 Ω (minimum)
10.2.2 Detailed Design Procedure
10.2.2.1 Charge-Pump Flying, PVSS and Decoupling Capacitors
To transfer charge during the generation of the negative supply voltage, an 1-µF low equivalent-series-resistance
(ESR) charge-pump flying capacitor is used for this design. Similar 1-µF capacitors are placed in VSS, and as
close as possible to VDD. See Charge-Pump Flying Capacitor and PVSS Capacitor and Decoupling Capacitors
for details.
10.2.2.2 Second-Order Active Low-Pass Filters
With the help of the TI WEBENCH Filter Designer (www.ti.com/filterdesigner), the values of R1 = 15 kΩ, R2 = 30
kΩ, R3 = 43 kΩ, C1 = 47 pF, and C2 = 180 pF are proposed to design a second-order low-pass filter with a
differential-input and a single-ended output. See Using the DRV632 as a Second-Order Filter for details.
10.2.2.3 UVP Resistor Divider
R11 and R12 are placed to design a resistor divider. The shutdown threshold at the UVP pin is 1.25 V. See
External Undervoltage Detection for details.
10.2.3 Application Curves
10
10
Active Filter
Gain = 2V/V
RL = 600Ω
1
1
0.1
0.1
THD+N (%)
THD+N (%)
Active Filter
Gain = 2V/V
RL = 10 kΩ
0.01
0.01
0.001
0.001
100 Hz
1 kHz
10 kHz
100 Hz
1 kHz
10 kHz
0.0001
0.1
1
3
0.0001
0.1
1
3
Output Voltage (V)
Output Voltage (V)
Figure 10. Total Harmonic Distortion and Noise vs Output
Voltage
Figure 11. Total Harmonic Distortion and Noise vs Output
Voltage
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10
10
Active Filter
Gain = 2V/V
RL = 600 Ω
Ch1 1 Vrms
Ch1 2 Vrms
1
1
0.1
0.1
THD+N (%)
THD+N (%)
Active Filter
Gain = 2V/V
RL = 10 kΩ
0.01
0.01
0.001
0.0001
Ch1 1 Vrms
Ch1 2 Vrms
0.001
20
100
1k
Frequency (Hz)
10k
0.0001
20k
Figure 12. Total Harmonic Distortion and Noise vs
Frequency
20
100
1k
Frequency (Hz)
10k
20k
Figure 13. Total Harmonic Distortion and Noise vs
Frequency
0
RL = 10 kΩ
VO = 1 Vrms
VREF = 1 V
−20
Left to Right
Right to Left
Crosstalk (dBrA)
−40
−60
−80
−100
−120
−140
20
100
1k
Frequency (Hz)
10k
20k
Figure 14. Crosstalk vs Frequency
11 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3 V and 3.6 V. This input supply
must be well-regulated. If the input supply is located more than a few inches from the DRV632 device, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a
value of 47 µF is a typical choice.
Placing a decoupling capacitor close to the DRV632 improves the performance of the line-driver amplifier. An low
equivalent-series-resistance (ESR) ceramic capacitor with a value of 1 µF is a typical choice.
If the DRV632 is used in highly noise-sensitive circuits, TI recommends adding a small LC filter on the VDD
connection.
14
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12 Layout
12.1 Layout Guidelines
12.1.1 Gain-Setting Resistors
The gain-setting resistors, RIN and Rfb, must be placed close to pins 13 and 17, respectively, to minimize
capacitive loading on these input pins and to ensure maximum stability of the DRV632. For the recommended
PCB layout, see the DRV632EVM User's Guide.
12.2 Layout Example
LOUT
LIN(-)
UVP
Circuit
LIN(+)
RIN(+)
Decoupling
capacitor as close
as possible to the
device
Power Ground
MUTE
RIN(-)
PVSS capacitor
as close as
possible to the
device
ROUT
Pad to Ground Plane
Top Layer Signal Traces
Connection to VDD
Top Layer Ground Plane
Via to Ground Layer
Figure 15. DRV632 Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For the DRV632EVM and Gerber files, go to www.ti.com/tool/DRV632EVM.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
DirectPath, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV632PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV632
DRV632PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV632
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV632PWR
Package Package Pins
Type Drawing
TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV632PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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