FAIRCHILD FMS3815

www.fairchildsemi.com
FMS3810/3815
Triple Video D/A Converters
3 x 8 bit, 150 Ms/s
Features
Description
• 8-bit resolution
• 150 megapixels per second
– 0.2% linearity error
• Sync and blank controls
• 1.0V p-p video into 37.5Ω or 75Ω load
• Internal bandgap voltage reference
• Double-buffered data for low distortion
• TTL-compatible inputs
• Low glitch energy
• Single +5 Volt power supply
FMS3810/3815 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
FMS3810
100 Ms/s
FMS3815
150 Ms/s
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5Ω loads corresponding to doubly-terminated
50–75Ω loads. A sync current following SYNC input timing
is added to the IOG output. BLANK will override RGB
inputs, setting IOG, IOB and IOR currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the VREF input.
Applications
• Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Block Diagram
SYNC
SYNC
BLANK
G7-0
B7-0
R7-0
8
8 bit D/A
Converter
IOG
8
8 bit D/A
Converter
IOB
8
8 bit D/A
Converter
IOR
CLOCK
+1.235V
Ref
COMP
RREF
VREF
REV. 1.08 12/21/00
FMS3810/3815
PRODUCT SPECIFICATION
Functional Description
D/A Outputs
Within the FMS3810/3815 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB7-0 are overridden by the BLANK input. SYNC
= H activates, sync current from IOS for sync-on-green video
signals.
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between RREF and GND.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes tDO after the rising
edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
data: 660 mV max.
The FMS3810/3815 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
RREF should be doubled.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3KΩ source resistance. An external
voltage reference may be connected to the VREF pin,
overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
pedestal: 54 mV
Power and Ground
sync: 286 mV
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be
connected to VDD pins with 0.1 and 0.01 µF decoupling
capacitors placed adjacent to each VDD pin or pin pair.
Figure 1. Nominal Output Levels
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = H, the D/A inputs are added to a pedestal which
offsets the current output. If BLANK = L, data inputs and the
pedestal are disabled.
2
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
High slew-rate of digital data makes capacitive coupling to
the outputs of any D/A converter a potential problem. Since
the digital signals contain high-frequency components of the
CLK signal, as well as the video output signal, the resulting
data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins should
be connected to a common solid ground plane for best
performance.
REV. 1.08 12/21/00
PRODUCT SPECIFICATION
FMS3810/3815
Table 1. Output Voltage versus Input Code, SYNC and BLANK
VREF = 1.235 V, RREF = 590 Ω, RL = 37.5 Ω
Blue and Red
Green
RGB7-0 (MSB…LSB)
SYNC
BLANK
VOUT
SYNC
BLANK
VOUT
1111 1111
X
1
0.714
1
1
1.000
1111 1111
X
1
0.714
0
1
0.714
1111 1110
X
1
0.711
1
1
0.997
1111 1101
X
1
0.709
1
1
0.995
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000 0000
X
1
0.385
1
1
0.671
1111 1111
X
1
0.383
1
1
0.669
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000 0010
X
1
0.059
1
1
0.345
0000 0001
X
1
0.057
1
1
0.343
0000 0000
X
1
0.054
1
1
0.340
0000 0000
X
1
0.054
0
1
0.054
XXXX XXXX
X
0
0.000
1
0
0.286
XXXX XXXX
X
0
0.000
0
0
0.000
XXXX XXXX
X
1
valid
0
1
valid
Pin Assignments
48
47
46
45
44
43
42
41
40
39
38
37
GND
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
NC
LQFP Package
1
2
3
4
5
6
7
8
9
10
11
12
FMS3810/3815
36
35
34
33
32
31
30
29
28
27
26
25
RREF
VREF
COMP
IOR
IOG
VDD
VDD
IOB
GND
GND
CLOCK
NC
NC
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
NC
13
14
15
16
17
18
19
20
21
22
23
24
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
VDD
REV. 1.08 12/21/00
3
FMS3810/3815
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin Number
LQFP
Value
Pin Function Description
Clock and Pixel I/O
CLK
26
TTL
Clock Input. The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R7-0
G7-0
B7-0
47-40
9-2
23-16
TTL
Red, Green, and Blue Pixel Inputs. TTL-compatible RGB digital inputs
are registered on the rising edge of CLK.
SYNC
11
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on any D/A converter output
connected to IOS. SYNC is registered on the rising edge of CLK along
with pixel data and has the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should be used only
during the blanking interval. If the system does not require sync pulses,
SYNC and IOS should be connected to GND.
BLANK
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK and has the same two-pipe latency
as SYNC and Data.
33
32
29
0.714 Vp-p
Red, Green, and Blue Current Outputs. Current source outputs can
drive RS-343A/SMPTE-170M compatible levels into doubly-terminated
75 Ohm lines. Sync pulses may be added to the green output.
When SYNC is HIGH, the current added to IOG is:
Controls
Video Outputs
IOR
IOG
IOB
IOS = 3.64 (VREF / RREF)
Voltage Reference
VREF
35
+1.235 V
Voltage Reference Input/Output. Internal 1.235V voltage reference is
available on this pin. An external +1.235 Volt reference may be applied to
this pin to override the internal reference. Decoupling VREF to GND with
a 0.1µF ceramic capacitor is required.
RREF
36
590 Ω
Current-setting Resistor. Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (amps) from the
D/A converter (without sync). Sync is 0.4 IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total resistive load
(ohms) on each D/A converter. VFS is the blank to full-scale voltage.
COMP
4
34
0.1 µF
Compensation Capacitor. A 0.1 µF ceramic capacitor should be
connected between COMP and VDD to stabilize internal bias circuitry.
REV. 1.08 12/21/00
PRODUCT SPECIFICATION
FMS3810/3815
Pin Descriptions (continued)
Pin
Name
Pin Number
LQFP
Value
Pin Function Description
Power, Ground
VDD
12, 30, 31
+5 V
Power Supply.
GND
1, 14, 15, 27,
28, 38, 39, 48
0.0V
Ground.
NC
13, 24, 25, 37
—
No Connect
Equivalent Circuits
VDD
VDD
p
Digital
Input
n
p
VDD
n
OUT
GND
GND
Figure 2. Equivalent Analog Output Circuit
Figure 1. Equivalent Digital Input Circuit
VDD
p
p
RREF
VREF
GND
27012B
Figure 3. Equivalent Analog Input Circuit
REV. 1.08 12/21/00
5
PRODUCT SPECIFICATION
FMS3810/3815
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
7.0
V
-0.5
VDD + 0.5
V
-10.0
10.0
mA
-0.5
VDD + 0.5
V
Power Supply Voltage
VDD (Measured to GND)
Inputs
Applied Voltage (measured to GND)2
Forced
Current3,4
Outputs
Applied Voltage (measured to GND)2
Forced
Current3,4
-60.0
60.0
mA
unlimited
sec.
110
°C
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
Short Circuit Duration (single output in HIGH state to ground)
Temperature
Operating, Ambient
-20
Storage
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter
Min
Nom
Max
Units
VDD
Power Supply Voltage
4.75
5.0
5.25
V
fS
Conversion Rate
tPWH
CLK Pulsewidth, HIGH
FMS3810
100
Msps
FMS3815
150
Msps
FMS3810
3.1
ns
FMS3815
2.5
ns
FMS3810
3.1
ns
FMS3815
2.5
ns
FMS3810
10
ns
FMS3815
tPWL
CLK Pulsewidth, LOW
tW
CLK Pulsewidth
6.6
ns
ts
Input Data Setup Time
1.7
ns
th
Input Date Hold Time
0
ns
VREF
Reference Voltage, External
CC
Compensation Capacitor
1.0
1.235
1.5
0.1
V
µF
Ω
RL
Output Load
VIH
Input Voltage, Logic HIGH
2.0
VDD
V
VIL
Input Voltage, Logic LOW
GND
0.8
V
TA
Ambient Temperature, Still Air
0
70
°C
REV. 1.08 12/21/00
37.5
6
FMS3810/3815
PRODUCT SPECIFICATION
Electrical Characteristics
Conditions3
Parameter
IDD
Power Supply Current2
2
PD
Total Power Dissipation
RO
Output Resistance
CO
Output Capacitance
IIH
IIL
IREF
VREF Input Bias Current
VREF
Reference Voltage Output
VOC
Output Compliance
CDI
Digital Input Capacitance
Min
Typ1
Max
Units
VDD = Max
125
mA
VDD = Max
655
mW
100
kΩ
IOUT = 0mA
30
Input Current, HIGH
VDD = Max, VIN = 2.4V
-5
µA
Input Current, LOW
VDD = Max, VIN = 0.4V
5
µA
±100
µA
0
+1.5
V
4
10
pF
Typ1
Max
Units
10
15
ns
1
2
ns
0
1.235
Referred to VDD
-0.4
pF
V
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C
2. Minimum/Maximum values with VDD = Max and TA = Min
3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω
Switching Characteristics
Parameter
Conditions2
tD
Clock to Output Delay
VDD = Min
tSKEW
Output Skew
tR
Output Risetime
10% to 90% of Full Scale
3
ns
tF
Output Falltime
90% to 10% of Full Scale
3
ns
Min
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
System Performance Characteristics
Parameter
Conditions2
ELI
Integral Linearity Error
ELD
EDM
PSRR
Power Supply Rejection Ratio
Typ1
Max
Units
VDD, VREF = Nom
±0.2
±0.3
%/FS
Differential Linearity Error
VDD, VREF = Nom
±0.2
±0.3
%/FS
DAC to DAC Matching
VDD, VREF = Nom
5
10
%
0.05
%/%
Min
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
7
REV. 1.08 12/21/00
FMS3810/3815
PRODUCT SPECIFICATION
Timing Diagram
tPWL
1/fS
tPWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
tD
tSET
tF
OUTPUT
50%
Applications Information
tR
10%
2.
The power plane for the FMS3810/3815 should be
separate from that which supplies the digital circuitry.
A single power plane should be used for all of the VDD
pins. If the power supply for the FMS3810/3815 is the
same as that of the system's digital circuitry, power to
the FMS3810/3815 should be decoupled with 0.1µF and
0.01µF capacitors and isolated with a ferrite bead.
It is important that the FMS3810/3815 power supply is
well-regulated and free of high-frequency noise. Careful
power supply decoupling will ensure the highest quality
video signals at the output of the circuit. The FMS3810/3815
has separate analog and digital circuits. To keep digital
system noise from the D/A converter, it is recommended that
power supply voltages (VDD) come from the system analog
power source and all ground connections (GND) be made to
the analog ground plane. Power supply pins should be
individually decoupled at the pin.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3810/3815,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3810/3815 and its related analog circuitry can
have an adverse effect on performance.
Printed Circuit Board Layout
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Figure 4 illustrates a typical FMS3810/3815 interface
circuit. In this example, an optional 1.2 Volt bandgap
reference is connected to the VREF output, overriding the
internal voltage reference source.
Grounding
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1.
8
Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as
possible from all digital signals. The FMS3810/3815
should be located near the board edge, close to the
analog output connectors.
REV. 1.08 12/21/00
PRODUCT SPECIFICATION
FMS3810/3815
+5V
10µF
0.1µF
VDD
RED PIXEL
INPUT
R7-0
GREEN PIXEL
INPUT
G7-0
BLUE PIXEL
INPUT
B7-0
CLOCK
SYNC
BLANK
GND
Red
IOG
FMS38XX
ZO=75Ω
IOR
IOB
75Ω
75Ω
ZO=75Ω
75Ω
Blue
ZO=75Ω
75Ω
75Ω
Triple 8-bit
D/A Converter
+5V
COMP
CLK
SYNC
BLANK
75Ω
Green w/Sync
0.1µF
VREF
RREF
590Ω
3.3kΩ (not required without
external reference)
LM185-1.2
(Optional)
0.1µF
Figure 4. Typical Interface Circuit
Related Products
• FMS3110/3115 Triple 10-bit 250 Msps D/A Converters
• FMS9884A 3 x 8 bit 140 Ms/s A/D Converter
REV. 1.08 12/21/00
9
FMS3810/3815
PRODUCT SPECIFICATION
Mechanical Dimensions
48-Lead LQFP Package
Inches
Symbol
Min.
A
A1
A2
B
D/E
D1/E1
e
L
N
ND
α
ccc
Millimeters
Max.
.055
.063
.001
.005
.053
.057
.006
.010
.346
.362
.268
.284
.019 BSC
.017
.029
48
12
0°
7°
.004
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Max.
1.40
1.60
.05
.15
1.35
1.45
.17
.27
8.8
9.2
6.8
7.2
.50 BSC
.45
.75
48
12
0°
7°
0.08
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
6
4
5
8. To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E E1
C
L
α
0.063" Ref (1.60mm)
See Lead Detail
A
Base Plane
A2
B
A1
Seating Plane
-CLEAD COPLANARITY
ccc
10
C
REV. 1.08 12/21/00
FMS3810/3815
PRODUCT SPECIFICATION
Ordering Information
Product Number
Conversion
Rate
Temperature Range
Screening
Package
Package
Marking
FMS3810KRC
100 Ms/s
TA = 0°C to 70°C
Commercial
48-Lead LQFP
3810KRC
FMS3815KRC
150 Ms/s
TA = 0°C to 70°C
Commercial
48-Lead LQFP
3815KRC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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