Sony ILX522K 2048 x 2pixel ccd linear sensor (color) Datasheet

ILX522K
2048 × 2pixel CCD Linear Sensor (Color)
For the availability of this product, please contact the sales office.
Descriptions
The ILX522K is a reduction type CCD linear
sensor designed for color image scanner use. This
sensor reads B4 size documents at a density of 200
DPI. (Dot Per Inch), and has 2lines analog
memories to adjust the position of green line and
red/blue line. A built-in timing generator and clockdrivers ensure direct drive at 5V logic.
12 φV1
11 φV2
Driver
Driver
φV2 11
G2047 R1024
G2048 B1024
12 φV1
14
GND
VDD2
13
10
8
VDD1
16
φCLK
18
GND
5
Output
amplifier
13 VDD2
VDD1
14 GND
21
9
VGG 19
φROG
Output
amplifier
15 GND
4
8
VOUT-G
VDD1
Driver
16 φCLK
1
7
AA
AA
AA
φRS
NC
NC
3
17
VOUT-R/B
NC 6
GND 10
AA
AA
AA
18 GND
5
GND
D13
VDD1
20
19 VGG
VDD2
VOUT-G 4
Clock driver
Readout gate
20 VDD2
VOUT-R/B 3
2
21 GND
CCD analog shift register
22 NC
Analog memory
Analog memory
Readout gate
Clock driver
2
R1
B1
D13
VDD1
G1
G2
D32
R1
B1
1
D32
G1
G2
φRS
R1024
B1024
D33
Pin Configuration (Top View)
CCD analog shift register
V
V
G2047
G2048
D33
11
6
GND
D46
Absolute Maximum Ratings
• Supply voltage
VDD1
VDD2
VDD1
9
15
Driver
φROG
GND
Block Diagram
D46
Features
• Number of effective pixels: 2048 × 2pixels
• Pixel size
Red/Blue pixel: 14µm × 12µm (14µm pitch)
Green pixel: 14µm × 14µm (14µm pitch)
• Built-in timing generator, clock-drivers
• Ultra-low lag
• Good linearity
• High sensitivity
• Input Clock Pulse: CMOS 5V drive
22 pin DIP (Cer-DIP)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95436-PP
ILX522K
Pin Description
Pin No.
Symbol
Description
1
φRS
Clock pulse input
2
VDD1
9V power supply
3
VOUT-R/B
R/B signal out
4
VOUT-G
G signal out
5
VDD1
9V power supply
6
NC
NC
7
NC
NC
8
VDD1
9V power supply
9
φROG
Clock pulse input
10
GND
GND
11
φV2
Clock pulse input
12
φV1
Clock pulse input
13
VDD2
5V power supply
14
GND
GND
15
GND
GND
16
φCLK
Clock pulse input
17
NC
NC
18
GND
GND
19
VGG
Output gate bias
20
VDD2
5V power supply
21
GND
GND
22
NC
NC
Recommended Supply Voltage
Item
Min.
Typ.
Max.
Unit
VDD1
8.5
9.0
9.5
V
VDD2
4.75
5.0
5.25
V
Note) Rules for raising and lowering power supply voltage.
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Clock Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φRS, φCLK
CφRS, CφCLK
—
10
—
pF
Input capacity of φV1, φV2
CφV1, CφV2
—
10
—
pF
Input capacity of φROG
CφROG
—
10
—
pF
Input clock frequency
fφRS, fφCLK
—
—
3.5
MHz
–2–
ILX522K
Electrical Characteristics (Note 1)
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V fφRS = 3.5MHz Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
V/(lx · s)
Note 2
Red
RR
5.2
8.0
10.8
Green
RG
6.5
10.0
13.5
Blue
RB
2.8
4.3
5.8
Sensitivity nonuniformity
PRNU
—
5.0
15.0
%
Note 3
Saturation output voltage
VSAT
1.0
1.5
—
V
Note 4
Green
VDRK-G
—
0.3
1.5
Red/Blue
VDRK-R/B
—
1.5
9.0
Green
DSNU-G
—
0.6
3.0
mV
Note 5
Red/Blue
DSNU-R/B
—
2.0
12.0
Image lag
IL
—
0.02
—
%
Note 6
9V supply current
IVDD1
—
20
40
mA
—
5V supply current
IVDD2
—
16.0
32.0
mA
—
Total transfer efficiency
TTE
92.0
98.0
—
%
—
Output impedance
ZO
—
150
—
Ω
—
Offset level
VOS
—
5.4
—
V
Note 7
Sensitivity
Dark voltage average
Dark signal nonuniformity
Note:
1) In accordance with the given electrooptical characteristics, the black level is defined as the average of D3,
D4, to D10.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) PRNU is defined as indicated below in each color. Ray incidence conditions are the same as for Note 2.
PRNU =
(VMAX – VMIN)/2
× 100 [%]
VAVE
The maximum output of each color is set to VMAX, the minimum output to VMIN, and the average output to
VAVE.
4)
5)
6)
7)
Use below the minimum value of the saturation output voltage.
Optical signal accumulated time τint stands at 5ms.
VOUT-G = 500mV (Typ.)
VOS is defined as indicated below.
VOUT∗
AA
AAA
AA
AAA
AAAAA
VOS
GND
∗ VOUT indicates VOUT-G and VOUT-R/B.
–3–
–4–
0V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0
D1
D1
Note) φCLK, φRS pulses must have more than 2094 cycles.
VOUT-R/B
VOUT-G
φRS
φCLK
φV2
φV1
φROG
Clock Timing Chart
1
D2
D2
2
D3
D3
D12
D12
D13
D13
D14
D14
D30
D30
D31
D31
D32
G1
G2
G2046 G2047 G2048 D33
D34
D39
D32
R1
B1
B1023 R1024 B1024
D33
D34
D39
D40
D40
AA AAAAAA
AA AAAAAA
1 Line Output (2094 pixels)
Optical Black (18 pixels)
Dummy Signal (32 pixels)
3
D46
D46
2088 2094
0
ILX522K
ILX522K
φROG, φV1, φV2, φCLK Timing
t6
φROG
t7
t3
t2
t1
φV1
t4
t6
t6
t7
t3
t1
φV2
t2
t7
t5
φCLK
Item
Symbol
Min.
Typ.
Max.
Unit
φROG, φV2 – φCLK pulse timing
t1
1
2
—
µs
φROG, φV1, φV2 pulse period
t2, t4
28
30
—
µs
φROG – φV1 pulse timing
t3
1
2
—
µs
φV1 – φCLK pulse timing
t5
1
2
—
µs
φROG, φV1, φV2 pulse rise time, fall time
t6, t7
0
10
30
ns
–5–
ILX522K
φCLK, φRS, VOUT Timing
t1
φCLK
t2
φRS
t3
VOUT
AA
AA
Item
t5
AAAAA
AAAAA
t4
t6
Symbol
Min.
φCLK pulse high level period
t1
135
φRS pulse high level period
t2
30
500∗
250∗
t3
—
t4
Signal output delay time
Max.
Unit
—
ns
—
ns
60
—
ns
—
25
—
ns
t5
—
70
—
ns
t6
—
25
—
ns
∗ These timing is the condition under fφRS = 1MHz.
–6–
Typ.
10µ
16V
VOUT-R/B
0.01µ
5V
9V
φRS
74HC04
2
1
2SA1175
4
1kΩ
VOUT-G
7
6
9
φROG
74HC04
8
11
φV2
74HC04
10
0.01µ
10µ
10V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2SA1175
3
5
12
13
14
15
16
17
18
19
20
21
10µ
16V
22
1kΩ
0.01µ
74HC04
φV1
NC
74HC04
φCLK
GND
φRS
VDD2
VDD1
VGG
VOUT-R/B
GND
VOUT-G
NC
VDD1
φCLK
VDD1
GND
φROG
GND
GND
VDD2
φV2
φV1
NC
–7–
NC
Application Circuit
ILX522K
ILX522K
Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.6
0.4
0.2
0
400
450
500
550
600
650
Wave length [nm]
Dark signal output temperature characteristics
(Standard characteristics)
10
Output voltage rate
5
1
0.5
0.1
0
10
20
30
40
50
60
Ta – Ambient temperature [°C]
Integration time output voltage characteristics
(Standard characteristics)
Output voltage rate
Relative sensitivity
0.8
1
0.5
0.1
1
5
τint – integration time [ms]
–8–
10
700
ILX522K
Operational frequency characteristics of the VDD1
supply current (Standard characteristics)
Operational frequency characteristics of the VDD2
supply current (Standard characteristics)
40
20
Ta = 25°C
IVDD2 – VDD2 supply current [mA]
IVDD1 – VDD1 supply current [mA]
Ta = 25°C
30
20
10
15
10
5
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
fφCLK – φCLK clock frequency [MHz]
Offset level vs. VDD1 characteristics
(Standard characteristics)
Offset level vs. VDD2 characteristics
(Standard characteristics)
3.5
9
8
8
Ta = 25°C
Ta = 25°C
7
VOS – Offset level [V]
7
6
5
4
3
∆VOS
∆VDD2
2
6
5
4
3
0.54
2
1
1
9.0
0
4.75
9.5
5
VDD1 [V]
VDD2 [V]
Offset level vs. Temperature characteristics
(Standard characteristics)
8
VOS – Offset level [V]
VOS – Offset level [V]
3.0
fφCLK – φCLK clock frequency [MHz]
9
0
8.5
2.5
6
4
∆VOS
∆Ta
2
–3mV/°C
0
0
10
20
30
40
50
Ta – Ambient temperature [°C]
–9–
60
5.25
ILX522K
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) lonized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-DlP Packages
The following points should be observed when handling and installing cer-DlP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1) Compressive strength: 39 N/surface (Do not apply load more than 0.7mm inside the outer
perimeter of the glass portion.)
(2) Shearing strength: 29 N/surface
(3) Tensile strength: 29 N/surface
(4) Torsional strength: 0.9 Nm
AAAAA
AAAAAAAAA
AAAA
AAAAA
AAAA
AAAAA AAAAAAAAAAAAA
Upper ceramic layer
39N
29N
29N
0.9Nm
(2)
(3)
(4)
Low-melting glass
Lower ceramic layer
(1)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating
(4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after
it has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded
30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool
sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
– 10 –
ILX522K
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to
scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
7) Since ILX522K has 2 line memory so that the signal of R/B line is delay, compese the optical system subscanning R/B line initially.
– 11 –
5.0 ± 0.5
V
H
6.26 ± 0.8
1
22
Cer-DIP
TIN PLATING
42 ALLOY
5.2g
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
2.54
40.2
11
12
0.51
22pin DIP (400mil)
28.672 (14µm × 2048Pixels)
41.6 ± 0.5
No.1 Pixel (Green)
PACKAGE STRUCTURE
4.0 ± 0.5
Unit: mm
M
9.0
0.3
10.0 ± 0.5
3.65
– 12 –
4.45 ± 0.5
Package Outline
0.25
0° to 9°
(AT STAND OFF)
10.16
2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm.
ILX522K
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