Revised April 2005 74VHC273 Octal D-Type Flip-Flop General Description Features The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High Speed: fMAX The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. ■ Low noise: VOLP 165 MHz (typ) at VCC 5V ■ Low power dissipation: ICC 4 PA (max) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs 0.9V (max) ■ Pin and function compatible with 74HC273 ■ Leadless DQFN Package An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Order Number Package Number 74VHC273M M20B 74VHC273SJ M20D 74VHC273BQ (Preliminary) MLP020B (Preliminary) 74VHC273MTC 74VHC273N MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. © 2005 Fairchild Semiconductor Corporation DS011670 www.fairchildsemi.com 74VHC273 Octal D-Type Flip-Flop April 1994 74VHC273 Logic Symbols Connection Diagrams Pin Assignments for PDIP, SOIC, SOP, and TSSOP IEEE/IEC Pad Assignments for DQFN Pin Descriptions Pin Names Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs Function Table Inputs Outputs Operating Mode MR CP Reset (Clear) L Load '1' H Load '0' H H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition X Dn Qn X L H H L L (Top Through View) Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 ns/V a 100 ns/V VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VOL TA Min 25qC Typ TA Max 40qC to 85qC Min Max 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH (V) HIGH Level Input Voltage VIL VCC Parameter 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 VIN 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Quiescent Supply Current 0.0 IOH V Voltage ICC VIH IOH 50 PA or VIL 4.4 2.0 Input Leakage Current V V LOW Level Output IIN Conditions V 3.0 5.5 HIGH Level Output Units 0.1 0.1 IOH VIN V VIH IOL 4 mA 8 mA 50 PA or VIL 3.0 0.36 0.44 4.5 0.36 0.44 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND V IOL 4 mA IOL 8 mA Noise Characteristics Symbol VOLP Parameter TA VCC 25qC Units Conditions (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 V CL 50 pF Quiet Output Minimum Dynamic VOL 5.0 0.6 0.9 V CL 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC273 Absolute Maximum Ratings(Note 1) 74VHC273 AC Electrical Characteristics Symbol fMAX VCC Parameter Maximum Clock TA Typ 3.3 r 0.3 75 120 65 50 75 45 120 165 100 80 110 70 5.0 r 0.5 Propagation Delay tPHL Time (CK - Q) 3.3 r 0.3 5.0 r 0.5 tPHL 3.3 r 0.3 Propagation Delay 40qC to 85qC TA Min Frequency tPLH 25qC (V) Time (MR - Q) 5.0 r 0.5 Max Min Max MHz 8.7 13.6 1.0 16.0 11.2 17.1 1.0 19.5 5.8 9.0 1.0 10.5 7.3 11.0 1.0 12.5 8.9 13.6 1.0 16.0 11.4 17.1 1.0 19.5 5.2 8.5 1.0 10.0 6.7 10.5 1.0 12.0 Output to 3.3 r 0.3 1.5 1.5 tOSHL Output Skew 5.0 r 0.5 1.0 1.0 CIN Input Capacitance 4.0 10.0 10.0 CPD Power Dissipation 31 ns ns ns ns ns pF pF Capacitance |tPLHmax tPLHmin|; tOSHL Conditions MHz tOSLH Note 4: Parameter guaranteed by design tOSLH Units (Note 4) VCC CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 50 pF CL 50 pF Open (Note 5) |tPHLmax tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) C PD * VCC * fIN ICC/8 (per F/F). The total CPD when n pieces of the Flip-Flop operates can be calculated by the equation: CPD (total) 22 9n. AC Operating Requirements Symbol tW(L) Parameter Minimum Pulse Width (CK) tW(H) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (MR) VCC (V) (Note 6) 25qC TA 40qC to 85qC Guaranteed Minimum 3.3 5.5 6.5 5.0 5.0 5.0 3.3 5.0 6.0 5.0 5.0 5.0 3.3 5.5 6.5 5.0 4.5 4.5 3.3 1.0 1.0 5.0 1.0 1.0 3.3 2.5 2.5 5.0 2.0 2.0 Note 6: VCC is 3.3 r 0.3V or 5.0 r 0.5V www.fairchildsemi.com TA Typ 4 Units ns ns ns ns ns Tape Format for DQFN Package Designator BQ Tape Number Cavity Section Cavities Status Cover Tape Status Leader (Start End) 125 (typ) Empty Sealed Carrier 2500/3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) REEL DIMENSIONS inches (millimeters) Tape Size 12 mm A B C D N W1 W2 13.0 0.059 0.512 0.795 7.008 0.488 0.724 (330) (1.50) (13.00) (20.20) (178) (12.4) (18.4) 5 www.fairchildsemi.com 74VHC273 Tape and Reel Specification 74VHC273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74VHC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74VHC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B (Preliminary) www.fairchildsemi.com 8 74VHC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74VHC273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10