Renesas HN58X24128FPIE Two-wire serial interface 128k eeprom (16-kword ã 8-bit) 256k eeprom (32-kword ã 8-bit) Datasheet

HN58X24128I/HN58X24256I
Two-wire serial interface
128k EEPROM (16-kword × 8-bit)
256k EEPROM (32-kword × 8-bit)
REJ03C0132-0400
Rev.4.00
Dec.14.2004
Description
HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 64-byte page programming function to make their write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as
cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology’s
sales office before using industrial applications such as automotive systems, embedded controllers,
and meters.
Features
•
•
•
•
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2CTM serial bus*1)
Clock frequency: 400 kHz
Power dissipation:
 Standby: 3 µA (max)
 Active (Read): 1 mA (max)
 Active (Write): 5 mA (max)
Automatic page write: 64-byte/page
Write cycle time: 10 ms (2.7 V to 5.5 V)/15 ms (1.8 V to 2.7 V)
Endurance: 105 Cycles (Page write mode)
Data retention: 10 Years
Rev.4.00, Dec.14.2004, page 1 of 20
HN58X24128I/HN58X24256I
• Small size packages: SOP-8pin, TSSOP-14pin
• Shipping tape and reel
 TSSOP 14-pin: 2,000 IC/reel
 SOP 8-pin: 2,500 IC/reel
• Temperature range: −40 to +85°C
• Lead free products.
Note: 1. I2C is a trademark of Philips Corporation.
Ordering Information
Type No.
Internal organization Operating voltage
HN58X24128FPIE 128k bit
(16384 × 8-bit)
1.8 V to 5.5 V
Frequency
Package
400 kHz
150 mil 8-pin plastic SOP
(FP-8DBV)
HN58X24256FPIE 256k bit
(32768 × 8-bit)
HN58X24128TIE
128k bit
(16384 × 8-bit)
HN58X24256TIE
256k bit
(32768 × 8-bit)
Lead free
1.8 V to 5.5 V
400 kHz
14-pin plastic TSSOP
(TTP-14DBV)
Lead free
Pin Arrangement
8-pin SOP
14-pin TSSOP
A0
1
8
VCC
A0
1
14
VCC
A1
2
7
WP
A1
2
13
WP
A2
3
6
SCL
NC
3
12
NC
VSS
4
NC
4
11
NC
NC
5
10
NC
A2
6
9
SCL
VSS
7
8
SDA
5
(Top view)
SDA
(Top view)
Rev.4.00, Dec.14.2004, page 2 of 20
HN58X24128I/HN58X24256I
Pin Description
Pin name
Function
A0 to A2
Device address
SCL
Serial clock input
SDA
Serial data input/output
WP
Write protect
VCC
Power supply
VSS
Ground
NC
No connection
Block Diagram
High voltage generator
Control
logic
A0, A1, A2
SCL
X decoder
WP
Address generator
VSS
Memory array
Y decoder
VCC
Y-select & Sense amp.
SDA
Serial-parallel converter
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
−0.6 to +7.0
V
Input voltage relative to VSS
Vin
−0.5*2 to +7.0*3
V
Operating temperature range*1
Topr
−40 to +85
°C
Storage temperature range
Tstg
−65 to +125
°C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
Rev.4.00, Dec.14.2004, page 3 of 20
Unit
HN58X24128I/HN58X24256I
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
1.8

5.5
V
VSS
0
0
0
V
Input high voltage
VIH
VCC × 0.7

VCC + 1.0
V
Input low voltage
VIL
−0.3*1

VCC × 0.3
V
Operating temperature
Topr
−40

+85
°C
Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns.
DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Input leakage current
ILI


2.0
µA
VCC = 5.5 V, Vin = 0 to 5.5 V
Output leakage current
ILO


2.0
µA
VCC = 5.5 V, Vout = 0 to 5.5 V
Standby VCC current
ISB

1.0
3.0
µA
Vin = VSS or VCC
Read VCC current
ICC1


1.0
mA
VCC = 5.5 V, Read at 400 kHz
Write VCC current
ICC2


5.0
mA
VCC = 5.5 V, Write at 400 kHz
Output low voltage
VOL2


0.4
V
VCC = 4.5 to 5.5 V, IOL = 1.6 mA
VCC = 2.7 to 4.5 V, IOL = 0.8 mA
VCC = 1.8 to 2.7 V, IOL = 0.4 mA
VOL1


0.2
V
VCC = 1.8 to 2.7 V, IOL = 0.2 mA
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Min
Typ
Max
Unit
Test
conditions
1


6.0
pF
Vin = 0 V
1


6.0
pF
Vout = 0 V
Symbol
Input capacitance (A0 to A2, SCL, WP) Cin*
Output capacitance (SDA)
Note:
CI/O*
1. This parameter is sampled and not 100% tested.
Rev.4.00, Dec.14.2004, page 4 of 20
HN58X24128I/HN58X24256I
AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V)
Test Conditions
• Input pules levels:
 VIL = 0.2 × VCC
 VIH = 0.8 × VCC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × VCC
• Output load: TTL Gate + 100 pF
Parameter
Symbol
Min
Typ
Max
Unit
Clock frequency
fSCL


400
kHz
Clock pulse width low
tLOW
1200


ns
Clock pulse width high
tHIGH
600


ns
Noise suppression time
tI


50
ns
Access time
tAA
100

900
ns
Bus free time for next mode
tBUF
1200


ns
Start hold time
tHD.STA
600


ns
Start setup time
tSU.STA
600


ns
Data in hold time
tHD.DAT
0


ns
Data in setup time
tSU.DAT
100


ns
Input rise time
tR


300
ns
1
Input fall time
tF


300
ns
1
Stop setup time
tSU.STO
600


ns
Data out hold time
tDH
50


ns
VCC = 2.7 V to 5.5 V
tWC


10
ms
2
VCC = 1.8 V to 2.7 V
tWC


15
ms
2
Write cycle time
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
Rev.4.00, Dec.14.2004, page 5 of 20
Notes
1
HN58X24128I/HN58X24256I
Timing Waveforms
Bus Timing
tF
tHIGH
1/fSCL
tLOW
tR
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
Write data
(Address (n))
ACK
Rev.4.00, Dec.14.2004, page 6 of 20
tWC
(Internally controlled)
HN58X24128I/HN58X24256I
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is
400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and
the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later,
the SDA transition needs to be completed during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Note:
Data
change
High-to-low and low-to-high change of SDA should be done during the SCL low period.
Rev.4.00, Dec.14.2004, page 7 of 20
HN58X24128I/HN58X24256I
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to VCC or VSS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated.
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2
1
A1
A0
128k bit
8
VCC/VSS*
VCC/VSS
VCC/VSS
256k bit
8
VCC/VSS
VCC/VSS
VCC/VSS
Note:
Note
1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin
status
128k bit
256k bit
VIH
Upper 1/8 (16k bit)
Upper 1/8 (32k bit)
VIL
Normal read/write operation
Rev.4.00, Dec.14.2004, page 8 of 20
HN58X24128I/HN58X24256I
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation
(See start condition and stop condition).
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts
after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the
write data inputs and place the device in a internally-timed write cycle to the memories. After the
internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle
timing).
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Rev.4.00, Dec.14.2004, page 9 of 20
Stop condition
HN58X24128I/HN58X24256I
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero
to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter
keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation,
EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM
sends a zero to acknowledge after receiving the device address word. After sending read data, the
EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge,
it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment)
and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM
receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending
read data.
Acknowledge Timing Waveform
SCL
1
SDA IN
SDA OUT
Rev.4.00, Dec.14.2004, page 10 of 20
2
8
9
Acknowledge
out
HN58X24128I/HN58X24256I
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed
by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device
out of all devices which are connected to the bus. This means that the device is selected if the inputted 3bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the
device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read
operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters
the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by
state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond
hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
128k, 256k
Note:
1
0
R/W code*1
Device address code
1
0
1. R/W=“1” is read and R/W = “0” is write.
Rev.4.00, Dec.14.2004, page 11 of 20
A2
A1
A0
R/W
HN58X24128I/HN58X24256I
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends
acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2
sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs
acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM
outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle.
The EEPROM returns to a standby mode after completion of the write cycle.
Start
1010
W
2nd Memory
address (n)
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
128k to 256k
1st Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
Device
address
*1
a14 *2
a13
a12
a11
a10
a9
a8
Byte Write Operation
ACK
R/W
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
Rev.4.00, Dec.14.2004, page 12 of 20
ACK
ACK
Stop
HN58X24128I/HN58X24256I
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for
inputting the more write data. The page write is initiated by a start condition, device address word,
memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop
condition. The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The
EEPROM can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last
address of the page, the a0 to a5 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving
write data and enters internally-timed write cycle.
Page Write Operation
ACK
R/W
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
Rev.4.00, Dec.14.2004, page 13 of 20
ACK
ACK
Write data (n+m)
D5
D4
D3
D2
D1
D0
W
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
Start
1010
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
128k to
256k
1st Memory
address (n)
*1
a14 *2
a13
a12
a11
a10
a9
a8
Device
address
ACK
ACK
Stop
HN58X24128I/HN58X24256I
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.
This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device
address word following the start condition during a internally-timed write cycle. Acknowledge polling
will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM
is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has
completed. See Write Cycle Polling using ACK.
Write Cycle Polling Using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
ACK
returned
No
Yes
Next operation is
addressing the memory
No
Yes
Proceed write operation
Send
memory address
Send
start condition
Proceed random address
read operation
Send
stop condition
Rev.4.00, Dec.14.2004, page 14 of 20
Send
stop condition
HN58X24128I/HN58X24256I
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations
are initiated the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation,
with incremented by one. Current address read accesses the address kept by the internal address counter.
After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit
current address data from the most significant bit following acknowledgment “0”. If the EEPROM
receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops
the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of
the last page at previous read operation, the current address will roll over and returns to zero address. In
case the EEPROM has accessed the last address of the page at previous write operation, the current address
will roll over within page addressing and returns to the first address in the same page. The current address
is valid while power is on. The current address after power on will be indefinite. The random read
operation described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Start
Rev.4.00, Dec.14.2004, page 15 of 20
1010
R
D7
D6
D5
D4
D3
D2
D1
D0
128k to 256k
Read data (n+1)
ACK
R/W
No ACK
Stop
HN58X24128I/HN58X24256I
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read
address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 ×
8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters
a current address read with receiving a start condition. The EEPROM outputs the read data of the address
which was defined in the dummy write operation. After receiving acknowledgment “1”(no
acknowledgment) and a following stop condition, the EEPROM stops the random read operation and
returns to a standby state.
Random Read Operation
Start
W
ACK
R/W
ACK
Device
address
1010
Start
ACK
Dummy write
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
3. 2nd device address code (#) should be same as 1st (@).
Rev.4.00, Dec.14.2004, page 16 of 20
Read data (n)
# # #
R
R/W
ACK
D7
D6
D5
D4
D3
D2
D1
D0
1010
@@@
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
128k to
256k
1st Memory
address (n)
*1
a14 *2
a13
a12
a11
a10
a9
a8
Device
address
No ACK
Stop
Currect address read
HN58X24128I/HN58X24256I
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are
coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The
address will roll over and returns address zero if it reaches the last address of the last page. The sequential
read can be continued after roll over. The sequential read is terminated if the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition.
Sequential Read Operation
ACK
R/W
Rev.4.00, Dec.14.2004, page 17 of 20
ACK
ACK
ACK
D5
D4
D3
D2
D1
D0
R
Read data (n+1) Read data (n+2) Read data (n+m)
D7
D6
D5
D4
D3
D2
D1
D0
Start
1010
Read data (n)
D7
D6
D5
D4
D3
D2
D1
D0
128k to
256k
D7
D6
D5
D4
D3
D2
D1
D0
Device
address
No ACK
Stop
HN58X24128I/HN58X24256I
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)
may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional
programming, this EEPROM has a power on reset function. Be careful of the notices described below in
order for the power on reset function to operate correctly.
• SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition
during VCC on/off may cause the trigger for the unintentional programming.
• VCC should be turned off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the
unintentional programming mode.
• VCC turn on speed should be longer than 10 µs.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1%
cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed
less than 104 cycles.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than
50 ns. Be careful not to allow noise of width more than 50 ns.
Rev.4.00, Dec.14.2004, page 18 of 20
HN58X24128I/HN58X24256I
Package Dimensions
HN58X24128FPIE / HN58X24256FPIE (FP-8DBV)
Unit: mm
3.90
4.89
5.15 Max
5
8
0.69 Max
*0.20 ± 0.05
4
1.73 Max
1
6.02 ± 0.18
1.06
*0.40 ± 0.05
0.114
0.14 +– 0.038
0˚ – 8˚
1.27
0.289
0.60 +– 0.194
0.10
0.25 M
*Pd Plating
Rev.4.00, Dec.14.2004, page 19 of 20
Package Code
JEDEC
JEITA
Mass (reference value)
FP-8DBV
—
—
0.08 g
HN58X24128I/HN58X24256I
HN58X24128TIE / HN58X24256TIE (TTP-14DBV)
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
*0.20 ± 0.05
1.0
0.13 M
6.40 ± 0.20
*Pd Plating
Rev.4.00, Dec.14.2004, page 20 of 20
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DBV
—
—
0.05 g
Revision History
Rev.
Date
HN58X24128I/HN24256I Data Sheet
Contents of Modification
Page
Description
1.0
Apr. 2, 1999

Initial issue
2.0
Nov. 26, 1999

1
Addition of Note
Features
Addition of contents for “Shipping tape and reel”
3.00
Oct. 23. 2003

2
4.00
Dec.14.2004
2
Change format issued by Renesas Technology Corp.
Ordering Information
Addition of HN58X24128FPIE, HN58X24256FPIE, HN58X24128TIE,
HN58X24256TIE
19-20 Package Dimensions
FP-8DB to FP-8DB, FP-8DBV
TTP-14D to TTP-14D, TTP-14DV
Ordering Information
Deletion of HN58X24128FPI, HN58X24256FPI, HN58X24128TI,
HN58X24256TI
19-20 Package Dimensions
Deletion of FP-8DB, TTP-14D
Sales Strategic Planning Div.
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Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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