Intersil CD4097BMS Cmos analog multiplexers/demultiplexer Datasheet

CD4067BMS
CD4097BMS
CMOS Analog
Multiplexers/Demultiplexers
December 1992
Features
Pinout
• High Voltage Types (20V Rating)
CD4067BMS
TOP VIEW
• CD4067BMS Single 16 Channel Multiplexer/Demultiplexer
• CD4097BMS Differential 8 Channel Multiplexer/Demultiplexer
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
Input Range for VDD - VSS = 15V
24 VDD
COMMON OUT/IN 1
7 2
23 8
• High OFF Resistance: Channel Leakage of ±10pA (typ)
at VDD - VSS = 18V
6 3
22 9
5 4
21 10
• Matched Switch Characteristics: RON = 5Ω (typ) for
VDD - VSS = 15V
4 5
20 11
3 6
19 12
• Very Low Quiescent Power Dissipation Under All Digital Control Input and Supply Conditions: 0.2µW (typ)
at VDD - VSS = 10V
2 7
18 13
1 8
17 14
0 9
16 15
• Binary Address Decoding on Chip
A 10
15 INHIBIT
B 11
14 C
VSS 12
13 D
*
• 5V, 10V and 15V Parametric Ratings
* CHANNEL
• 100% Tested for Quiescent Current at 20V
IN/OUT
*
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics
Applications
CD4097BMS
TOP VIEW
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.
COMMON X
OUT/IN 1
Description
CD4067BMS and CD4097BMS CMOS analog multiplexers/
demultiplexers* are digitally controlled analog switches having
low ON Impedance, low OFF leakage current, and internal
address decoding. In addition, the ON resistance is relatively
constant over the full input-signal range.
CHANNEL X
IN/OUT
The CD4067BMS is a 16 channel multiplexer with four binary
control inputs, A, B, C, D and an inhibit input, arranged so that
any combination of the inputs selects one switch.
24 VDD
7 2
23 0
6 3
22 1
5 4
21 2
4 5
20 3
3 6
19 4
2 7
Y CHANNEL
IN/OUT
0 9
18 5
17 COMMON Y
OUT/IN
16 6
Y CHANNEL
A 10
15 7
B 11
14 C
1 8
VSS 12
IN/OUT
13 INHIBIT
The CD4097BMS is a differential 8 channel multiplexer having
three binary control inputs A, B, C and an inhibit input. The inputs
permit selection of one of eight pairs of switches. A logic “1”
present at the inhibit input turns all channels off.
The CD4067BMS and CD4097BMS are supplied in these 24
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4067B Only
*H4V
†H6M
*H1Z
†HFN
*H4P
†H4P
†CD4097B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1
File Number
3190
Specifications CD4067BMS, CD4097BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
ON-State Resistance
RL = 10K Returned to
VDD - VSS/2
RON
VDD = 5V
VIS = VSS to VDD
VDD = 10V
VIS = VSS to VDD
VDD = 15V
VIS = VSS to VDD
N Threshold Voltage
P Threshold Voltage
Functional (Note 4)
VNTH
VPTH
F
Input Voltage Low
(Note 2)
VIL
Input Voltage High
(Note 2)
VIH
Input Voltage Low
(Note 2)
VIL
Input Voltage High
(Note 2)
VIH
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
MAX
UNITS
1
+25
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25o
C
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1
+25oC
-
1050
Ω
2
+125oC
-
1300
Ω
3
-55oC
-
800
Ω
1
+25oC
-
400
Ω
2
+125oC
-
500
Ω
3
-55oC
-
310
Ω
1
+25oC
-
240
Ω
2
+125oC
-
320
Ω
3
-55oC
-
220
Ω
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
oC
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
VDD = 5V = VIS Thru 1K
VEE = VSS
RL = 1K to VSS
|ISS| < 2µA on all
OFF Channels
VDD = 15V = VIS Thru 1K
VEE = VSS
RL = 1K to VSS
|ISS| < 2µA on all
OFF Channels
7-2
VOH > VOL <
VDD/2 VDD/2
V
Specifications CD4067BMS, CD4097BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
OFF Channel Leakage
Any Channel OFF or All
Channels OFF
(Common OUT/IN)
IOZL
CONDITIONS (NOTE 1)
VOUT = 0V
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-0.1
-
µA
2
+125oC
-1.0
-
µA
3
-55oC
-0.1
-
µA
1
+25oC
-
0.1
µA
2
+125oC
-
1.0
µA
3
-55oC
-
0.1
µA
VDD = 20V
VDD = 18V
IOZH
VOUT = VDD
LIMITS
GROUP A
SUBGROUPS
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8/3.0V, RL = 200K
VDD = 20V/18V, RL = 10K - 25K
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
(Signal In to Output)
Propagation Delay
Address or Inhibit to
Signal Out.
(Channel Turning On)
SYMBOL
TPHL
TPLH
GROUP A
SUBGROUPS TEMPERATURE
CONDITIONS
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
LIMITS
MIN
MAX
UNITS
9
+25oC
-
60
ns
10, 11
+125oC, -55oC
-
81
ns
9
+25oC
-
650
ns
-
878
ns
10, 11
+125oC,
-55oC
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Input Voltage Low
Input Voltage High
VIL
VIH
Propagation Delay
Address or Inhibit to
Signal Out.
(Channel Turning On)
TPZH
TPZL
Propagation Delay
Signal In to Output
TPHL
TPLH
VDD = VIS = 10V
VEE = VSS
RL = 1K to VSS
IIS < 2µA
ON OFF Channel
+25oC
MAX
UNITS
-
5
µA
-
150
µA
µA
-
10
+125oC
-
300
µA
-55oC, +25oC
-
10
µA
+125oC
-
600
µA
+25oC, +125oC,
-
3
V
-55oC
VDD = 15V
VDD = 15V
1, 2
1, 2
VDD = 10V
VDD = 10V
1, 2
-55oC,
MIN
VIS = VDD or
GND
7-3
1, 2
+25oC, +125oC,
-55oC
+7
-
V
1, 2, 4
+25oC
-
270
ns
1, 2, 4
+25oC
-
190
ns
1, 2, 3
+25oC
-
30
ns
1, 2, 3
+25oC
-
20
ns
Specifications CD4067BMS, CD4097BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Propagation Delay
Address or Inhibit to
Signal Out
(Channel Turning Off)
TPHZ
TPLZ
Input Capacitance
CONDITIONS
VDD = 5V
CIN
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 5
+25oC
-
440
ns
o
VDD = 10V
1, 2, 5
+25 C
-
180
ns
VDD = 15V
1, 2, 5
+25oC
-
130
ns
-
7.5
pF
Any Address or Inhibit
o
1, 2
+25 C
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
5. CL = 50pF, RL = 300Ω, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
∆VTP
Functional
F
CONDITIONS
NOTES
TEMPERATURE
VDD = 20V, VIN = VDD or GND
1, 4
+25o
VDD = 10V, ISS = -10µA
1, 4
+25oC
C
UNITS
-
25
µA
-2.8
-0.2
V
1, 4
+25 C
-
±1
V
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
TPHL
TPLH
MAX
VDD = 10V, ISS = -10µA
o
1, 4
+25 C
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
o
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
Supply Current - MSI-2
ON Resistance
SYMBOL
DELTA LIMIT
± 1.0µA
IDD
RONDEL10
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
7-4
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
Specifications CD4067BMS, CD4097BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1 Note 1
1
2 - 23
24
Static Burn-In 2 Note 1
1
12
2 - 11, 13 - 24
Dynamic Burn-In Note 1
-
12, 15
24
Irradiation Note 2
1
12
2 - 11, 13 - 24
Static Burn-In 1 Note 1
1, 17
2 - 16, 18 - 23
24
Static Burn-In 2 Note 1
1, 17
12
2 - 11, 13 - 16,
18 - 24
Dynamic Burn-In Note 1
-
12, 13
24
1, 17
12
2 - 11, 13 - 16,
18 - 24
9V ± -0.5V
50kHz
25kHz
1
2 - 9, 16 - 23
10, 11, 13, 14
(Note 3)
1, 17
2 - 9, 15, 16,
18 - 23
10, 11, 14
(Note 4)
PART NUMBER CD4067BMS
PART NUMBER CD4097BMS
Irradiation Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 13 is at 1.7kHz, Pin 14 is at 3.5kHz
4. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 14 is at 3.5kHZ
7-5
CD4067BMS, CD4097BMS
Functional Diagram
INHIBIT
1 of 8 DECODERS
3
INHIBIT
1 of 16 DECODERS
4
0
X
OUT/IN
1
X
IN/OUT
0
1
OUT/IN
7
VDD = 24
VSS = 12
IN/OUT
15
VDD = 24
VSS = 12
0
Y
OUT/IN
1
Y
IN/OUT
7
CD4067
CD4097
CD4067 TRUTH TABLE
CD4097 TRUTH TABLE
A
B
C
D
Inh
SELECTED
CHANNEL
A
B
C
Inh
X
X
X
X
1
None
X
X
X
1
None
0
0
0
0
0
0
0
0
0
0
0X, 0Y
1
0
0
0
0
1
1
0
0
0
1X, 1Y
0
1
0
0
0
2
0
1
0
0
2X, 2Y
1
1
0
0
0
3
1
1
0
0
3X, 3Y
0
0
1
0
0
4
0
0
1
0
4X, 4Y
1
0
1
0
0
5
1
0
1
0
5X, 5Y
0
1
1
0
0
6
0
1
1
0
6X, 6Y
1
1
1
0
0
7
1
1
1
0
7X, 7Y
0
0
0
1
0
8
1
0
0
1
0
9
0
1
0
1
0
10
1
1
0
1
0
11
0
0
1
1
0
12
1
0
1
1
0
13
0
1
1
1
0
14
1
1
1
1
0
15
SELECTED
CHANNEL
tf = 20ns
tr = 20ns
90%
90%
50%
50%
10%
10%
TURN-ON
TIME
tPZL
90%
50%
10%
10%
TURN-OFF TIME
tPLZ
FIGURE 1. WAVEFORM CHANNEL BEING TURNED ON, OFF
tr = 20ns
90%
tf = 20ns
90%
50%
50%
10%
10%
90%
tPHZ
TURN-OFF TIME
10%
TURN-ON
TIME tPZH
FIGURE 2. PROPAGATION DELAY WAVEFORM, CHANNEL
BEING TURNED OFF, ON
7-6
CD4067BMS, CD4097BMS
16
CHANNEL IN/OUT
VDD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
24
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
TG
TG
TG
TG
TG
*
A
*
11
B
*
14
C
*
13
*
15
D
INHIBIT
BINARY 1 OF 16 DECODERS WITH INHIBIT
TG
10
TG
TG
1
TG
TG
TG
TG
TG
TG
TG
TG
VDD
*ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
12
VSS
VSS
FIGURE 3. CD4067BMS LOGIC DIAGRAM
7-7
COMMON
OUT/IN
CD4067BMS, CD4097BMS
VDD
7
6
5
24
15
16
18
8
CHANNEL
IN/OUT Y
4
3
19
20
2
1
0
7
6
5
21
22
23
2
3
4
8
CHANNEL
IN/OUT X
4
3
5
6
2
1
0
7
8
9
TG
TG
TG
TG
1
TG
COMMON
X OUT/IN
*
A
*
11
B
*
14
*
13
C
INHIBIT
BINARY 1 OF 8 DECODERS WITH INHIBIT
TG
10
TG
TG
TG
TG
TG
TG
17
TG
TG
TG
TG
VDD
*ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
12
VSS
VSS
FIGURE 4. CD4097BMS LOGIC DIAGRAM
7-8
COMMON
Y OUT/IN
CD4067BMS, CD4097BMS
Typical Performance Characteristics
SUPPLY VOLTAGE (VDD - VSS) = 10V
600
CHANNEL ON RESISTANCE (RON) (Ω)
CHANNEL ON RESISTANCE (RON) (Ω)
SUPPLY VOLTAGE (VDD - VSS) = 5V
AMBIENT TEMPERATURE
(TA) = +125oC
500
400
300
+25oC
200
-55oC
100
-3
-2
-1
0
1
2
3
AMBIENT TEMPERATURE
(TA) = +125oC
250
200
+25oC
150
-55oC
100
50
0
-10.0 -7.5
0
-4
300
4
AMBIENT TEMPERATURE
(TA) = +25oC
SUPPLY VOLTAGE (VDD - VSS) = 5V
500
400
300
200
10V
100
15V
0
2.5
5.0
7.5
10.0
SUPPLY VOLTAGE (VDD - VSS) = 15V
300
250
200
AMBIENT TEMPERATURE
(TA) = +125oC
150
100
+25oC
50
-55oC
0
0
-10.0 -7.5
-2.5
FIGURE 6. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
CHANNEL ON RESISTANCE (RON) (Ω)
CHANNEL ON RESISTANCE (RON) (Ω)
FIGURE 5. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
600
-5.0
INPUT SIGNAL VOLTAGE (VIS) (V)
INPUT SIGNAL VOLTAGE (VIS) (V)
-5.0
-2.5
0
2.5
5.0
7.5
10.0
-10.0 -7.5
INPUT SIGNAL VOLTAGE (VIS) (V)
-5.0
-2.5
0
2.5
5.0
7.5
10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
FIGURE 7. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
FIGURE 8. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
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CD4067BMS, CD4097BMS
Chip Dimensions and Pad Layouts
CD4067BMSH
CD4097BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
Special Considerations
In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load). This
provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the
CD4067BMS or CD4097BMS.
channel will lose 3 to 4% of its voltage at the moment the
channel turns on or off. This loss of voltage is essentially
independent of the address or inhibit signal transition time, if
the transition time is less than 1 - 2µs. When the inhibit signal turns a channel off, there is no charge dumping to VSS.
Rather, there is a slight rise in the channel voltage level
(65mV typ.) due to capacitive coupling from inhibit input to
channel input or output. Address inputs also couple some
voltage steps onto the channel signal levels.
When switching from one address to another, some of the
ON periods of the channels of the multiplexers will overlap
momentarily, which may be objectionable in certain applications. Also when a channel is turned on or off by an address
input, there is a momentary conductive path from the channel to VSS, which will dump some charge from any capacitor
connected to the input or output of the channel. The inhibit
input turning on a channel will similarly dump some charge
to VSS.
In certain applications, the external load resistor current may
include both VDD and signal-line components. To avoid
drawing VDD current when switch current flows into the
transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8 volt (calculated from
RON values shown in ELECTRICAL CHARACTERISTICS
CHART - Table 1). no VDD current will flow through RL if the
switch current flows into terminal 1 on the CD4067BMS, terminals 1 and 17 on the CD4097BMS.
The amount of charge dumped is mostly a function of the
signal level above VSS. Typically, at VDD - VSS = 10V, a
100pF capacitor connected to the input or output of the
METALLIZATION:
PASSIVATION:
BOND PADS:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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