Revised March 2000 DM74LS194A 4-Bit Bidirectional Universal Shift Register General Description Features This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: ■ Parallel inputs and outputs ■ Four operating modes: Synchronous parallel load Right shift Left shift Do nothing Parallel (broadside) load Shift right (in the direction QA toward QD) ■ Positive edge-triggered clocking Shift left (in the direction QD toward QA) ■ Direct overriding clear Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are LOW. Ordering Code: Order Number Package Number Package Description DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006407 www.fairchildsemi.com DM74LS194A 4-Bit Bidirectional Universal Shift Register August 1986 DM74LS194A Function Table Inputs Clear Mode S1 S0 Clock Outputs Serial Left Parallel Right A B C D QA QB QC QD L X X X X X X X X X L L L L H X X L X X X X X X QA0 QB0 QC0 QD0 H H H ↑ X X a b c d a b c d H L H ↑ X H X X X X H QAn QBn QCn H L H ↑ X L X X X X L QAn QBn QCn H H L ↑ H X X X X X QBn QCn QDn H H H L ↑ L X X X X X QBn QCn QDn L H L L X X X X X X X QA0 QB0 QC0 QD0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a, b, c, d = The level of steady state input at inputs A, B, C or D, respectively. QA0, QB0, QC0, Q D0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, Q Dn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock. Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 25 Clock Frequency (Note 3) 0 20 tW tSU V 2 Pulse Width Clock 20 (Note 4) Clear 20 Setup Time Mode 30 (Note 4) Data 20 tH Hold Time (Note 4) 0 tREL Clear Release Time (Note 4) 25 TA Free Air Operating Temperature 0 V MHz ns ns ns ns °C 70 Note 2: CL = 15 pF, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min VOL Min 2.7 Typ (Note 5) Max Units −1.5 V 3.4 0.35 V 0.5 IOL = 4 mA, VCC = Min 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA IOS Short Circuit Output Current VCC = Max (Note 6) −100 mA ICC Supply Current VCC = Max (Note 7) 23 mA −20 15 mA Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK. 3 www.fairchildsemi.com DM74LS194A Absolute Maximum Ratings(Note 1) DM74LS194A Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay Time From (Input) To (Output) CL = 50 pF, RL = 2 kΩ Min 20 Clock to Any Q LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Any Q HIGH-to-LOW Level Output tPHL Propagation Delay Time Max Clear to Any Q HIGH-to-LOW Output Units MHz 26 ns 35 ns 38 ns Note 8: All typicals are at VCC = 5V, TA = 25°C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK. Timing Diagram Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences www.fairchildsemi.com 4 DM74LS194A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74LS194A 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6