Elpida MC-458CB64ESB 8m-word by 64-bit synchronous dynamic ram module (so dimm) Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CB64ESB, 458CB64PSB
8M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
EO
Description
The MC-458CB64ESB and MC-458CB64PSB are 8,388,608 words by 64 bits synchronous dynamic RAM module
(Small Outline DIMM) on which 4 pieces of 128M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
L
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
Clock frequency
(MAX.)
Access time from CLK
CL = 3
100 MHz
7 ns
CL = 2
67 MHz
8 ns
CL = 3
100 MHz
7 ns
CL = 2
67 MHz
8 ns
/CAS Latency
MC-458CB64PSB-A10B
u
od
Pr
MC-458CB64ESB-A10B
(MIN.)
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single +3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
ct
• Burst termination by Burst Stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0068N10 (1st edition)
(Previous No. M12263EJAV0DS00)
Date Published January 2001 CP (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Ordering Information
Part number
Clock frequency
Package
Mounted devices
MHz (MAX.)
MC-458CB64ESB-A10B
100 MHz
144-pin Small Outline DIMM
4 pieces of µPD45128163G5 (Rev. E)
(Socket Type)
(10.16mm (400) TSOP (II))
Edge connector: Gold plated
MC-458CB64PSB-A10B
100 MHz
25.4 mm height
4 pieces of µPD45128163G5 (Rev. P)
(10.16mm (400) TSOP (II))
L
EO
ct
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Pr
2
Data Sheet E0068N10
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
Vss
DQ 0
DQ 1
DQ 2
DQ 3
VCC
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB0
DQMB1
VCC
A0
A1
A2
Vss
DQ 8
DQ 9
DQ 10
DQ 11
VCC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
L
EO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CLK0
CKE0
Vcc
Vcc
/RAS
/CAS
/WE
NC
/CS0
NC
NC
NC
NC
CLK1
Vss
Vss
NC
NC
NC
NC
VCC
Vcc
DQ 16
DQ 48
DQ 17
DQ 49
DQ 18
DQ 50
DQ 19
DQ 51
Vss
Vss
DQ 20
DQ 52
DQ 21
DQ 53
DQ 22
DQ 54
DQ 23
DQ 55
Vcc
Vcc
A6
A7
A8
BA0 (A13)
Vss
Vss
A9
BA1 (A12)
A10
A11
Vcc
Vcc
DQMB2
DQMB6
DQMB3
DQMB7
Vss
Vss
DQ 56
DQ 24
DQ 57
DQ 25
DQ 58
DQ 26
DQ 59
DQ 27
VCC
Vcc
DQ 60
DQ 28
DQ 61
DQ 29
DQ 62
DQ 30
DQ 63
DQ 31
Vss
Vss
SCL
SDA
VCC
Vcc
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
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od
Pr
Data Sheet E0068N10
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0(A13), BA1(A12) : SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0, CLK1
: Clock Input
CKE0
: Clock Enable Input
/CS0
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
NC
ct
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
: Ground
: No Connection
3
Block Diagram
/WE
/CS0
LDQM
DQMB0
DQ 0
/CS
/WE
DQ 0
DQ 1
DQ 1
DQ 33
DQ 1
DQ 2
DQ 2
DQ 34
DQ 2
DQ 3
DQ 3
DQ 35
DQ 3
DQ 4
DQ 4
DQ 36
DQ 4
DQ 5
DQ 5
DQ 37
DQ 5
DQ 6
DQ 6
DQ 38
DQ 6
DQ 7
DQ 7
DQ 39
DQ 7
UDQM
EO
DQMB4
DQ 32
D0
UDQM
DQ 15
DQMB5
DQ 40
DQ 9
DQ 14
DQ 41
DQ 14
DQ 10
DQ 13
DQ 42
DQ 13
DQ 11
DQ 12
DQ 43
DQ 12
DQ 12
DQ 11
DQ 44
DQ 11
DQ 13
DQ 10
DQ 45
DQ 10
DQ 14
DQ 9
DQ 46
DQ 9
DQ 15
DQ 8
DQ 47
DQ 8
DQMB2
DQ 16
DQ 7
DQMB6
DQ 48
DQ 7
DQ 17
DQ 6
DQ 49
DQ 6
DQ 18
DQ 5
DQ 50
DQ 5
DQ 19
DQ 4
DQ 51
DQ 4
DQ 20
DQ 3
DQ 52
DQ 3
DQ 21
DQ 2
DQ 53
DQ 2
DQ 22
DQ 1
DQ 54
DQ 1
DQ 23
DQ 0
DQ 55
DQ 0
L
DQMB1
DQ 8
LDQM
/CS
/WE
D2
DQ 15
/CS
LDQM
/WE
DQ 24
DQ 8
DQ 25
DQ 9
DQ 57
DQ 9
DQ 26
DQ 10
DQ 58
DQ 10
DQ 27
DQ 11
DQ 59
DQ 11
DQ 28
DQ 12
DQ 60
DQ 12
DQ 29
DQ 13
DQ 61
DQ 13
DQ 30
DQ 14
DQ 62
DQ 14
DQ 31
DQ 15
DQ 63
DQ 15
CLK0
SDA
A1
DQ 8
10 Ω
SERIAL PD
A0
D3
UDQM
DQMB7
DQ 56
SCL
/WE
u
od
Pr
D1
UDQM
DQMB3
/CS
LDQM
DQ 0
CLK : D0, D2
CLK : D1, D3
A2
CLK1
10pF
A0 - A11 : D0 - D3
/RAS : D0 - D3
BA0
A13 : D0 - D3
/CAS
/CAS : D0 - D3
BA1
A12 : D0 - D3
CKE0
CKE : D0 - D3
VCC
D0 - D3
C
VSS
D0 - D3
Remark D0 - D3: µPD45128163 (2M words × 16 bits × 4 banks)
4
/RAS
ct
A0 - A11
Data Sheet E0068N10
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
4
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
EO
Voltage on power supply pin relative to GND
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
L
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
High level input voltage
Low level input voltage
Operating ambient temperature
Condition
MIN.
TYP.
MAX.
u
od
Pr
Supply voltage
Symbol
VCC
3.0
VIH
3.3
Unit
3.6
V
2.0
VCC + 0.3
V
VIL
–0.3
+ 0.8
V
TA
0
70
°C
MAX.
Unit
pF
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
TYP.
CI1
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
30
CI2
CLK0
30
CI3
CKE0
30
CI4
/CS0
30
CI5
DQMB0 -DQMB7
10
CI/O
DQ0 - DQ63
10
pF
ct
Data Sheet E0068N10
5
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Precharge standby current
in power down mode
Precharge standby current
ICC1
ICC2P
ICC2PS
ICC2N
in non power down mode
EO
Active standby current in
power down mode
Active standby current in
MAX.
Unit
Notes
mA
1
Burst length = 1, tRC ≥ tRC(MIN.)
/CAS latency = 2
440
IO = 0 mA
/CAS latency = 3
440
CKE ≤ VIL(MAX.), tCK = 15 ns
4
CKE ≤ VIL(MAX.), tCK = ∞
4
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
80
ICC3P
ICC3PS
ICC3N
CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
32
CKE ≤ VIL(MAX.), tCK = 15 ns
20
CKE ≤ VIL(MAX.), tCK = ∞
16
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
120
mA
mA
mA
mA
Input signals are changed one time during 30 ns.
ICC3NS
ICC4
CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
80
tCK ≥ tCK(MIN.) , IO = 0 mA
/CAS latency = 2
400
/CAS latency = 3
560
(Burst mode)
ICC5
tRC ≥ tRC(MIN.)
L
CBR (Auto) refresh current
MIN.
Input signals are changed one time during 30 ns.
ICC2NS
non power down mode
Operating current
Test condition
Symbol
/CAS latency = 2
880
/CAS latency = 3
880
Self refresh current
ICC6
CKE ≤ 0.2 V
Input leakage current
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
Output leakage current
IO(L)
DOUT is disabled, VO = 0 to 3.6 V
High level output voltage
VOH
IO = – 4.0 mA
Low level output voltage
VOL
IO = + 4.0 mA
mA
2
mA
3
8
mA
–4
+4
µA
– 1.5
+ 1.5
µA
V
u
od
Pr
2.4
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
ct
6
Data Sheet E0068N10
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
EO
Transition time (Input rise and fall time)
Output timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
tCK
tCH
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
2.4 V
1.4 V
L
Input
0.4 V
tAC
tOH
u
od
Pr
Output
ct
Data Sheet E0068N10
7
Synchronous Characteristics
Parameter
Symbol
-A 10B
MIN.
Clock cycle time
Access time from CLK
Unit
MAX.
/CAS latency = 3
tCK3
10
ns
/CAS latency = 2
tCK2
15
ns
/CAS latency = 3
tAC3
7
ns
1
/CAS latency = 2
tAC2
8
ns
1
tCH
3.5
ns
CLK low level width
tCL
3.5
ns
Data-out hold time
tOH
3
ns
Data-out low-impedance time
tLZ
0
ns
/CAS latency = 3
tHZ3
3
7
ns
/CAS latency = 2
tHZ2
3
8
ns
Data-in setup time
tDS
2.5
ns
Data-in hold time
tDH
1
ns
Address setup time
tAS
2.5
ns
Address hold time
tAH
1
ns
CKE setup time
tCKS
2.5
ns
CKE hold time
tCKH
1
ns
CKE setup time (Power down exit)
tCKSP
2.5
ns
EO
CLK high level width
Data-out high-impedance time
L
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
1
u
od
Pr
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Note
tCMS
2.5
ns
tCMH
1
ns
Z = 50 Ω
Output
50 pF
ct
8
Data Sheet E0068N10
Asynchronous Characteristics
Parameter
Symbol
-A 10B
MIN.
Unit
MAX.
tRC
90
ACT to PRE command period
tRAS
60
PRE to ACT command period
tRP
30
ns
Delay time ACT to READ/WRITE command
tRCD
30
ns
ACT(0) to ACT(1) command period
tRRD
20
ns
Data-in to PRE command period
tDPL
10
ns
Data-in to ACT(REF) command /CAS latency = 3
tDAL3
1CLK+30
ns
period (Auto precharge)
tDAL2
1CLK+30
ns
tRSC
2
CLK
tT
1
EO
REF to REF/ACT command period
/CAS latency = 2
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
Note
ns
120,000
ns
30
ns
64
ms
L
ct
u
od
Pr
Data Sheet E0068N10
9
Serial PD
(1/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
0
Defines the number of bytes written into
serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
09H
0
0
0
0
1
0
0
1
9 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
EO
6
Data width
40H
0
1
0
0
0
0
0
0
64 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
CL = 3 Cycle time
-A10B A0H
1
0
1
0
0
0
0
0
10 ns
CL =3 Access time
-A10B
70H
0
1
1
1
0
0
0
0
7 ns
11
DIMM configuration type
00H
0
0
0
0
0
0
0
0
Non-parity
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
10H
0
0
0
1
0
0
0
0
×16
14
Error checking SDRAM width
00H
0
0
0
0
0
0
0
0
None
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
22
SDRAM device attributes: General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A10B F0H
1
1
1
1
0
0
0
0
15 ns
24
CL = 2 Access time
8 ns
L
9
10
27
tRP(MIN.)
28
tRRD(MIN.)
29
tRCD(MIN.)
30
tRAS(MIN.)
u
od
Pr
25-26
-A10B
80H
1
0
0
0
0
0
0
0
00H
0
0
0
0
0
0
0
0
-A10B 1EH
0
0
0
1
1
1
1
0
-A10B
30 ns
14H
0
0
0
1
0
1
0
0
20 ns
-A10B 1EH
0
0
0
1
1
1
1
0
30 ns
-A10B 3CH
0
0
1
1
1
1
0
0
60 ns
ct
10
Data Sheet E0068N10
(2/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
31
Module bank density
10H
0
0
0
1
0
0
0
0
64 M bytes
32
Command and address signal setup -A10B
time
25H
0
0
1
0
0
1
0
1
2.5 ns
33
Command and address signal hold
time
10H
0
0
0
1
0
0
0
0
1 ns
34
Data signal input setup time
-A10B
25H
0
0
1
0
0
1
0
1
2.5 ns
35
Data signal input hold time
-A10B
10H
0
0
0
1
0
0
0
0
1 ns
00H
0
0
0
0
0
0
0
0
12H
0
0
0
1
0
0
1
0
B5H
1
0
1
1
0
1
0
1
-A10B
EO
36-61
62
SPD revision
63
Checksum for bytes 0 – 62
64-71
72
-A10B
1.2
Manufacture’s JEDEC ID code
Manufacturing location
73-90
Manufacture’s P/N
91-92
Revision code
93-94
Manufacturing date
95-98
Assembly serial number
L
99-125 Mfg specific
126
Intel specification frequency
-A10B
66H
0
1
1
0
0
1
1
0
127
Intel specification /CAS latency
support
-A10B
06H
0
0
0
0
0
1
1
0
u
od
Pr
Timing Chart
66 MHz
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
ct
Data Sheet E0068N10
11
Package Drawing
144 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
M1 (AREA B)
R
N
EO
M2 (AREA A)
M
L
H
S
A
(OPTIONAL HOLES)
U1
U2
C
B
L
I
Q
T
E
D
A1 (AREA A)
F
u
od
Pr
ITEM
A
detail of A part
W
D2
D1
X
V
MILLIMETERS
67.6
A1
67.6±0.15
B
23.2
C
29.0
D
4.6
D1
1.5±0.10
D2
4.0
E
32.8
F
3.7
H
0.8(T.P.)
I
3.3
L
20.0
M
25.4±0.15
M1
3.4
22.0
N
3.8 MAX.
Q
R2.0
R
T
4.0±0.10
φ 1.8
1.0±0.1
U1
3.2 MIN.
U2
4.0 MIN.
V
0.25 MAX.
W
0.6±0.05
Y
2.0 MIN.
ct
M2
S
M144S-80A10
12
Data Sheet E0068N10
[MEMO]
L
EO
ct
u
od
Pr
Data Sheet E0068N10
13
[MEMO]
L
EO
ct
u
od
Pr
14
Data Sheet E0068N10
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
EO
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
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No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
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related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
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Data Sheet E0068N10
15
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
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• The information in this document is current as of January, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
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