LINER LCZM 16-/14-/12-bit vout dacs in 3mm ã 3mm dfn Datasheet

LTC2641/LTC2642
16-/14-/12-Bit VOUT DACs in
3mm × 3mm DFN
FEATURES
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DESCRIPTION
Tiny 3mm × 3mm 8-Pin DFN Package
Maximum 16-Bit INL Error: ±2LSB over Temperature
Low 120μA Supply Current
Guaranteed Monotonic over Temperature
Low 0.5nV•sec Glitch Impulse
2.7V to 5.5V Single Supply Operation
Fast 1μs Settling Time to 16 Bits
Unbuffered Voltage Output Directly Drives 60k Loads
50MHz SPITM/QSPITM/MICROWIRETM Compatible
Serial Interface
Power-On Reset Clears DAC Output to Zero Scale
(LTC2641) or Midscale (LTC2642)
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
Asynchronous ⎯C⎯L⎯R Pin
8-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2641)
10-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2642)
APPLICATIONS
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High Resolution Offset and Gain Adjustment
Process Control and Industrial Automation
Automatic Test Equipment
Data Aquisition Systems
The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit
unbuffered voltage output DACs. These DACs operate from
a single 2.7V to 5.5V supply and are guaranteed monotonic
over temperature. The LTC2641-16/LTC2642-16 provide
16-bit performance (±2LSB INL and ±1LSB DNL) over
temperature. Unbuffered DAC outputs result in low supply
current of 120μA and a low offset error of ±1LSB.
Both the LTC2641 and LTC2642 feature a reference input
range of 2V to VDD. VOUT swings from 0V to VREF. For
bipolar operation, the LTC2642 includes matched scaling
resistors for use with an external precision op amp (such
as the LT1678), generating a ±VREF output swing at RFB.
The LTC2641/LTC2642 use a simple SPI/MICROWIRE
compatible 3-wire serial interface which can be operated
at clock rates up to 50MHz and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the LTC2641’s DAC output
to zero scale and the LTC2642’s DAC output to midscale
when power is initially applied. A logic low on the ⎯C⎯L⎯R pin
asynchronously clears the DAC to zero scale (LTC2641)
or midscale (LTC2642). These DACs are all specified over
the commercial and industrial ranges.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Bipolar 16-Bit DAC
2.7V TO 5.5V
LTC2642
VDD
1μF
REF
0.1μF
CS
SCLK
DIN
CLR
VDD = 5V
VREF = 2.5V
±2.5V RANGE
0.8
0.6
5pF
–
1/2 LT1678
16-BIT DAC
1.0
RFB
INV
POWER-ON
RESET
LTC2642-16 Integral Nonlinearity
VREF
2V TO VDD
+
VOUT
0.4
BIPOLAR VOUT
–VREF TO VREF
INL (LSB)
0.1μF
0.2
0
–0.2
–0.4
–0.6
16-BIT DATA LATCH
INL 25°C
INL 90°C
INL –45°C
–0.8
CONTROL
LOGIC
–1.0
0
16-BIT SHIFT REGISTER
GND
26412 TA01a
16384
32768
CODE
49152
65535
LT1372 • G10
26412f
1
LTC2641/LTC2642
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VDD to GND .................................................. –0.3V to 6V
⎯C⎯S, SCLK, DIN,
⎯C⎯L⎯R to GND ........................ –0.3V to (VDD + 0.3V) or 6V
REF, VOUT, INV to GND ........ –0.3V to (VDD + 0.3V) or 6V
RFB to INV ....................................................... –6V to 6V
RFB to GND ..................................................... –6V to 6V
Operating Temperature Range
LTC2641C/LTC2642C ............................... 0°C to 70°C
LTC2641I/LTC2642I ............................. –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PIN CONFIGURATION
LTC2641
TOP VIEW
REF 1
CS 2
SCLK 3
8
9
DIN 4
TOP VIEW
GND
7
VDD
6
VOUT
5
CLR
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C (NOTE 2), θJA = 43°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
REF
CS
SCLK
DIN
8
7
6
5
1
2
3
4
GND
VDD
VOUT
CLR
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C (NOTE 2), θJA = 200°C/W
LTC2642
TOP VIEW
REF
TOP VIEW
10 GND
1
9 VDD
CS
2
SCLK
3
DIN
4
8 RFB
7 INV
CLR
5
6 VOUT
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C (NOTE 2), θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
REF
CS
SCLK
DIN
CLR
1
2
3
4
5
10
9
8
7
6
GND
VDD
RFB
INV
VOUT
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C (NOTE 2), θJA = 120°C/W
26412f
2
LTC2641/LTC2642
ORDER INFORMATION
LTC2641
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2641CDD-16#PBF
LTC2641CDD-14#PBF
LTC2641CDD-12#PBF
LTC2641CDD-16#TRPBF
LTC2641CDD-14#TRPBF
LTC2641CDD-12#TRPBF
LCZP
LCZN
LCZM
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2641IDD-16#PBF
LTC2641IDD-14#PBF
LTC2641IDD-12#PBF
LTC2641IDD-16#TRPBF
LTC2641IDD-14#TRPBF
LTC2641IDD-12#TRPBF
LCZP
LCZN
LCZM
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2641CMS8-16#PBF
LTC2641CMS8-14#PBF
LTC2641CMS8-12#PBF
LTC2641CMS8-16#TRPBF
LTC2641CMS8-14#TRPBF
LTC2641CMS8-12#TRPBF
LTCZS
LTCZR
LTCZQ
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2641IMS8-16#PBF
LTC2641IMS8-14#PBF
LTC2641IMS8-12#PBF
LTC2641IMS8-16#TRPBF
LTC2641IMS8-14#TRPBF
LTC2641IMS8-12#TRPBF
LTCZS
LTCZR
LTCZQ
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2642CDD-16#PBF
LTC2642CDD-14#PBF
LTC2642CDD-12#PBF
LTC2642CDD-16#TRPBF
LTC2642CDD-14#TRPBF
LTC2642CDD-12#TRPBF
LCZW
LCZV
LCZT
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2642IDD-16#PBF
LTC2642IDD-14#PBF
LTC2642IDD-12#PBF
LTC2642IDD-16#TRPBF
LTC2642IDD-14#TRPBF
LTC2642IDD-12#TRPBF
LCZW
LCZV
LCZT
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2642CMS-16#PBF
LTC2642CMS-14#PBF
LTC2642CMS-12#PBF
LTC2642CMS-16#TRPBF
LTC2642CMS-14#TRPBF
LTC2642CMS-12#TRPBF
LTCZZ
LTCZY
LTCZX
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
LTC2642IMS-16#PBF
LTC2642IMS-14#PBF
LTC2642IMS-12#PBF
LTC2642IMS-16#TRPBF
LTC2642IMS-14#TRPBF
LTC2642IMS-12#TRPBF
LTCZZ
LTCZY
LTCZX
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC2642
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
26412f
3
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
LTC2641-12
LTC2642-12
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2641-14
LTC2642-14
MAX
MIN
TYP
LTC2641-16
LTC2642-16
MAX
MIN
TYP
MAX
UNITS
Static Peformance
N
Resolution
●
12
14
16
Bits
Monotonicity
●
12
14
16
Bits
DNL
Differential Nonlinearity
(Note 2)
●
±0.5
±0.5
±1
±0.5
±1
LSB
INL
Integral Nonlinearity
(Note 2)
●
±0.5
±0.5
±1
±0.5
±2
LSB
ZSE
Zero Code Offset Error
Code = 0
●
1
2
LSB
ZSTC
Zero Code Tempco
GE
Gain Error
±0.05
GETC
Gain Error Tempco
ROUT
DAC Output Resistance
(Note 4)
Bipolar Resistor Matching
(LTC2642) RFB/RINV
●
±0.5
Bipolar Zero Offset Error
(LTC2642)
BZSTC
Bipolar Zero Tempco
(LTC2642)
PSR
Power Supply Rejection
ΔVDD = ±10%
●
±0.05
±2
±0.05
±1
±4
±2
ppm/°C
±5
LSB
±0.1
±0.1
±0.1
ppm/°C
6.2
6.2
6.2
kΩ
1
1
1
Ratio Error (Note 7) ●
BZE
2
±0.1
±0.5
±2
±0.1
●
±0.03
±0.5
±0.015
±4
±2
±0.1
±0.5
±0.1
±0.5
%
±5
LSB
ppm/°C
±1
LSB
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
V
Reference Input
VREF
RREF
Reference Input Range
●
2.0
Reference Input Resistance (Note 5)
●
●
11
8.5
Unipolar Mode (LTC2641)
Bipolar Mode (LTC2642)
14.8
11.4
kΩ
kΩ
15
V/μs
Dynamic Performance—VOUT
SR
Voltage Output Slew Rate
Measured from 10% to 90%
Output Settling Time
To ±0.5LSB of FS
DAC Glitch Impulse
Major Carry Transition
0.5
1
nV•s
μs
Digital Feedthrough
Code = 0000hex; NCS = VDD;
SCLK, DIN 0V to VDD Levels
0.2
nV•s
Reference –3dB Bandwidth
Code = FFFFhex
1.3
Reference Feedthrough
Code = 0000hex, VREF = 1VP-P at 100kHz
Dynamic Performance—Reference Input
BW
SNR
Signal-to-Noise Ratio
CIN(REF)
Reference Input Capacitance
Code = 0000hex
Code = FFFFhex
VIH
Digital Input High Voltage
VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
●
●
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
●
●
MHz
1
mVP-P
92
dB
75
120
pF
pF
Digital Inputs
2.4
2.0
V
V
0.8
0.6
V
V
26412f
4
LTC2641/LTC2642
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
IIN
Digital Input Current
VIN = GND to VCC
●
CIN
Digital Input Capacitance
(Note 6)
●
VH
Hysteresis Voltage
TYP
MAX
UNITS
±1
μA
3
10
pF
0.15
V
Power Supply
●
VDD
Supply Voltage
IDD
Supply Current, VDD
Digital Inputs = 0V or VDD
PD
Power Dissipation
Digital Inputs = 0V or VDD, VDD = 5V
Digital Inputs = 0V or VDD, VDD = 3V
2.7
●
5.5
120
200
0.60
0.36
V
μA
mW
mW
TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL
PARAMETER
t1
DIN Valid to SCLK Setup Time
●
10
ns
t2
DIN Valid to SCLK Hold Time
●
0
ns
t3
SCLK Pulse Width High
●
9
ns
t4
SCLK Pulse Width Low
⎯CS
⎯ Pulse High Width
●
9
ns
●
10
ns
●
8
ns
t7
LSB SCLK High to ⎯C⎯S High
⎯C⎯S Low to SCLK High
●
8
ns
t8
⎯C⎯S High to SCLK Positive Edge
●
8
ns
t9
⎯C⎯L⎯R Pulse Width Low
●
15
ns
SCLK Frequency
⎯ S
⎯ Low (Power-Up Delay)
VDD High to C
●
t5
t6
fSCLK
CONDITIONS
MIN
50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
TYP
MAX
50
UNITS
MHz
30
μs
Note 4: ROUT tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.
26412f
5
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
vs Supply (VDD)
Integral Nonlinearity (INL)
1.0
1.0
LTC2642-16
VREF = 2.5V
VDD = 5V
0.4
0.2
0.2
0
–0.2
0.6
+INL
0
–INL
–0.2
–0.6
–0.6
–0.6
–0.8
–0.8
–0.8
–1.0
–1.0
–1.0
32768
CODE
65535
49152
3
2
4
VDD (V)
6
5
1.0
LTC2642-16
VREF = 2.5V
VDD = 5V
DNL vs VREF
1.0
VREF = 2.5V
0.8
0.4
0.2
DNL (LSB)
0.4
0.2
–0.2
0.6
0.4
+DNL
0
–DNL
–0.2
0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–0.8
–1.0
16384
32768
CODE
49152
–1.0
3
2
65535
4
6
5
INL vs Temperature
DNL vs Temperature
VREF = 2.5V
VDD = 5V
0.8
0.6
Bipolar Zero Error vs Temperature
5
VREF = 2.5V
VDD = 5V
4
0.6
+INL
2
0.2
+DNL
0
BZE (LSB)
DNL (LSB)
–INL
–DNL
–0.2
1
0
–1
–0.4
–0.4
–2
–0.6
–0.6
–3
–0.8
–0.8
–4
–1.0
–40
–1.0
–40
–15
35
10
TEMPERATURE (°C)
60
85
26412 G07
VREF = 2.5V
VDD = 5V
3
0.4
0
–0.2
6
5
26412 G06
1.0
0.2
4
VREF (V)
26412 G05
1.0
0.4
3
2
VDD (V)
26412 G04
0.8
–DNL
–0.2
–0.4
0
+DNL
0
–0.6
–1.0
VDD = 5.5V
0.8
0.6
0
6
5
26412 G03
DNL (LSB)
0.6
4
VREF (V)
3
2
Differential Nonlinearity (DNL)
vs Supply (VDD)
1.0
0.8
–INL
26412 G02
Differential Nonlinearity (DNL)
DNL (LSB)
0
–0.2
–0.4
26412 G01
INL (LSB)
0.2
–0.4
16384
+INL
0.4
–0.4
0
VDD = 5.5V
0.8
0.6
0.4
INL (LSB)
INL (LSB)
0.6
VREF = 2.5V
0.8
INL (LSB)
0.8
INL vs VREF
1.0
–15
35
10
TEMPERATURE (°C)
60
85
26412 G08
–5
–40
–15
35
10
TEMPERATURE (°C)
60
85
26412 G09
26412f
6
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Unbuffered Zero Scale Error vs
Temperature (LTC2641-16)
Bipolar Gain Error vs Temperature
5
VREF = 2.5V
VDD = 5V
1.0
0.8
0.6
0.6
2
0.4
0.4
1
0.2
0.2
0
–1
FSE (LSB)
0.8
ZSE (LSB)
BGE (LSB)
1.0
3
4
0
–0.2
–0.4
–0.4
–3
–0.6
–0.6
–4
–0.8
–0.8
–15
35
10
TEMPERATURE (°C)
60
–1.0
–40
85
–15
35
10
TEMPERATURE (°C)
60
26412 G10
–1.0
–40
85
LTC2642-14
VREF = 2.5V
VDD = 5V
250
LTC2642-14
VREF = 2.5V
VDD = 5V
0.8
0.4
0.2
DNL (LSB)
0.4
0.2
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
0
4096
8192
CODE
12288
0
16383
4096
8192
CODE
LTC2642-12
VREF = 2.5V
VDD = 5V
LTC2642-12
VREF = 2.5V
VDD = 5V
0.2
DNL (LSB)
0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–1.0
2048
CODE
3072
4095
26412 G16
49152
65535
VREF = 2.5V
200
IREF (μA)
0.6
0.4
1024
32768
IREF vs Code (Bipolar LTC2642)
250
0.8
0.4
0
16384
26412 G15
1.0
0
0
CODE
12-Bit Differential Nonlinearity
(DNL) (LTC2642-12)
1.0
–0.2
100
26412 G14
12-Bit Integral Nonlinearity (INL)
(LTC2642-12)
0.6
150
0
16383
12288
26412 G13
0.8
VREF = 2.5V
50
–1.0
–1.0
85
200
IREF (μA)
0.6
0
60
IREF vs Code (Unipolar LTC2641)
1.0
0.6
35
10
TEMPERATURE (°C)
26412 G12
14-Bit Differential Nonlinearity
(DNL) (LTC2642-14)
1.0
0.8
–15
26412 G11
14-Bit Integral Nonlinearity (INL)
(LTC2642-14)
INL (LSB)
0
–0.2
–2
–5
–40
INL (LSB)
Unbuffered Full-Scale Error vs
Temperature (LTC2641-16)
150
100
50
0
0
1024
2048
CODE
3072
4095
0
16384
32768
49152
65535
CODE
26412 G17
26412 G18
26412f
7
LTC2641/LTC2642
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current (IDD) vs
Temperature
150
Supply Current (IDD) vs Supply
Voltage (VDD)
150
VREF = 2.5V
Supply Current (IDD) vs Digital
Input Voltage
900
VREF = 2.5V
800
125
125
VDD = 5V
IDD (μA)
75
75
50
50
25
25
VDD = 5V
600
100
VDD = 3V
IDD (μA)
IDD (μA)
100
700
500
400
300
VDD = 3V
200
100
0
–40
–15
10
35
TEMPERATURE (°C)
0
85
60
0
2.5
3.5
3
4
5
4.5
150
VDD = 5V
100
100
IDD (μA)
125
IDD (μA)
125
50
25
25
1.5
2
2.5
3
3.5
4
Midscale Glitch Impulse
CS
5V/DIV
VDD = 3V
5
LTC2641-16
UNBUFFERED
CL = 10pF
1
VREF (V)
1.5
2
VREF (V)
26412 G22
2.5
CS
5V/DIV
500ns/DIV
26412 G25
500ns/DIV
26412 G24
VOUT vs VDD = 0V to 5.5V
(POR Function) LTC2641
VDD = VREF
0V TO 5.5V
2V/DIV
SETTLE
RESIDUE
250μV/DIV
VOUT
1V/DIV
CODE
32767
3
Full-Scale Settling (Zoomed In)
CS
5V/DIV
CODE
32768
26412 G23
Full-Scale Transition
LTC2641-16
UNBUFFERED
CL = 10pF
VREF = 2.5V
VDD = 5V
CODE
32767
VOUT
20mV/DIV
0
4.5
5
75
50
1
1 1.5 2 2.5 3 3.5 4 4.5
DIGITAL INPUT VOLTAGE (V)
26412 G21
Supply Current (IDD) vs VREF,
VDD = 3V
75
0.5
26412 G20
Supply Current (IDD) vs VREF,
VDD = 5V
0
0
VDD (V)
26412 G19
150
5.5
VOUT
10mV/DIV
LTC2641-16
500ns/DIV
VREF = 2.5V
CONSULT FACTORY FOR
MEASUREMENT CIRCUIT
26412 G26
LTC2641-16
UNBUFFERED
CL = 10pF
50ms/DIV
26412 G27
26412f
8
LTC2641/LTC2642
PIN FUNCTIONS
LTC2641
LTC2642
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
⎯C⎯S (Pin 2): Serial Interface Chip Select/Load Input. When
⎯C⎯S is low, SCLK is enabled for shifting in data on DIN.
When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
⎯C⎯S (Pin 2): Serial Interface Chip Select/Load Input. When
⎯C⎯S is low, SCLK is enabled for shifting in data on DIN.
When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied
to DIN for transfer to the device at the rising edge of
SCLK.
DIN (Pin 4): Serial Interface Data Input. Data is applied
to DIN for transfer to the device at the rising edge of
SCLK.
⎯C⎯L⎯R (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to code 0.
⎯ ⎯L⎯R (Pin 5): Asynchronous Clear Input. A logic low clears
C
the DAC to midscale.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF.
VDD (Pin 7): Supply Voltage. Set between 2.7V and
5.5V.
INV (Pin 7): Center Tap of Internal Scaling Resistors.
Connect to an external amplifier’s inverting input in bipolar
mode.
GND (Pin 8): Circuit Ground.
Exposed Pad (DFN Pin 9): Circuit Ground. Must be soldered to PCB ground.
RFB (Pin 8): Feedback Resistor. Connect to an external
amplifier’s output in bipolar mode. The bipolar output
range is –VREF to VREF.
VDD (Pin 9): Supply Voltage. Set between 2.7V and
5.5V.
GND (Pin 10): Circuit Ground.
Exposed Pad (DFN Pin 11): Circuit Ground. Must be
soldered to PCB ground.
26412f
9
LTC2641/LTC2642
BLOCK DIAGRAMS
LTC2641
7
LTC2642
9
1
REF
VDD
POWER-ON
RESET
3
4
5
VOUT
16-/14-/12-BIT DAC
6
CS
2
SCLK
DIN
REF
RFB
LTC2642-16
LTC2642-14
LTC2642-12
LTC2641-16
LTC2641-14
LTC2641-12
2
1
VDD
CONTROL
LOGIC
CLR
3
16-BIT DATA LATCH
4
16-BIT SHIFT REGISTER
5
GND
8
INV
POWER-ON
RESET
16-/14-/12-BIT DAC
CONTROL
LOGIC
16-BIT DATA LATCH
VOUT
8
7
6
CS
SCLK
DIN
CLR
16-BIT SHIFT REGISTER
GND
2641 BD
10
2642 BD
TIMING DIAGRAM
t1
t2
t3
1
SCK
2
t4
t6
3
15
16
t8
SDI
t5
t7
26412 TD
CS/LD
OPERATION
General Description
Digital-to-Analog Architecture
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
±2LSB integral linearity error and less than ±1LSB differential linearity error, guaranteeing monotonic operation. They
operate from a single supply ranging from 2.7V to 5.5V,
consuming 120μA (typical). An external voltage reference
of 2V to VDD determines the DAC’s full-scale output voltage. A 3-wire serial interface allows the LTC2641/LTC2642
to fit into a small 8-/10-pin MSOP or DFN 3mm × 3mm
package.
The DAC architecture is a voltage switching mode resistor ladder using precision thin-film resistors and CMOS
switches. The LTC2641/LTC2642 DAC resistor ladders are
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
impulse is very low at 500pV•sec, CL = 10pF, ten times
lower than previous DACs of this type.
26412f
10
LTC2641/LTC2642
OPERATION
chip select input (⎯C⎯S) controls and frames the loading
of serial data from the data input (DIN). Following a ⎯C⎯S
high-to-low transition, the data on DIN is loaded, MSB
first, into the shift register on each rising edge of the serial
clock input (SCLK). After 16 data bits have been loaded
into the serial input register, a low-to-high transition on ⎯C⎯S
transfers the data to the 16-bit DAC latch, updating the DAC
output (see Figures 1a, 1b, 1c). While ⎯C⎯S remains high,
the serial input shift register is disabled. If there are less
than 16 low-to-high transitions on SCLK while ⎯C⎯S remains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while ⎯C⎯S remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
The digital-to-analog transfer function at the VOUT pin
is:
⎛k⎞
VOUT(IDEAL) = ⎜ N ⎟ VREF
⎝2 ⎠
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is between 2.0V and
VDD (see Tables 1a, 1b and 1c).
The LTC2642 includes matched resistors that are tied to
an external amplifier to provide bipolar output swing (Figure 2). The bipolar transfer function at the RFB pin is:
⎞
⎛ k
VOUT _ BIPOLAR(IDEAL) = VREF ⎜ N–1 – 1⎟
⎠
⎝2
(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
CS
SCLK
DIN
1
2
3
4
5
6
7
D15 D14 D13 D12 D11 D10
8
D9
9
D8
10
D7
D6
11
D5
12
D4
13
D3
14
D2
15
D1
16
DAC
UPDATED
D0
MSB
LSB
26412 F01a
DATA (16 BITS)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
CS
SCLK
DIN
1
2
3
4
D13 D12 D11 D10
5
D9
6
D8
7
D7
8
D6
9
D5
10
D4
11
D3
12
D2
13
D1
MSB
14
D0
15
X
16
DAC
UPDATED
X
LSB
26412 F01b
DATA (14 BITS + 2 DON’T-CARE BITS)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
CS
SCLK
DIN
1
2
D11 D10
3
D9
4
D8
5
D7
6
D6
7
D5
8
D4
9
D3
10
D2
11
D1
MSB
12
D0
13
X
14
X
15
X
LSB
16
DAC
UPDATED
X
26412 F01c
DATA (12 BITS + 4 DON’T-CARE BITS)
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
26412f
11
LTC2641/LTC2642
OPERATION
Power-On Reset
32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048
(LTC2642-12).
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC ouput comes up in a known state.
When VDD is first applied, the power-on reset circuit sets
the output of the LTC2641 to zero-scale (code 0). The
LTC2642 powers up to midscale (bipolar zero). Depending on the DAC number of bits, the midscale code is:
Clearing the DAC
A 10ns (minimum) low pulse on the ⎯C⎯L⎯R pin asynchronously clears the DAC latch to code zero (LTC2641) or to
midscale (LTC2642).
APPLICATIONS INFORMATION
Unipolar Configuration
The external amplifier provides a unity-gain buffer. The
LTC2642 can also be used in unipolar configuration by
tying RFB and INV to REF. This provides power-up and
clear to midscale.
Figure 2 shows a typical unipolar DAC application for
the LTC2641. Tables 1a, 1b and 1c show the unipolar
binary code tables for 16-bit, 14-bit and 12-bit operation.
VREF
2.5V
OUT
0.1μF
5V/3V
4.7μF
IN
5V
LT®1019CS8-2.5
Table 1a. 16-Bit Unipolar Binary Code Table
(LTC2641-16)
GND
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
0.1μF
7
VDD
5V/3V 0.1μF
1
REF
–
LTC2641-16
1/2 LTC6078
2
16-BIT DAC
CS
3
SCLK
4
DIN
5
CLR
VOUT 6
+
MSB
ANALOG OUTPUT
(VOUT)
LSB
1111 1111 1111 1111 VREF (65,535/65,536)
UNIPOLAR VOUT
0V TO 2.5V
1000 0000 0000 0000 VREF (32,768/65,536) = VREF/2
0000 0000 0000 0001 VREF (1/65,536)
0000 0000 0000 0000 0V
GND
26412 F02
8
Figure 2. 16-Bit Unipolar Output (LTC2641-16) Unipolar VOUT = 0V to VREF
Table 1b. 14-Bit Unipolar Binary Code Table
(LTC2641-14)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
MSB
ANALOG OUTPUT
(VOUT)
LSB
Table 1c. 12-Bit Unipolar Binary Code Table
(LTC2641-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
MSB
ANALOG OUTPUT
(VOUT)
LSB
1111 1111 1111 11xx VREF (16,383/16,384)
1111 1111 1111 xxxx VREF (4,095/4,096)
1000 0000 0000 00xx VREF (8,192/16,384) = VREF/2
1000 0000 0000 xxxx VREF (2,048/4,096) = VREF/2
0000 0000 0000 01xx VREF (1/16,384)
0000 0000 0001 xxxx VREF (1/4,096)
0000 0000 0000 00xx 0V
0000 0000 0000 xxxx 0V
26412f
12
LTC2641/LTC2642
APPLICATIONS INFORMATION
Bipolar Configuration
The amplifier circuit provides a gain of +2 from the VOUT
pin, and gain of –1 from VREF. Tables 2a, 2b and 2c show
the bipolar offset binary code tables for 16-bit, 14-bit and
12-bit operation.
Figure 3 shows a typical bipolar DAC application for the
LTC2642. The on-chip bipolar offset/gain resistors, RFB
and RINV, are connected to an external amplifier to produce
a bipolar output swing from –VREF to VREF at the RFB pin.
5V/3V
VREF
2.5V
OUT
0.1μF
0.1μF
9
VDD
4.7μF
RFB 8
C1
10pF
LTC2642-16
5V
INV 7
–
VOUT 6
+
0.1μF
BIPOLAR VOUT
–2.5V TO 2.5V
1/2 LT1678
2
CS
3
SCLK
4
DIN
5
CLR
16-BIT DAC
5V
GND
1
REF
IN
LT1019CS8-2.5
0.1μF
–5V
GND
26412 F02
10
Figure 3. 16-Bit Bipolar Output (LTC2642-16) VOUT = –VREF to VREF
Table 2a. 16-Bit Bipolar Offset Binary
Code Table (LTC2642-16)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
MSB
ANALOG OUTPUT
(VOUT)
LSB
Table 2b. 14-Bit Bipolar Offset Binary
Code Table (LTC2642-14)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
MSB
ANALOG OUTPUT
(VOUT)
LSB
Table 2c. 12-Bit Bipolar Offset Binary
Code Table (LTC2642-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
MSB
ANALOG OUTPUT
(VOUT)
LSB
1111 1111 1111 1111 VREF (32,767/32,768)
1111 1111 1111 11xx VREF (8,191/8,192)
1111 1111 1111 xxxx VREF (2,047/2,048)
1000 0000 0000 0001 VREF (1/32,768)
1000 0000 0000 01xx VREF (1/8,192)
1000 0000 0001 xxxx VREF (1/2,048)
1000 0000 0000 0000 0V
1000 0000 0000 00xx 0V
1000 0000 0000 xxxx 0V
0111 1111 1111 1111 –VREF (1/32,768)
0111 1111 1111 11xx –VREF (1/8,192)
0111 1111 1111 xxxx –VREF (1/2048)
0000 0000 0000 0000 –VREF
0000 0000 0000 00xx –VREF
0000 0000 0000 xxxx –VREF
26412f
13
LTC2641/LTC2642
APPLICATIONS INFORMATION
Unbuffered Operation and VOUT Loading
The DAC output is available directly at the VOUT pin, which
swings from GND to VREF. Unbuffered operation provides
the lowest possible offset, full-scale and linearity errors, the
fastest settling time and minimum power consumption.
However, unbuffered operation requires that appropriate
loading be maintained on the VOUT pin. The LTC2641/
LTC2642 VOUT can be modeled as an ideal voltage source
in series with a source resistance of ROUT, typically 6.2k
(Figure 4). The DAC’s linear output impedance allows
it to drive medium loads (RL > 60k) without degrading
INL or DNL; only the gain error is increased. The gain
error (GE) caused by a load resistance, RL, (relative to
full scale) is:
–1
GE =
⎛R ⎞
1+ ⎜ OUT ⎟
⎝ RL ⎠
In 16-bit LSBs:
GE =
–65536
[LSB]
⎛ ROUT ⎞
1+ ⎜
⎝ RL ⎟⎠
ROUT has a low tempco (typically < ±50ppm/°C), and is
independent of DAC code. The variation of ROUT, part-topart, is typically less than ±20%.
Note on LSB units:
For the following error descriptions, “LSB” means 16-bit
LSB and 65,536 is rounded to 66k.
To convert to 14-bit LSBs (LTC2641-14/LTC2642-14)
divide by 4.
To convert to 12-bit LSBs (LTC2641-12/LTC2642-12)
divide by 16.
A constant current, IL, loading VOUT will produce an offset
of:
VOFFSET = –IL • ROUT
For VREF = 2.5V, a 16-bit LSB equals 2.5V/65,536, or 38μV.
Since ROUT is 6.2k, an IL of 6nA produces an offset of
1LSB. Therefore, to avoid degrading DAC performance,
it is critical to protect the VOUT pin from any sources of
leakage current.
Unbuffered VOUT Settling Time
The settling time at the VOUT pin can be closely approximated by a single-pole response where:
τ = ROUT • (COUT + CL)
(Figure 4). Settling to 1/2LSB at 16-bits requires about
12 time constants (ln(2 • 65,536)). The typical settling
time of 1μs corresponds to a time constant of 83ns, and
a total (COUT + CL) of about 83ns/6.2k = 13pF. The internal
capacitance, COUT is typically 10pF, so an external CL of
3pF corresponds to 1μs settling to 1/2LSB.
VREF
REF
ROUT
LTC2641
LTC2642
+
( )–
CODE
VREF
2N
VOUT
COUT
GND
VOUT
0V TO VREF
RL
CL
IL
26412 F04
Figure 4. VOUT Pin Equivalent Circuit
Op Amp Selection
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
In bipolar mode (LTC2642 only), the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. In this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
±VREF output range (Figure 3).
In unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applications a precision, rail-to-rail input, single supply op amp
26412f
14
LTC2641/LTC2642
APPLICATIONS INFORMATION
such as the LTC6078 is suitable, if the application does not
require linear operation very near to GND, or zero scale
(Figure 2). The LTC6078 typically swings to within 1mV
of GND if it is not required to sink any load current. For an
LSB size of 38μV, 1mV represents 26 missing codes near
zero scale. Linearity will be degraded over a somewhat
larger range of codes above GND. It is also unavoidable
that settling time and transient performance will degrade
whenever a single supply amplifier is operated very close
to GND, or to the positive supply rail.
The small LSB size of a 16-bit DAC, coupled with the tight
accuracy specifications on the LTC2641/LTC2642, means
that the accuracy and input specifications for the external
op amp are critical for overall DAC performance.
Op Amp Specifications and Unipolar DAC Accuracy
Most op amp accuracy specifications convert easily to
DAC accuracy.
Op amp input bias current on the noninverting (+) input is
equivalent to an IL loading the DAC VOUT pin and therefore
produces a DAC zero-scale error (ZSE) (see Unbuffered
Operation):
ZSE = –IB(IN+) • ROUT [Volts]
In 16-bit LSBs:
( )
⎛ 66k ⎞
ZSE = –IB IN+ • 6.2k • ⎜
[LSB]
⎝ VREF ⎟⎠
Op amp input impedance, RIN, is equivalent to an RL
loading the LTC2641/LTC2642 VOUT pin, and produces a
gain error of:
GE =
–66k
[LSB]
⎛ 6.2k ⎞
1+ ⎜
⎝ RIN ⎟⎠
Op amp offset voltage, VOS, corresponds directly to DAC
zero code offset error, ZSE:
ZSE = VOS •
66k
[LSB]
VREF
Temperature effects also must be considered. Over the
–40°C to 85°C industrial temperature range, an offset
voltage temperature coefficient (referenced to 25°C) of
0.6μV/°C will add 1LSB of zero-scale error. Also, IBIAS and
the VOFFSET error it causes, will typically show significant
relative variation over temperature.
Op amp open-loop gain, AVOL, contributes to DAC gain
error (GE):
GE =
66k
[LSB]
A VOL
Op amp input common mode rejection ratio (CMRR) is an
input-referred error that corresponds to a combination of
gain error (GE) and INL, depending on the op amp architecture and operating conditions. A conservative estimate
of total CMRR error is:
⎛ ⎛ CMRR⎞ ⎞
⎟
⎜
Error = ⎜10⎝ 20 ⎠ ⎟
⎟
⎜
⎝
⎠
⎛V
⎞
• ⎜ CMRR _ RANGE ⎟ • 66k [LSB]
VREF
⎝
⎠
where VCMRR_RANGE is the voltage range that CMRR (in
dB) is specified over. Op amp Typical Performance Characteristics graphs are useful to predict the impact of CMRR
errors on DAC performance. Typically, a precision op amp
will exhibit a fairly linear CMRR behavior (corresponding
to DAC gain error only) over most of the common mode
input range (CMR), and become nonlinear and produce
significant errors near the edge of the CMR.
Rail-to-rail input op amps are a special case, because they
have 2 distinct input stages, one with CMR to GND and
the other with CMR to V+. This results in a “crossover”
CM input region where operation switches between the
two input stages.
The LTC6078 rail-to-rail input op amp typically exhibits
remarkably low crossover linearity error, as shown in the
VOS vs VCM Typical Performance Characteristics graphs
(see the LTC6078 data sheet). Crossover occurs at CM
inputs about 1V below V+, and an LTC6078 operating as
a unipolar DAC buffer with VREF = 2.5V and V+ = 5V will
typically add only about 1LSB of GE and almost no INL
error due to CMRR. Even in a full rail-to-rail application,
with VREF = V+ = 5V, a typical LTC6078 will add only about
1LSB of INL at 16-bits.
26412f
15
LTC2641/LTC2642
APPLICATIONS INFORMATION
Op Amp Specifications and Bipolar DAC Accuracy
The op amp contributions to unipolar DAC error discussed
above apply equally to bipolar operation. The bipolar application circuit gains up the DAC span, and all errors, by
a factor of 2. Since the LSB size also doubles, the errors
in LSBs are identical in unipolar and bipolar modes.
One added error in bipolar mode comes from IB (IN–),
which flows through RFB to generate an offset. The full
bias current offset error becomes:
VOFFSET = (IB (IN–) • RFB – IB (IN+) • ROUT • 2) [Volts]
So:
(
)
VOFFSET = IB (IN– ) • 28k – IB (IN+ ) • 12.4k •
33k
[LSB]
VREF
Settling Time with Op Amp Buffer
When using an external op amp, the output settling time will
still include the single pole settling on the LTC2641/LTC2642
VOUT node, with time constant ROUT • (COUT + CL) (see Unbuffered VOUT Settling Time). CL will include the buffer input
capacitance and PC board interconnect capacitance.
The external buffer amplifier adds another pole to the output
response, with a time constant equal to (fbandwidth/2π).
For example, assume that CL is maintained at the same
value as above, so that the VOUT node time constant is
83ns = 1μs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2π • 83ns) = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
root square sum of the individual time constants, or √⎯2
• 83ns = 117ns, and 1/2 LSB settling time will be ~12 •
117ns = 1.4μs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. In practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1μs.
The output settling time for bipolar applications (Figure 3)
will be somewhat increased due to the feedback resistor
network RFB and RINV (each 28k nominal). The parasitic
capacitance, CP, on the op amp (–) input node will introduce
a feedback loop pole with a time constant of (CP • 28k/2).
A small feedback capacitor, C1, should be included, to
introduce a zero that will partially cancel this pole. C1
should nominally be <CP, typically in the range of 5pF
to 10pF. This will restore the phase margin and improve
coarse settling time, but a pole-zero doublet will unavoidably leave a slower settling tail, with a time constant of
roughly (CP + C1) • 28k/2, which will limit 16-bit settling
time to be greater than 2μs.
Reference and GND Input
The LTC2641/LTC2642 operates with external voltage references from 2V to VDD, and linearity, offset and gain errors
are virtually unchanged vs VREF. Full 16-bit performance
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typical, corresponds to less than 0.5LSB variation over the
–40°C to 85°C temperature range. In practice, this means
that the overall gain error tempco will be determined almost
entirely by the external reference tempco.
The DAC voltage-switching mode “inverted” resistor ladder
architecture used in the LTC2641/LTC2642 exhibits a reference input resistance (RREF) that is code dependent (see
the Typical Performance curves IREF vs Input Code).
In unipolar mode, the minimum RREF is 14.8k (at code
871Chex, 34,588 decimal) and the the maximum RREF is
300k at code 0000hex (zero scale). The maximum change
in IREF for a 2.5V reference is 160μA. Since the maximum
occurs near midscale, the INL error is about one half of the
change on VREF, so maintaining an INL error of <0.1LSB
requires a reference load regulation of (1.53ppm • 2/160μA)
= 19 [ppm/mA]. This implies a reference output impedance
of 48mΩ, including series wiring resistance.
To prevent output glitches from occuring when resistor
ladder branches switch from GND to VREF, the reference
input must maintain low impedance at higher frequencies.
A 0.1μF ceramic capacitor with short leads between REF
and GND provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1μF between REF
and GND provides low frequency bypassing. The circuit
will benefit from even higher bypass capacitance, as long
as the external reference remains stable with the added
capacative loading.
26412f
16
LTC2641/LTC2642
APPLICATIONS INFORMATION
Digital Inputs and Interface Logic
All of the digital inputs include Schmitt-trigger buffers
to accept slow transition interfaces. This means that optocuplers can interface directly to the LTC2641/LTC2642
without additional external logic. Digital input hysteresis
is typically 150mV.
The digital inputs are compatible with TTL/CMOS-logic
levels. However, rail-to-rail (CMOS) logic swings are
preferred, because operating the logic inputs away from
the supply rails generates additional IDD and GND current,
(see Typical Performance Characteristic graph Supply
Current vs Logic Input Voltage).
Digital feedthrough is only 0.2nV•s typical, but it is always
preferred to keep all logic inputs static except when loading
a new code into the DAC.
Board Layout for Precision
Even a small amount of board leakage can degrade accuracy. The 6nA leakage current into VOUT needed to
generate 1LSB offset error corresponds to 833MΩ leakage
resistance from a 5V supply.
The VOUT node is relatively sensitive to capacitive noise
coupling, so minimum trace length, appropriate shielding
and clean board layout are imperative here.
Temperature differences at the DAC, op amp or reference
pins can easily generate tens of microvolts of thermocouple voltages. Analog signal traces should be short,
close together and away from heat dissipating components. Air currents across the board can also generate
thermocouples.
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane.
A “star ground” area should be established by attaching
the LTC2641/LTC2642 GND pin, VREF GND and the DAC
VOUT GND reference terminal to the same area on the GND
plane. Care should be taken to ensure that no large GND
return current paths flow through the “star GND” area. In
particular, the resistance from the LTC2641 GND pin to the
point where the VREF input source connects to the ground
plane should be as low as possible. Excessive resistance
here will be multiplied by the code dependent IREF current
to produce an INL error similar to the error produced by
VREF source resistance.
Sources of ground return current in the analog area include
op amp power supply bypass capacitors and the GND
connection for single supply amps. A useful technique
for minimizing errors is to use a separate board layer
for power ground return connections, and reserve one
ground plane layer for low current “signal” GND connections. The “signal”, or “star” GND plane must connected
to the “power” GND plane at a single point, which should
be located near the LTC2641/LTC2642 GND pin.
If separate analog and digital ground areas exist it is necessary to connect them at a single location, which should be
fairly close to the DAC for digital signal integrity. In some
systems, large GND return currents can flow between the
digital and analog GNDs, especially if different PC boards
are involved. In such cases the digital and analog ground
connection point should not be made right at the “star”
GND area, so the highly sensitive analog signals are not
corrupted. If forced to choose, always place analog ground
quality ahead of digital signal ground. (A few mV of noise
on the digital inputs is imperceptible, thanks to the digital
input hysteresis)
Just by maintaining separate areas on the GND plane
where analog and digital return currents naturally flow,
good results are generally achieved. Only after this has
been done, it is sometimes useful to interrupt the ground
plane with strategically placed “slots”, to prevent the digital
ground currents from fringing into the analog portion of
the plane. When doing this, the gap in the plane should be
only as long as it needs to be to serve its purpose.
Caution: if a GND plane gap is improperly placed, so that
it interrupts a significant GND return path, or if a signal
traces crosses over the gap, then adding the gap may
greatly degrade performance! In this case, the GND and
signal return currents are forced to flow the long way
around the gap, and then are typically channeled directly
into the most sensitive area of the analog GND plane.
26412f
17
LTC2641/LTC2642
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
4
0.25 ± 0.05
0.75 ±0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
PACKAGE TOP MARK
OUTLINE (SEE NOTE 6)
(DD) DFN 1103
5
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
26412f
18
LTC2641/LTC2642
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
0.254
(.010)
7 6 5
0.52
(.0205)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
3.20 – 3.45
(.126 – .136)
1
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
0.65
(.0256)
BSC
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8) 0307 REV F
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.889 ± 0.127
(.035 ± .005)
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
26412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2641/LTC2642
TYPICAL APPLICATION
Wide Range Current Load Sinks 0A to 2.5A
5V
0.1μF
VREF
2.5V
0.1μF
4.7μF
OUT
IN
5V
LT1019CS8-2.5
GND
1
7
REF
VDD
10V
LTC2641-16
2
16-BIT DAC
CS
3
SCLK
4
DIN
5
CLR
VOUT 6
0.1μF
ISINK
0A TO 2.5A
+
1k
IRLZ44
LTC2054HV
–
0.033μF
GND
8
10k
1Ω
10W
26412 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1588/LTC1589
LTC1592
12-/14-/16-Bit SoftSpanTM Current Output DACs
Software Programmable Output Ranges up to ±10V
LTC1595/LTC1596
Serial 16-Bit Current Output DACs
Low Glitch, ±1LSB Maximum INL, DNL
LTC1591/LTC1597
Parallel 14-/16-Bit Current Output DACs
±1LSB Max INL, DNL, ±10V Output
LTC1599
16-Bit Current Output DAC
±1LSB Max INL, DNL, ±10V Output
LTC1650
16-Bit Voltage Output DAC
2nV•s Glitch Impulse, 30nV/√Hz Noise
LTC2621/LTC2611
LTC2601
12-/14-/16-Bit Serial Voltage Output DACs
Single DACs, Single Supply, 0V to 5V Outputs in DFN10
LTC2704-12
LTC2704-14
LTC2704-16
12-/14-/16-Bit Quad Voltage Output DACs
Software Programmable Output Ranges up to ±10V, Serial I/O
LT®1678
Dual Low Noise Rail-to-Rail Precision Op Amp
3.9nV/√Hz at 1MHz
LTC2054
Micropower Zero Drift Op Amp
3μV Maximum Offset
LT6010
150μA 8nV/√Hz Rail-to-Rail Output Precision Op Amp
Micropower
LTC6078
Dual CMOS Rail-to-Rail Input/Output Amplifier
54μA per Amp, 16nV/√Hz Input Noise Voltage
Precision Bandgap Reference
0.005% Max, 5ppm/°C Max
DACs
Op Amps
References
LT1019
SoftSpan is a trademark of Linear Technology Corporation.
26412f
20 Linear Technology Corporation
LT 0707 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
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