STMicroelectronics M58LW064BT 64 mbit x16 and x16/x32, block erase low voltage flash memory Datasheet

M58LW064A
M58LW064B
64 Mbit (x16 and x16/x32, Block Erase)
Low Voltage Flash Memories
PRODUCT PREVIEW
■
M58LW064A x16 organisation,
■
M58LW064B x16/x32 selectable
■
MULTI-BIT CELL for HIGH DENSITY and LOW
COST
■
SUPPLY VOLTAGE
86
1
– VDD = 2.7V to 3.6V Supply Voltage
– VDDQ = 2.7V to 3.6V or 1.8V to 2.5V
Input/Output Supply Voltage
■
PIPELINED SYNCHRONOUS BURST
INTERFACE
■
SYNCHRONOUS/ASYNCHRONOUS READ
TSOP56 (NF)
TSOP86 II (NH)
FBGA
– Synchronous Burst read
– Asynchronous Random and Latch Enabled
Controlled Read, with Page Read
■
– Asynchronous Page Mode Read 150/25ns,
Random Read 150ns
Figure 1. Logic Diagram
VDD VDDQ
PROGRAMMING TIME
– 12us Word effective programming time
MEMORY BLOCKS
A1-A22
W
ELECTRONIC SIGNATURE
E
– Manufacturer Code: 20h
– Device Code M58LW064A: 17h
G
– Device Code M58LW064B: 14h
RP
DESCRIPTION
The M58LW064 is a non-volatile Flash memory
that may be erased electrically at the block level
and programmed in-system on a 16 Word or 8
Double-Word basis using a 2.7V to 3.6V supply for
the circuit and a supply down to 1.8V for the Input
and Output buffers. The M58LW064A is organised
as 4M by 16 bit. The M58LW064B has 4M by 16
bit or 2M by 32 bit organisation selectable by the
Word Organisation WORD input. Both devices are
internally configured as 64 blocks of 1 Mbit each.
DQ0-DQ31
VPP
– 64 Equal blocks of 1 Mbit
■
32
22
– 16 Word or 8 Double-Word Write Buffer
■
LBGA54 (ZA)
ACCESS TIME
– Synchronous Burst Read up to 66MHz
■
PQFP80 (T)
RB
M58LW064A
M58LW064B
R
L
B
K
WORD
(1)
VSS
AI03223
Note: 1. Only on M58LW064B.
May 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/53
M58LW064A, M58LW064B
Table 1. Signal Names
A1-A22
Address Inputs x16 Organisation
A2-A22
Address inputs x32 Organisation
DQ0-DQ7
Data Input/Output x16 and x32
Organisation Command Input,
Electronic Signature Output, Block
Protection Ststus Output, Status
Register Output
DQ8-DQ15
Data Input/Output x16 and x32
Organisation
DQ16-DQ31
Data Input/Output x32 Organisation
B
Burst Address Advance
E
Chip Enable
G
Output Enable
K
Burst Clock
L
Latch Enable
R
Valid Data Ready (open drain output)
RB
Ready/Busy (open drain output)
RP
Reset/Power-down
VPP
Program/Erase Enable
W
Write Enable
WORD
Word Organisation (M58LW064B only)
VDD
Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS
Ground
NC
No internal connection
DU
Don’t Use (internally connected)
The devices support Asynchronous Random and
Latch Enable Controlled Read with Page mode as
well as Synchronous Burst Read with a configurable burst. They also support pipelined synchronous Burst Read. Writing is Asynchronous or
Asynchronous Latch Enable Controlled.
The configurable synchronous burst read interface
allows a high data transfer rate controlled by the
2/53
Burst Clock K signal. It is capable of bursting fixed
or unlimited lengths of data. The burst type, latency and length are configurable and can be easily
adapted to a large variety of system clock frequencies and microprocessors. A 16 Word or 8 DoubleWord Write Buffer improves effective programming speed by up to 20 times when data is programmed in full buffer increments. Effective Word
programming takes typically 12µs. The array matrix organisation allows each block to be erased
and reprogrammed without affecting other blocks.
Program and Erase operations can be suspended
in order to perform either Read or Program in any
other block and then resumed. All blocks are protected against spurious programming and erase
cycles at power-up. Any block can be separately
protected at any time. The block protection bits
can also be deleted, this is executed as one sequence for all blocks simultaneously. Block protection can be temporarily disabled. Each block can
be programmed and erased over 100,000 cycles.
Block erase is performed in typically 1 second.
An internal Command Interface (C.I.) decodes Instructions to access/modify the memory content.
The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the
timings required by the program and erase operations. Verification is internally performed and a
Status Register tracks the status of the operations.
The Ready/Busy output RB indicates the completion of operations.
Instructions are written to the memory through the
Command Interface (C.I.) using standard microprocessor write timings. The device supports the
Common Flash Interface (CFI) command set definition.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consumption is lower than in the normal standby mode, the
device is write protected and both the Status and
the Burst Configuration Registers are cleared. A
recovery time is required when the RP input goes
High.
The device is offered in various package versions,
TSOP56 (14 x 20 mm), TSOP86 Type II (11.76 x
22.22 mm) and LBGA54 1mm ball pitch for the
M58LW064A and PQFP80 for the M58LW064B.
M58LW064A, M58LW064B
Figure 2. TSOP56 Connections
A22
R
A21
A20
A19
A18
A17
A16
VDD
A15
A14
A13
A12
E
VPP
RP
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
1
56
Figure 3. TSOP86 Type II Connections
NC
W
G
RB
14
43
M58LW064A
15
42
28
29
AI03224
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VDDQ
VSS
DQ11
DQ3
DQ10
DQ2
VDD
DQ9
DQ1
DQ8
DQ0
B
K
NC
L
VPP
RP
A11
A10
A9
A8
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
NC
NC
DQ16
DQ24
DQ17
DQ25
DQ18
DQ26
DQ19
DQ27
L
K
B
DQ0
DQ8
DQ1
DQ9
VDD
VDD
DQ2
DQ10
DQ3
DQ11
VSS
VSS
1
86
21
66
M58LW064A
22
65
43
44
E
A12
A13
A14
A15
VDD
VDD
A16
A17
A18
A19
A20
A21
R
A22
WORD
NC
NC
NC
DQ31
DQ23
DQ30
DQ22
DQ29
DQ21
DQ28
DQ20
W
G
RB
DQ15
DQ7
DQ14
DQ6
VSS
VSS
DQ13
DQ5
DQ12
DQ4
VDDQ
VDDQ
VDDQ
AI03634
3/53
M58LW064A, M58LW064B
Figure 4. LBGA Connections for M58LW064A (Top view through package)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPP
A13
VDD
A18
A22
B
A2
VSS
A9
E
A14
A19
R
C
A3
A7
A10
A12
A15
A20
A21
D
A4
A5
A11
RP
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
DQ15
R/B
F
K
DQ0
DQ10
DQ11
DQ12
B
DQ2
VDDQ
DQ5
DQ6
DQ14
VDD
VSS
DQ13
VSS
DQ7
G
H
L
G
W
AI03536
4/53
M58LW064A, M58LW064B
VSS
A8
A9
A10
A11
RP
VPP
E
A12
A13
A14
A15
VDD
A16
A17
A18
Figure 5. PQFP Connections
1
12
73
M58LW064B
53
32
A19
A20
A21
R
A22
WORD
NC
NC
NC
DQ31
DQ23
DQ30
DQ22
DQ29
DQ21
DQ28
DQ20
W
G
RB
DQ15
DQ7
DQ14
DQ6
DQ1
DQ9
VDD
DQ2
DQ10
DQ3
DQ11
VSS
VDDQ
VDDQ
DQ4
DQ12
DQ5
DQ13
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
DQ16
DQ24
DQ17
DQ25
DQ18
DQ26
DQ19
DQ27
L
NC
K
B
DQ0
DQ8
AI03546
5/53
M58LW064A, M58LW064B
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature
Value
Unit
Grade 1
0 to 70
°C
Grade 6
–40 to 85
TBIAS
Temperature Under Bias
–40 to 125
°C
TSTG
Storage Temperature
–55 to 150
°C
–0.6 to VDDQ +0.6
V
–0.6 to 5.0
V
–0.6 to 10 (2)
V
VIO
V DD, VDDQ
VHH
Input or Output Voltage
Supply Voltage
RP Hardware Block Unlock Voltage
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Cumulative time at a high voltage level of 10V should not exceed 80 hours on RP pin.
6/53
M58LW064A, M58LW064B
Figure 6. Memory Map
M58LW064A, M58LW064B
Word (x16) Organisation
Address lines A1-A22
3FFFFFh
3F0000h
1Mbit or
64 KWords
M58LW064B
Double-Word (x32) Organisation
Address lines A2-A22
(A1 is Don’t Care)
1FFFFFh
1F8000h
x64
01FFFFh
010000h
00FFFFh
000000h
1Mbit or
64 KWords
1Mbit or
64 KWords
1Mbit or
32 KDouble-Words
x64
00FFFFh
008000h
007FFFh
000000h
1Mbit or
32 KDouble-Words
1Mbit or
32 KDouble-Words
AI03228
ORGANISATION
Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Latch
Enable L input latches an address for both Read
and Write operations. The Burst Clock K and the
Burst Address Advance B inputs synchronize the
memory to the microprocessor during burst read.
Reset/Power-down RP is used to reset all the
memory circuitry, excluding the block protection
bits, and to set the chip in deep power down mode.
Erase and Program operations are controlled by
an internal Program/Erase Controller (P/E.C.). A
Status Register data output on DQ7 provides a
Ready/Busy signal to indicate the state of the P/
E.C. operations. A Ready/Busy RB output also indicates the completion of the internal algorithms. A
Valid Data Ready R output indicates the memory
data output valid status during the synchronous
burst mode operations.
A Word Organisation WORD input selects the x16
or x32 data width for the M58LW064B. For the x16
only organisation of the M58LW064A or the x16
organisation of the M58LW064B the address lines
are A1-A22 and the Data Input/Output is on DQ0DQ15. For the x32 organisation of the
M58LW064B the address lines are A2-A22 and
the Data Input/Output is DQ0-DQ31.
MEMORY BLOCKS
The device has a uniform block architecture with
an array of 64 separate blocks of 1Mbit each. The
memory features a software erase suspend of a
block allowing read or programming within any
other block. A suspended erase operation can be
resumed to complete block erasure. A program
suspend operation on a block allows reading only
within any other block. A suspend program operation can be resumed to complete programming. At
any moment of the sequence the Status Register
indicates the status of the operation.
Each block is erased separately. An Erase or Program operation is managed automatically by the
P/E.C. Individual block protection against Program
or Erase provides additional data security. All
blocks are protected during power-up. A software
instruction is provided to cancel all block protection bits simultaneously in an application and a
higher level input on RP can temporarily disable
the protection mechanism. A software instruction
is provided to allow protection of some or all of the
blocks in an application. All Program or Erase operations are blocked when the Program/Erase Enable input VPP is Low.
7/53
M58LW064A, M58LW064B
BUS OPERATIONS
The following operations can be performed using
the appropriate bus configuration:
Asynchronous
– Read Array
– Read Electronic Signature
– Read Block Protection
– Read Status Register
– Read Query
– Write
– Output Disable
– Standby
– Reset/Power-down
Synchronous
– Address Latch
– Burst Read
– Burst Read Suspend
– Burst Read Interrupt
– Burst Read Resume
– Burst Address Advance
See Tables 3, 4, 5, 6 and 7.
COMMAND INTERFACE
Instructions, made up of Commands written in Cycles, can be given to the Program/Erase Controller
(P/E.C.) by writing to the Command Interface
(C.I.). At power-up or on exit from power down or
if V DD is lower than VLKO, the Command Interface
is reset to Read Array. Any incorrect command will
reset the device to Read Array. Any improper command sequence will cause the Status Register to
report the error condition and the device will default to Read Status Register.
The internal Program/Erase Controller (P/E.C.)
automatically handles all timing and verification of
the Program and Erase operations. The Status
Register information P/ECS on DQ7 can be read
at any time, during programming or erase, to monitor the progress of the operation.
Table 3. Asynchronous Bus Operations (1)
Operation
E
G
W
RP
L
DQ0-DQ31
Read Array
VIL
V IL
VIH
High
X
Data Output
Read Electronic Signature or
Block Protection Status
VIL
V IL
VIH
High
X
Manufacturer or Device Code
Output Block Protection Status
Read Status
P/E.C. Active
VIL
V IL
VIH
High
X
Status Register Output
Read Query
VIL
V IL
VIH
High
X
CFI Query Output
Write
VIL
VIH
V IL
High
VIL
Data Input
Output Disable
VIL
VIH
VIH
High
X
High Z
Standby
VIH
X
X
High
X
High Z
X
X
X
VIL
X
High Z
Reset/Power-down
Note: 1. X = Don’t Care VIL or V IH. High = VIH or VHH.
2. ? = need to check with designers - X or VIL???
8/53
M58LW064A, M58LW064B
Table 4. Synchronous Burst Read Operations (1)
E
G
RP
K
L
B
A1-A22
DQ0-DQ31
Address Latch
VIL
V IH
VIH
_/
VIL
VIH
Addess Input
Burst Read
VIL
VIL
VIH
_/
VIH
VIH
Data Output
Burst Read Suspend
VIL
V IH
VIH
X
VIH
VIH
High Z
Burst Read Interrupt (E)
VIH
X
VIH
X
VIH
VIH
High Z
X
X
VIL
X
X
X
High Z
Burst Read Resume
VIL
VIL
VIH
_/
VIH
V IL
Data Output
Burst Address Advance
VIL
V IH
VIH
_/
VIH
V IL
High Z
No Data Output Burst Address
Advance with valid Data Output
VIL
VIL
VIH
_/
VIH
V IL
Data Output
Operation
Burst Read Interrupt (RP)
Note: 1. X = Don’t Care, VIL or VIH.
2. ? need to check with designers for various X and clock _/ definitions
Table 5. Asynchronous Read Electronic Signature Operation
Code
Device
E
G
W
A22-A1
A22-A2
DQ7-DQ0
Manufacturer
All
VIL
VIL
V IH
00000h
00000h
20h
M58LW064A
VIL
VIL
V IH
00001h
–
17h
M58LW064B (1)
VIL
VIL
V IH
–
00001h
14h
Device
Note: 1. For M58LW064B, A1 = Dont’Care
Table 6. M58LW064A CFI Block Protection Status Query Operation (1)
Block Status
E
G
W
A1
A2
A3-A16
A17-A22
DQ7-DQ0
Protected
VIL
VIL
VIH
V IH
VIH
X
Block Address
01h
Unprotected
VIL
VIL
VIH
V IH
VIH
X
Block Address
00h
Note: 1. X = Dont’Care, VIL or VIH.
Table 7. M58LW064B CFI Block Protection Status Query Operation (1)
Block Status
E
G
W
A1
A2
A3
A4-A16
A17-A22
DQ7-DQ0
Protected
VIL
V IL
VIH
X
VIH
VIH
X
Block Address
01h
Unprotected
VIL
V IL
VIH
X
VIH
VIH
X
Block Address
00h
Note: 1. X = Dont’Care, VIL or VIH.
9/53
M58LW064A, M58LW064B
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A1-A22). A1 is used to select
between the high and low Word in the x16 configuration of the M58LW064A or B. For the
M58LW064B A1 is not used in the x32 mode.
When Chip Enable E is at VIL the address bus is
used to input addresses for the memory array in
Read mode, or addresses for the data to be programmed, or to input addresses associated with
Commands to be written to the Command Interface. The address latch is transparent when Latch
Enable L is at VIL. The address inputs for the
memory array are latched on the rising edge of
Chip Enable E or Latch Enable L or Write Enable
W, whichever occurs first in a write operation. The
address is also internally latched in the command
for an Erase or Program Instruction.
Data Inputs/Outputs (DQ0-DQ31). Input
data
for a Write to Buffer and Program operation and for
writing Commands to the Command Interface are
latched on the rising edge of Write Enable W or
Chip Enable E, whichever occurs first.
When Chip Enable E and Output Enable G are at
VIL data is output from the Array, the Electronic
Signature - the Manufacturer and the Device code
- the Block Protection status, the CFI Query information or the Status Register. The data bus is high
impedance when the device is deselected with
Chip Enable E at VIH, Output Enable G is at VIH or
RP is at VIL. When the P/E.C. is active the Status
Register content is output on DQ0-DQ7 and DQ8DQ31 are at VIL.
Chip Enable (E). The Chip Enable E input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable E at VIH
deselects the memory and reduces the power consumption to the standby level.
Output Enable (G). The Output Enable G gates
the outputs through the data output buffers during
a read operation. When Output Enable G is at VIH
the outputs are high impedance. Output Enable G
can be used to suspend the data output in a burst
read operation.
10/53
Write Enable (W). The Write Enable W input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of W (see also
Latch Enable L).
Reset/Power-down (RP). The
Reset/Powerdown RP input provides a hardware reset of the
memory and power-down functions. Reset/Powerdown of the memory is achieved by pulling RP to
VIL for at least tPLPH. Writing is inhibited to protect
data, the Command Interface and the P/E.C. are
reset. The Status Register information is cleared
and power consumption is reduced to deep powerdown level. The device acts as deselected, that is
the data outputs are high impedance.
When RP rises to VIH, the device will be available
for new operations after a delay of tPHQV and will
be configured by default for Asynchronous Random Read. The minimum delay required to access
the Command Interface by a write cycle is tPHWL.
If the RP input is activated during a Block Erase, a
Write to Buffer and Program or a Block Protect/Unprotect operation the cycle is aborted and data is
altered and may be corrupted. The Ready/Busy
output RB may remain low for a maximum time of
tPLPH + tPHRH beyond the completion of the Reset/
Power-down RP pulse.
Applying the higher voltage VHH to the Reset/Power-down input RP temporarily unprotects and enables Erase and Program operations on all blocks.
Thus it acts as a hardware block unprotect input.
In an application, it is recommended to associate
RP to the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the device
is performing an Erase or Program cycle, the
Flash memory may output the Status Register information instead of being re-initialized to the default Asynchronous Random Read.
Latch Enable (L). Latch Enable L latches the address bits A1-A22 on its rising edge for the Asynchronous Latch Enable Controlled Read or Write,
or Synchronous Burst Read operations. The address latch is transparent when Latch Enable L is
at VIL. Latch Enable L must remain at VIL for Asynchronous Random Read and Write operations.
M58LW064A, M58LW064B
Burst Clock (K). The Burst Clock K is used only
in burst mode. It is the fundamental synchronous
signal that allows internal latching of the address
from the address bus, together with Latch Enable
L; increment of the internal address counter in association with Burst Address Advance B; and to indicate valid data on the external data bus. All
these operations are synchronously controlled on
the valid edge of the Burst Clock K, which can be
selected to be the rising or falling edge depending
on the definition in the Burst Configuration Register.
For Asynchronous Read or Write, the Burst Clock
K input level is Don’t Care. For Synchronous Burst
Read the address is latched on the first valid clock
edge when Latch Enable L is at VIL, or the rising
edge of Latch Enable L, whichever occurs first.
Burst Address Advance (B). Burst Address Advance B enables increment of the internal address
counter when it falls to VIL during Synchronous
Burst Read. It is sampled on the last valid edge of
the Burst Clock K at the expiry of the X-latency
time. If sampled at VIL, new data will be output on
the next Burst Clock K valid edge (or second next
depending on the definition in the Burst Configuration Register). If it is at VIH when sampled, the previous data remains on the Data Outputs. The Burst
Address Advance B may be tied to VIL.
Ready (R). The Valid Data Ready R is an output
signal used during Synchronous Burst Read. It indicates, at the valid clock edge (or one cycle before depending on the definition in the Burst
Configuration Register), if valid data is ready on
the Data Outputs. New Data Outputs are valid if
Valid Data Ready R is at VIH, the previous Data
Outputs remain active if Valid Data Ready R is at
VIL.
In all operations except Burst Read, Valid Data
Ready R is at V IH. It may be tied to other components with the same Valid Data Ready R signal to
create a unique system Ready signal. The Valid
Data Ready R output has an internal pull-up resistor of around 1 MΩ powered from VDDQ, designers
should use an external pull-up resistor of the correct value to meet the external timing requirements for R going to VIH.
Word Organisation (WORD). The Word Organisation WORD input is present only on the
M58LW064B and selects x16 or x32 organisation.
The WORD input selects the data width as Word
wide (x16) or Double-Word wide (x32). When
WORD is at VIL, Word-wide x16 width is selected
and data is read and programmed on DQ0-DQ15,
DQ16-DQ31 are at high impedance and A1 is the
LSB address. When WORD is at VIH, the DoubleWord wide x32 width is selected and the data is
read and programmed on DQ0-DQ31, and A2 is
the LSB address.
Ready/Busy (RB). Ready/Busy RB is an opendrain output and gives the internal state of the P/
E.C. When Ready/Busy RB is at VIL the device is
busy with a Program or Erase operation and it will
not accept any additional program or erase instructions except for the Program or Erase Suspend instructions. When a Program or Erase
Suspend is given the RB signal rises to VIH, after
a latency time, to indicate that the Command Interface is ready for a new instruction. When RB is at
VIH, the device is ready for any Read, Program or
Erase operation. Ready/Busy RB is also at VIH
when the memory is in Erase/Program Suspend or
Standby modes.
Program/Erase Enable (VPP). Program/Erase
Enable VPP automatically protects all blocks from
programming or erasure when at VIL.
Supply Voltage (VDD). The Supply Voltage VDD
is the main power supply for all operations (Read,
Program and Erase).
Input/Output Supply Voltage (VDDQ). The Input/Output Supply Voltage VDDQ is the Input and
Output buffer power supply for all operations
(Read, Program and Erase).
Ground (V SS). Ground VSS is the reference for all
the voltage measurements.
11/53
M58LW064A, M58LW064B
DEVICE OPERATIONS
See Tables 5, 6, 7 and 10.
Address Latch. An address is latched on the rising edge of the Latch Enable L input for Asynchronous Latch Enable Controlled Read. For
Asynchrouns Latch Enable Controlled Write, the
address is latched on the rising edge of Chip Enable E, Write Enable W or Latch Enable L, whichever occurs first.
For Synchronous Burst Read the address is
latched on the first valid Burst Clock K edge when
Latch Enable L is at Low, or on the rising edge of
Latch Enable L, whichever occurs first.
Asynchronous Random Read. Asynchronous
Random Read outputs the contents of the Array.
Both Chip Enable E and Output Enable G must be
Low in order to read the output of the memory.
By first writing the appropriate Instruction, the
Electronic Signature (RSIG), the Status Register
(RSR), the Read Query Instruction (RCFI) or the
Block Protection Status (RSIG) can be read.
Asynchronous Random Read is the default read
mode which the device enters on power-up or on
return from Reset/Power-down.
Asynchronous Page Read. Asynchronous
Page Read may be used for Random or Latch Enable Controlled Reads of the Array, which are performed independent of the Burst Clock signal. A
page has a size of 4 Words or 2 Double-Words
and is addressed by the address inputs A1 and A2
in the x16, or A2 only in the x32 organisation. Data
is read internally and stored in the Page Buffer.
The page read starts when both Chip Enable E
and Output Enable G are Low. The first data is internally read and is output after the normal access
time tAVQV. Successive Words or Double-Words
can be read with a much reduced access time of
tAVQV1 by changing only the low address bits.
Synchronous Burst Read. The memory supports different types of burst access using a Burst
Configuration Register to configure the burst type,
length and latency.
In continuous burst read, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B Low for the
appropriate number of clock cycles. At the end of
the memory address space the burst read restarts
from the beginning at address 000000h.
Synchronous Burst Read is activated when the
Burst Clock K input is clocking and Chip Enable E
is Low. The burst start address is latched and
loaded into the internal Burst Address Counter on
the valid Burst Clock K edge (rising or falling depending on the M6 bit value for the Burst Clock
Edge Configuration in the Burst Configuration
Register) when Latch Enable L is Low, or upon the
rising edge of Latch Enable L when the Burst
12/53
Clock K is valid. After an initial memory latency
time, the memory outputs data each clock cycle
(or two clock cycles depending on M9 bit value defined in the Burst Configuration Register). The
Burst Address Advance B input controls the memory burst output. The second burst output is on the
next clock valid edge after the Burst Address Advance B has been pulled Low.
The Valid Data Ready output signal R monitors if
the memory burst boundary is exceeded and the
Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready R is Low
on the active clock edge, no new data is available
and the memory does not increment the internal
address counter at the active clock edge even if
Burst Address Advance B is Low.
Synchronous Burst Read will be suspended when
Burst Address Advance B is High. The Valid Data
Ready signal R may be configured (by bit M8 of
Burst Configuration Register) to be valid immediately at the valid clock edge or one data cycle before the valid clock edge.
To increase the data throughput the device has
been built with an internal pipelined architecture
allowing the user to enter a burst read input command and the next starting address location to be
read while the device is filling the output data bus
with its current burst content. This pipelined structure is intended to produce no wait-states on the
output data bus for successive burst read mode
operations.
Asynchronous and Latch Enable Controlled
Write. Asynchronous Write is used to give commands to the Command Interface for Instructions
to the memory or to latch addresses and input data
to be programmed. To perform any Instruction the
Command Interface is activated starting with a
write cycle. A write cycle is also required give the
Instruction to clear the Status Register information. Two write cycles are needed to define the
Block Erase and the Write to Buffer and Program
Instructions. The first write cycle defines the Instruction selection and the second indicates the
appropriate block address to be erased for the
Block Erase instruction, or the address locations to
program with the number of Words or DoubleWords in the Write to Buffer and Program Instruction.
An Asynchronous Write is initiated when Chip Enable E, Write Enable W and Latch Enable L are
Low with Output Enable G High. Commands and
Input Data are latched on the rising edge of Chip
Enable E or Write Enable W, whichever occurs
first. For an Asynchronous Latch Enable Controlled Write the address is latched on the rising
edge of Latch Enable L, Write Enable W or Chip
Enable E, whichever occurs first.
M58LW064A, M58LW064B
Data to be programmed in the array is internally
latched in the Write Buffer before the programming
operation starts and a minimum of 4 Words or 2
Double-Words need to be programmed in the
same sequence and must be contained in the
same address location boundary defined by A1 to
A2 for the x16 and A2 for the x32 organisation.
Write operations are asynchronous and the Burst
Clock signal K is ignored during a write operation.
Output Disable. The data outputs are high impedance when the Output Enable G is High.
Standby. The memory is in standby when Chip
Enable E goes High and the P/E.C. is idle. The
power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Low Power. After a short time of bus
inactivity (no Chip Enable E, Latch Enable L or Address transitions) the chip automatically enters a
pseudo-standby mode where consumption is reduced to the Automatic Low Power standby value,
while the outputs may still drive the bus. The Automatic Low Power feature is available only for
Asynchronous Read.
Power-down. The memory is in Power-down
when Reset/Power-down RP is Low. The power
consumption is reduced to the power-down level
and the outputs are high impedance, independent
of the Chip Enable E, Output Enable G or Write
Enable W inputs.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory allowing programming equipment or applications to automatically match their interface to
the characteristics of the memory. The Electronic
Signature is output by giving the RSIG Instruction.
The manufacturer code is output when all the Address inputs are Low. The device code is output
when A1 (M58LW064A) or A2 (M58LW064B) input is High, the other pins A3-A22 must be Low.
The codes are output on DQ0-DQ7. A return to
Read mode is achieved by writing the Read Array
instruction.
INITIALIZATION
The device must be powered up and initialized in
a predefined manner. Procedures other than
specified may result in undefined operation.
Power should be applied simultaneously to VDD
and VDDQ with the RP input held Low. When the
supplies are stable RP is taken High. The Output
Enable G, Chip Enable E and Write Enable W inputs should also be held High during power-up.
The memory will be ready to accept the first Instruction after the power-up time tPUR. The device
is automatically configured for Asynchronous Random Read at power-up or after leaving Reset/
Power-down.
BURST CONFIGURATION REGISTER
See Tables 8, 9, 10 and 11.
The Synchronous Burst Read, Asynchronous
Random Read, Asynchronous Latch Enable Controlled Read are selected using the Burst Configuration Register.
For Synchronous Read the register defines the X
and Y Latencies, Valid Data Ready signal timing,
Burst Type, Valid Clock Edge and Burst Length.
The Burst Configuration Register is programmed
using the Set Burst Configuration Register (SBCR)
Instruction and will retain the stored information
until it is programmed again or the device is reset
or goes into the Reset/Power-down.
The Burst Configuration Register bits M2-M0
specify the burst length (1, 2, 4, 8 or continuous);
bit M3 specifies Asynchronous Random Read or
Asynchronous Latch Enable Controlled Read; bits
M4 and M5 are not used; bit M6 specifies the rising
or falling burst clock edge as valid; bit M7 specifies
the burst type (Sequential or Interleaved); M8
specifies the Valid Data Ready output period; bit
M9 specifies the Y-latency; bit M10 is not used;
M14-M11 specify the X-latency; and bit M15 selects between Synchronous Burst Read or Asynchronous Read. M10, M5 and M4 are reserved for
future use.
M15 Read Select
The device features three kinds of read operation:
Asynchronous Random Read, Asynchronous
Latch Enable Controlled Read and Synchronous
Burst Read. Page Read may be used in either of
the Asynchronous Read operations.
The Burst Configuration Register bit M15 selects
between Synchronous Burst and Asynchronous
Read.
M14 - M11 and M9 X and Y Latency.
The values of X and Y are used to define the burst
latency for the data sequence. The X-latency defines the number of clock cycles before the output
of the first data from the clock edge that latches
the address. The X-latency can be set from 7 to
16. A value of 7 is only valid for continuous burst.
The Y-latency is the number of clock cycles needed to output the next data from the burst register,
following the first data output. The latency can be
set to 1 or 2 clock cycles.
The minimum X-Latency value to consider depends on the Burst Clock K signal frequency. The
burst performance in terms of frequency is listed in
Table 11 and indicates the minimum X-latency and
Y-latency values (X.Y.Y.Y) related to the burst
type, burst length and x16 or x32 organisation.
13/53
M58LW064A, M58LW064B
M8 Valid Data Ready R Signal Configuration.
The Valid Data Ready R output signal indicates
when valid data is on the data outputs synchronous with the valid burst clock egde. It can be asserted by the device synchronously with the valid
clock edge or one clock cycle before.
M7 Burst Type.
Accesses within a given burst may be programmed to be either Sequential or Interleaved.
This is referred to as the burst type and is selected
by the Burst Configuration Register M7 bit. The access order within a burst is determined by the
burst length, the burst type and the starting address (See Table 8).
M6 Valid Clock Edge Configuration.
All the synchronous operations such as Burst
Read, Output Data or Ready signal validation can
be synchronized on the valid rising or on the falling
edge of the Burst Clock signal K.
M2 - M0 Burst Length.
Synchronous reads have a programmable burst
length, set using the M2 - M0 bits of the Burst Configuration Register. The burst length corresponds
to the maximum number of Words or DoubleWords that can be output. Burst lengths of 1, 2, 4
or 8 are available for both the Sequential and Interleaved burst types, and a continuous burst is
available for the Sequential type. The burst length
of 8 is not available in the x32 configuration.
When a Read command is issued, a block of
Words or Double-Words equal to the burst length
is selected. All accesses for that burst take place
14/53
within this block, meaning that the burst wraps
within the burst block if a boundary is reached.
If a Continuous Burst Read has been initiated the
device will output data synchronously. Depending
on the starting address of the read, the device activates the Valid Data Ready R output to indicate
that it needs a delay to complete the internal read
operation before outputing data. If the starting address is aligned to a four Word boundary the continuous burst mode will run without activating the
Valid Data Ready R output. If the starting address
is not aligned to a four Word boundary, Valid Data
Ready R is activated at the beginning of the continuous burst read to indicate that the device
needs an internal delay to read the content of the
four successive words in the array.
Pipelined Burst Read.
An overlapping Burst Read operation is possible.
That is, the address and data phases of consecutive synchronous read operations can be overlapped by several clock cycles. This is done by
applying a pulse on Latch Enable L input to latch a
new address before the completion of the data
output of the current cycle. This reduces or avoids
wait-states in the data output for the burst read
mode. The minimum clock edge number for the
following read sequence must be six before the
last data output of the previous read cycle. The
pipelined burst read mode is available in the x16
organisation for both burst length definitions of
four and eight, and in the x32 organisation for the
burst length of four. It is not possible for a burst
length of one or two.
M58LW064A, M58LW064B
Table 8. Burst Type Definition (x16 mode)
Burst Length
Starting Address
(binary)
Sequential
(decimal)
Interleaved
(decimal)
0-0-0
0-1
0-1
0-0-1
1-0
1-0
0-0-0
0-1-2-3
0-1-2-3
0-0-1
1-2-3-0
1-0-3-2
0-1-0
2-3-0-1
2-3-0-1
0-1-1
3-0-1-2
3-2-1-0
0-0-0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0-0-1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0-1-0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0-1-1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1-0-0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1-0-1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1-1-0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1-1-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Sequential
(decimal)
Interleaved
(decimal)
0-0
0-1
0-1
0-1
1-0
1-0
0-0
0-1-2-3
0-1-2-3
0-1
1-2-3-0
1-0-3-2
1-0
2-3-0-1
2-3-0-1
1-1
3-0-1-2
3-2-1-0
A3-A2-A1
2
4
8
Table 9. Burst Type Definition (x32 mode)
Burst Length
Starting Address
(binary)
A2-A1
2
4
15/53
M58LW064A, M58LW064B
Table 10. Burst Configuration Register (1)
BCR mode bit
M15
M14-M11
M9
M8
M7
M6
M3
M2-M0
Description
Value
Description
0
Synchronous Burst Read
1
Asynchronous Read
0001
Reserved
0010
7, only for F K = 33MHz (5)
0011
8, only for F K = 33MHz
0100
9, only for F K = 33MHz
0101
10, only for FK = 50MHz (6)
0110
11, only for FK = 50MHz (7)
1001
12, only for FK = 50MHz
1010
13, only for FK = 50MHz
1011
14, only for FK = 66MHz (8)
1101
16, only for FK = 66MHz
0
One Burst Clock cycle
1
Two Burst Clock cycles
0
R valid Low during valid Burst Clock edge
1
R valid Low one data cycle before valid Burst Clock edge
0
Interleaved
1
Sequential
0
Falling Burst Clock edge
1
Rising Burst Clock edge
0
Random Read
1
Latch Enable Controlled Read
100
1 Word or Double-Word
101
2 Words or Double-Words
001
4 Words or Double-Words
010
8 Words or Double-Words (3)
111
Continuous
Read Select
X-Latency (4)
Y-Latency (4)
Valid Data Ready
Burst Type
Valid Clock Edge
Asynchronous
Burst Length (2)
Note: 1. The BCR defines both the read mode and the burst configuration.
2. Synchronous burst length is defined as Word or Double-Word, the data bus width depends only on the WORD input.
Asynchronous Page read is two Words or one Double-Word.
3. A burst length of 8 is not available for x32 organisation.
4. At FK > 50MHz when X-Latency = 10 or 12, Y-Latency = 2 independent of the value of M9.
At FK = 66MHz when X-Lantency = 14 or 16, Y-Latency = 2 indepedent of the value of M9.
5. Latency 7 valid only for continuous burst. Otherwisw Latency = 8.
6. Latency 10 valid only for continuous burst. Otherwisw Latency = 12.
7. Latency 11 valid only for continuous burst. Otherwisw Latency = 12.
8. Latency 14 valid only for continuous burst. Otherwisw Latency = 16.
16/53
M58LW064A, M58LW064B
Table 11. Burst Performance (1)
X-Y Latencies (minimum)
x16 organisation
x32 organisation
x16
organisation
x32
organisation
Clock
Frequency
Sequential
Interleaved
Sequential
Interleaved
VDD = 2.7 to 3.6V
Burst length:
1,2,4,8
Burst length:
1,2,4,8
Burst length:
1,2,4
Burst length:
1,2,4
Continuo us Burst
8.1.1.1
8.1.1.1
8.1.1.1
8.1.1.1
7.1.1.1
7.1.1.1
≤ 33 MHz
12.1.1.1
12.1.1.1
12.1.1.1
12.1.1.1
10.1.1.1
10.1.1.1
≤ 50 MHz
t.b.a.
t.b.a.
t.b.a.
t.b.a.
t.b.a.
t.b.a.
≤ 60 MHz
16.2.2.2
16.2.2.2
16.2.2.2
16.2.2.2
14.2.2.2
14.2.2.2
≤ 66 MHz
Note: 1. The burst length of 8 is not available in the x32 organisation.
17/53
M58LW064A, M58LW064B
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands written to the memory. Instructions are made up of
one or more commands to perform:
– Read Array (RD),
– Read Electronic Signature or Read Block Protection (RSIG),
– Read Status Register (RSR),
– Read Query (RCFI),
– Clear Status Register (CLRS),
– Block Erase (EE),
– Write to Buffer and Program (WBPR),
– Erase/Program Suspend (PES),
– Erase/Program Resume (PER),
– Set Burst Configuration Register (SBCR),
– Block Protect (BP), and
– Block Unprotect (BU).
Instructions (see Table 12) are composed of a first
write sequence followed by either a second write
sequence needed to confirm an Erase or Program
instruction or by a read operation in order to read
data from the array, the Electronic Signature, the
Block Protection information, the CFI or the Status
Register information. The instructions for Write to
Buffer and Program and Block Erase operations
consist of two commands written into the memory
Command Interface (C.I.) that start the automatic
P/E.C. operation. Erasure of a memory block may
be suspended, in order to read data from or to program data in an other block, and then be resumed.
Write to Buffer and Program operation may be
suspended, in order to read data from another
block, and then be resumed.
At power-up the Command Interface is reset to
Read Array. The appropriate Instruction must be
given to access Read Query (RCFI), Read Electronic Signature or Block Protection Status (RSIG)
or Read Status Register (RSR). Reading of the
memory array is disabled during a Block Protect/
Unprotect (BP, BU), a Block Erase (EE) or a Write
to Buffer and Program (WBPR) Instruction. A
Erase/Program Suspend Instruction (PES) must
be given to read under these conditions.
Read Array Instruction (RD). The Read Array
Instruction consists of one write cycle giving the
command FFh. Subsequent read operations will
read the array content addressed and output the
corresponding data. The Read Array Instruction
remains active until another one is written into the
Command Interface. At Power-up or at the exit of
the Reset/Power-down mode, the device is by default initialised to Read Array.
18/53
Read Electronic Signature Instruction (RSIG).
An Electronic Signature can be read from the
memory allowing programming equipment or applications to automatically match their interface to
the characteristics of the device.
The Electronic Signature instruction consists of a
first write cycle giving the command 90h, followed
by a subsequent read which will output the Manufacturer Code, the Device Code or the Block Protection Status. The Manufacturer Code is output
when all the address inputs are at VIL. The Device
Code is output when A1 (for the M58LW064A) or
A2 (for the M58LW064B) is at VIH, with all other
address inputs at VIL. The code is output on DQ0DQ7 with DQ8-DQ31 at VIL.
The RSIG Instruction also allows access to the
Block Protection Status for the selected block address defined by A17-A22. After the Read Electronic Signature (RSIG) command, A1-A2 (for the
M58LW064A) or A2-A3 (for the M58LW064B) are
set to VIH, while A17-A22 define the address of the
block to be queried. A read operation outputs 01h
if the block is protected and 00h if the block is not
protected.
Read Query Instruction (RCFI). The Read Query Instruction is initiated with one write cycle giving
the command 98h at any address. Subsequent
read operations, depending on the address specified, will output the Block Status information, the
Common Flash Interface ID string, the System Interface information, the Device Geometry Configuration or STMicroelectronics Specific Query
information. The address mapping for the information is shown in Table 14.
Read Status Register Instruction (RSR). The
Read Status Register Instruction consists of one
write cycle giving the command 70h. Subsequent
read operations, independent of the address, output the Status Register information that indicates if
a Block Erase, Write to Buffer and Program, Block
Protect or Block Unprotect operation has been
completed successfully. See Table 12. Once initiated the RSR Instruction is active until another
command is given to the Command Interface.
For Asynchronous Read, the Status Register information is present on the output data bus when
both Chip Enable E and Output Enable G are Low.
In Synchronous Burst Read the Status Register information is output on the data bus DQ1-DQ7
when Latch Enable L goes High or on a valid Burst
Clock K edge (M6 in the Burst Configuration Register specifies the rising or falling valid clock edge)
when Latch Enable L is low. An interactive update
of the status register information is possible by
toggling Output Enable G, or when the device is
M58LW064A, M58LW064B
Table 12. Instructions
Mnemonic
1st Cycle
Instruction
2nd Cycle
Cycles
Comments
Op.
Address
Data
1+
Write
X
FFh
Read
RSIG Manufacturer
Code
≥2
Write
X
90h
Read
000000h
20h
Read Manufacturer Code
Read Device
Code or Block
RSIG Protection
Status
≥2
Write
X
90h
Read
IAh
IDh
Read Device ID Code
2
Write
X
70h
Read
X
SRDh
SRD = Status Register
Data
≥2
Write
X
98h
Read
QAh
QDh
QA = Query Address
QD = Query Data
Clear Status
Register
1
Write
X
50h
Block
Erase
2
Write
X
20h
Write
BAh
D0h
BA = Block Address to
erase
Write
WBPR to Buffer and
Program
≥2
Write
BAh
E8h
Write
BAh
N
BA = Block Address
N = Word/Double-Word
Count Argument
Erase/
Program
Suspend
1
Write
X
B0h
Erase/
PER Program
Resume
1
Write
X
D0h
2
Write
BCRh
60h
RD
RSR
Read Array
Read Status
Register
RCFI Read Query
CLRS
EE
PES
Set Burst
SBCR Configuration
Register
Op.
Address
Data
Read Array until a new
write cycle is initiated
Confirm command for
Write to Buffer and
Program instruction
Write
BCRh
03h
BCR = Burst Configuration
Register
BP
Block Protect
2
Write
BAh
60h
Write
BAh
01h
Keep the Block Protect bit
active of the selected
block
BA = Block Address
BU
Block
Unprotect
2
Write
X
60h
Write
X
D0h
Clear all the Block protect
bits simultaneously
dis-activated by Chip Enable E High and then reactivated by Chip Enable E and Output Enable G
Low, during an Erase or Program operation. The
content of Status Register may also be read at the
completion of an Erase/Program and/or Suspend
operation.During a Block Erase, Write to Buffer
and Program, Block Protect or Block Unprotect Instruction, DQ7 indicates the P/E.C. status. It is valid until the operation is completed or suspended,
DQ0-DQ7 output the Status Register content and
DQ8-DQ31 are Low.
19/53
M58LW064A, M58LW064B
Table 13. Status Register Definition
Mnemonic
DQ
P/ECS
DQ7
P/E.C. Status
1 = Ready
0 = Busy (1)
ESS
DQ6
Erase Suspend Status
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed (2)
ES
Function
Status
(7)
1 = Error in Block Erase operation or Block
Unprotect
0 = Successful Block Erase operation or Block
Unprotect (3)
DQ5
Erase/Block Unprotect Status
DQ4
Write to Buffer and Program/Block
Protect Status (7)
DQ3
Not used
PSS
DQ2
Program Suspend Status
1 = Program Suspended
0 = Program operation in Progress/Completed (5)
EPPB
DQ1
Erase/Write to Buffer and Program in a
Protected Block
1 = Error in the defined operation
0 = Operation in Progress/Completed (6)
DQ0
Not used
PS
1 = Error in Write to Buffer and Program, Block
Protect (4)
0 = Write to Buffer and Program, Block Protect
Completed successfully
Note: 1. DQ0-DQ6 are High Impedance when DQ7 is indicating that the part is busy. Status Register P/ECS bit7 indicates the P/E. C. status,
check during Program or Erase, and on completion before checking bit4 or bit5 for Program or Erase Success.
2. DQ6 indicates the Erase Suspend Status. On an Erase Suspend instruction P/ECS and ESS bits are set to ’1’. ESS bit remains ’1’
until an Erase Resume instruction is given.
3. Erase Status, ES bit5 is set to ’1’ if the P/E. C. has applied the maximum number of erase pulses to the block without achieving an
erase verify.
4. Program Status, PS bit4 is set to ’1’ if the P/E.C . has failed to program a Word or Double-Word.
5. DQ2 indicates the Program Suspend Status. On a Program Suspend instruction P/ECS and PSS bits are set to ’1’. PSS bit remains
’1’ until an Program Resume instruction is given.
6. DQ1 defines the status of an Erase or Write to Buffer and Program instruction defined in a protected block. RP pin must be held at
VHH to temporarily override the block protect feature once it has been enabled.
7. DQ5 and DQ4 simultaneously at ’1’ after an Erase or Block Unprotect instruction indicates that an improper command was entered.
20/53
M58LW064A, M58LW064B
Clear Status Register Instruction (CLRS). The
Clear Status Register Instruction is given with the
command 50h at any address location. It is a reset
instruction that resets DQ5, DQ4 and DQ1 in the
Status Register to ’0’.
If an operation such as Block Erase, Write to Buffer and Program Block Protect or Block Unprotect
has failed, the P/E.C. will set DQ5, DQ4 or DQ1 to
’1’ depending on the failure detected (see Table
12, Status Register Definition). The Clear Status
Register Instruction must be given before restarting any corrective Erase/Program Instruction. The
CLRS Instruction should be given also after an
Erase or Program Suspend Instruction failure or
before a Resume Instruction if the previous instruction has been detected to have failed. It is
also a software reset solution that may allow the
execution of several operations such as cumulated Erase or Block Protect operations of multiple
blocks. The Clear Status Register instruction is
valid when the P/E.C. is inactive or the device is in
a suspend mode and it is also valid independent of
the voltage VIH or VHH applied on the RP input.
Write to Buffer and Program Instruction (WBPR). The Write to Buffer and Program Instruction
is used to program the memory array. Up to 16
Words or 8 Double-Words can be loaded into the
Write Buffer and programmed into the device. The
Write to buffer and Program Instruction is composed of three successive steps. The first step is
to give the Write to Buffer and Program command,
E8h with the selected memory Block Address
where the program operation should occur. The
Status Register DQ7 bit then indicates the ”buffer
available” status. If the write buffer is not available
(indicated by DQ7 = 0) then the software can either continue monitoring DQ7 until it transitions to
1, or else re-try later by reloading first the WBPR
command, E8h, and then again monitoring the value of DQ7.
Once the ”write buffer available” condition is valid
(indicated by DQ7 = 1), the second step is to write
the block address again, along with the value N,
where N+1 is the number of Words (x16 organisation) or Double-Words (x32 organisation) to be
programmed.
In the third step, a sequence of N+1 write cycles
loads the addresses and data to the write buffer
(see boundary constraints below). The addresses
must lie between the starting address and the
starting address + (N+1).
The array must be programmed in 4 Word or 2
Double-Word blocks, which must be aligned with
an A2 = A1 = 0 starting address (or A2 = 0 for x32
organisation). Invalid data will be flagged and the
operation will abort with the status register bits
DQ4 and DQ5 set to 1.
The Confirm Command, D0h (the same as Erase/
Program Resume PER Instruction) needs to be
given immediately after the completion of the Write
to Buffer and Program Instruction. It represents
the last (that is the N+2) write operation.
The P/E.C. is enabled only if the whole previous
sequence is fully respected. Otherwise an Invalid
Command/Sequence error will be generated with
the Status Register DQ5 and DQ4 set to ’1’. For
additional Write to Buffer and Program operations,
after the initial input command the software can
check the availability of the write buffer by checking DQ7 status from the Status Register.
If an error appears during a program sequence,
the device will stop its operation and DQ4 of the
Status Register will be set to ’1’ to indicate a program failure. DQ5 will indicate if an error has been
detected during a Block Erase operation. If these
bits, DQ4 or DQ5 are set to ’1’, the Write to Buffer
and Program input command is not accepted by
the device until the status register has been
cleared.
Additionally, if the Block is protected and
VIH < RP < VHH instead of RP = VHH, the Write to
Buffer and Program Instruction will not be accepted by the device, and DQ4 and DQ1 of the status
register will be set to ’1’.
Block Protect Instruction (BP). The Block Protect Instruction BP uses a two-cycle write sequence. The first write cycle gives the command
60h at any address location. The second write cycle gives the block address memory location to be
protected and the command 01h.
Block protection can be cleared with the BU Instruction, which unprotects all blocks. Alternatively, temporary unprotect can be achieved by raising
the RP input to VHH and holding it at that level
throughout the Block Erase or Write to Buffer and
Program operations.
21/53
M58LW064A, M58LW064B
Block Unprotect Instruction (BU). The Block
Unprotect Instruction BU uses a two-cycle write
sequence. All the Block Protect bits are simultaneously erased. The Block Protect bit register is
erased by giving the command 60h and then the
Confirm command D0h, at any address location.
The sequence is aborted if the Confirm command
is not given and the device will output the Status
Register Data with DQ4 and DQ5 set to ’1’.
Block Erase Instruction (EE). The Block Erase
Instruction EE uses a two-cycle command sequence. The Erase Setup command 20h is written
to any address location. Then a second write cycle
is given with the block address to be erased and
the Confirm command D0h. The sequence is
aborted if the Confirm command is not given and
the device will output the Status Register Data with
DQ4 and DQ5 set to ’1’.
During the execution of the erase cycle by the P/
E.C., the memory accepts only the Erase/Program
Suspend instructions. Read operations output the
Status Register bits. A complete state of the erase
operation is given by the Status Register bits.
Erase/Program Suspend Instruction (PES).
The Block Erase or Write to Buffer and Program
operations may be suspended by writing the command B0h at any address. The Erase/Program
Suspend Instruction interrupts the P/E.C. Erase or
Program sequence at a predetermined point in the
algorithm. After the Suspend command is written
the device outputs the Status Register data.
It is possible to read or program data in a block
other than the one in which the Erase Suspend operation is effective. It is only possible to read in a
block other than the one in which a Program Suspend operation is effective. The suspended Erase/
Program operation has to be resumed in order to
complete the previous erase/program sequence.
The Erase Suspend instruction is accepted only
during a Block Erase operation execution. Program Suspend also is valid only during the Write to
Buffer and Program instruction execution. Block
Erase or Erase/Program Suspend instructions are
22/53
ignored if the memory is already in the Suspend
mode.
The Suspend Instruction may be presented at any
time during the execution of a Block Erase. For a
Write to Buffer and Program instruction the Suspend Instruction is accepted only when the P/E.C.
is running.
The device outputs information about the suspend
in the Status Register information on DQ7, DQ6
and DQ2. If the operation has been completed
DQ7 = ’1’ and DQ6 = ’0’ (Erase Suspend) or
DQ2 = ’0’ (Program Suspend).
If the Suspend instruction occurred after the P/
E.C. has completed its operation (DQ7 = 1,
DQ6 = 0 and DQ2 = 0), the Status Register information remains available by toggling Output Enable G. No command is accepted by the device
with the exception of a Read Memory Array Instruction FFh. After the FFh Command is issued,
the device is ready for Read Array (in the mode
defined by the last Set Configuration Register issued).
When a program operation is completed inside a
Block Erase Suspend Instruction, Read Array Instruction FFh will reset the device to Read Array.
The Erase Resume Instruction has to be issued to
complete the whole sequence.
When erase is suspended, the memory will respond only to the Read Array, Read Electronic
Signature, Read Query, Read Status Register,
Clear Status Register, Erase/Program Resume
and the Write to Buffer and Program instructions.
When a Write to Buffer and Program instruction is
suspended, the memory will respond only to the
Read Array, Read Electronic Signature, Read
Query, Read Status Register, Clear Status Register and Erase/Program Resume instructions.
Erase/Program Resume Instruction (PER). If
an Erase Suspend instruction was previously executed, the erase operation may be resumed by
giving the command D0h, at any address. This
also serves as the Confirm command for the Write
to Buffer and Program (WPBR) Instruction which
is issued after the write buffer loading sequence is
completed, and which starts the P/E.C.
M58LW064A, M58LW064B
Set Burst Configuration Register (SBCR).
This instruction uses two command cycles. The
Burst Configuration Setup command 60h is written
with the address corresponding to the Set Burst
Configuration Register content. Then in the second write cycle the address bus A2-A17 specifies
the BCR, Burst Configuration Register, information and the command 03h. The burst length, type,
latency, synchronous/asynchronous read mode
and clock edge active configuration are defined in
that operation. After the command 03h the device
will default in the Read array mode.
Status Register Bits. The P/E.C. status is indicated during execution with a Ready/Busy output
available on DQ7. Any read attempt during Program or Erase command execution will automatically update the Status Register bits. The P/E.C.
automatically sets bits DQ1, DQ2, DQ4, DQ5,
DQ6 and DQ7. The bit DQ0 is reserved for future
use and should be masked. It is not necessary to
specify an address when the Status Register bits
are read. The Status Register is a static memory
register that is reset when RP signal is active or on
a power-down operation.
POWER SUPPLY
Power Down. The memory provides Reset/Power-down control using the input RP. When Reset/
Power-down RP is pulled to VIL the supply current
drops to typically less than 1µA, the memory is deselected and the outputs are at high impedance. If
RP is pulled to VIL during a Program or Erase operation, this operation is aborted after a latency
time of tPLRH and the memory content is no longer
valid.
RESET, POWER-DOWN AND POWER-UP
See Fig 16.
The device is reset if the Reset/Power-down RP
input is pulled to VIL for longer than tPLPH. If the
device was in a Read mode then it will recover
from reset after a time of tPHQV to give valid data
output. If the device was executing an Erase or
Program operation, with the P/E.C. active, the operation will abort in a time of tPLRH maximum. The
device will be ready to accept new write commends after a time of tPHWL or tPHEL.
The supply voltages VDD and VDDQ must be high
a time t VDHEL or tVDHWL before a read or write cycle. At first power up Reset/Power-down should be
held Low for a time of tVDHPH after VDD and VDDQ
are high. The device will be ready to accept its first
read or write commands after a time of tPUR or
tPUW.
COMMON FLASH INTERFACE - CFI
The introduction to the JEDEC CFI specification
Rel. 1.2 quotes, ”The Common Flash Interface
(CFI) specification outlines a device and host system software interrogation handshake which allows specific software algorithms to be used for
entire families of devices. This allows device-independent, JEDEC, ID independent and forwardand backward-compatible software support for the
specified flash device families. It allows flash vendors to standardize their existing interfaces for
long-term compatibility.”
The CFI Query instruction RCFI describes how the
device enters the CFI Query mode which enables
information to be read from the Flash memory. CFI
allows a system software to query the flash device
to determine various electrical and timing parameters, density information and functions supported
by the device. CFI allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to
upgrade itself when necessary.
Query Structure Overview
The flash memory displays the CFI data structure
when the CFI Query Instruction RCFI is issued. A
list of the main subsections is detailed in Tables 15
to 19.
23/53
M58LW064A, M58LW064B
Table 14. Query Structure Overview
Offset
Sub-section Name
Description
00h
Manufacturer Code
01h
Device Code
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing and voltage information
27h
Device Geometry Definition
Flash device layout
P(h)
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A(h)
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Block Status Register
Block-related Information
(BA+3)h
Table 15. CFI - Query Address and Data Output in the x16/x32 organization
Address (4)
A22-A1 (M58LW064A)
A22-A2 (M58LW064B)
Data
Instruction
10h
51h
”Q”
11h
52h
”R”
12h
59h
”Y”
13h
20h
14h
00h
15h
31h
16h
00h
17h
00h
18h
00h
19h
31h
1Ah
00h
Query ASCII String
51h; ”Q”
52h; ”R”
59h; ”Y”
Primary Vendor:
Command Set and Control Interface ID Code
Primary algorithm extended Query Address Table: P(h)
Alternate Vendor:
Command Set and Control Interface ID Code
Alternate Algorithm Extended Query address Table
Note: 1.
2.
3.
4.
24/53
The x8 or Byte Address mode is not available.
In the x16 organization, the value of the address location of the CFI Query is independent of A1 pad (M58LW064B).
Query Data are always presented on the lowest order data outputs (DQ7-DQ0) only. Others data (DQ31-DQ8) are set to ’0’.
For M58LW064B, A1 = Don’t Care.
M58LW064A, M58LW064B
Table 16. CFI - Device Voltage and Timing Specification
Address (4)
A22-A1 (M58LW064A)
A22-A2 (M58LW064B)
Data
1Bh
27h (1)
VCC Min, 2.7V
1Ch
36h (1)
VCC max, 3.6V
1Dh
00h (2)
VPP min – Not Available
1Eh
00h (2)
VPP max – Not Available
1Fh
00h (3)
2N ms Word, DWord prog. typical time-out
20h
x07h
2N ms, typical time out for max buffer write
21h
0Ah
2N ms, Erase Block typical time-out
22h
00h (3)
2N ms, chip erase time-out typ. – Not Available
23h
00h (3)
2N times typ. for Word Dword time-out max – Not Available
24h
04h
2N times typ. for buffer write time-out max
25h
04h
2N x typ. individual block erase time-out maximum
26h
00h (3)
Note: 1.
2.
3.
4.
Instruction
2N times typ. for chip erase max time-out – Not Available
Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volt and bit3 to bit0 in mV.
Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
Not supported.
For M58LW064B, A1 = Don’t Care.
Table 17. Device Geometry Definition
Address (1)
A22-A1 (M58LW064A)
A22-A2 (M58LW064B)
Data
27h
17h
2N nb. of bytes device Size
28h
01h.
Device Interface Sync./Async.
29h
00h
Organisation Sync./Async.
2Ah
05h
2Bh
00h
2Ch
01h
2Dh
3Fh
2Eh
00h
2Fh
00h
30h
02h
Instruction
Page size in bytes, 2N
Bit7-0 = nb of Erase Block region
Number (N-1) of Erase Blocks of identical size; N=64
x times 256 bytes per Erase block (128K bytes)
Note: 1. For M58LW064B, A1 = Don’t Care.
25/53
M58LW064A, M58LW064B
Table 18. Block Status Register (see also, Table 6 and 7 in the datasheet)
Address
A22-A2
Data (Hex) x32 organization
Selected Block Information
0
Block Unlocked
1
Block Locked
0
Last erase operation ended successfully (2)
1
Last erase operation not ended successfully (2)
0
Reserved for future features
bit0
(BA+3)h (1)
bit1
bit7-2
Note: 1. BA specifies the block address location, i-e, A22-A17.
2. Not Supported.
Table 19. Extended Query information
M58LW064B - x32
M58LW064A - x16
M58LW064B x16 organization
Instruction
Address
offset
Address
A22-A2
Data (Hex)
x32 organization
Address
A22-A1
Data
(P)h
31h
50h
”P”
62h, 63h
50h
(P+1)h
32h
52h
”R”
64h, 65h
52h
(P+2)h
33h
49h
”Y”
66h, 67h
49h
(P+3)h
34h
31h
68h, 69h
31h
Major version number
(P+4)h
35h
31h
6Ah, 6Bh
31h
Minor version number
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Lock/Unlock Supported (1=yes)
bit4, Queue Erase Supported (0=no)
Bit 31-5 reserved for future use
Query ASCII string - Extended Table
(P+5)h
36h
0Eh
6Ch, 6Dh
0Eh
(P+6)h
37h
00h
6Eh, 6Fh
00h
(P+7)h
38h
00h
70h, 71h
00h
(P+8)h
39h
00h
72h, 73h
00h
(P+9)h
3Ah
01h
74h, 75h
00h
(P+A)h
3Bh
00h (2)
76h, 77h
(P+C)h
3Ch
33h
78h, 79h
33h
VCC OPTIMUM Program/Erase voltage conditions
(P+D)h
3Dh
50h
7Ah, 7Bh
50h
VPP OPTIMUM Program/Erase voltage conditions
(P+E)h
3Eh
00h
7Ch, 7Dh
00h
Reserved for future use
(P+F)h
3Fh
00h
7Dh, 7Fh
00h
Reserved for future use
Optional Features
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
00h (2) Block Status Register Mask
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. Not supported.
26/53
M58LW064A, M58LW064B
Table 20. AC Measurement Conditions
Figure 8. AC Testing Load Circuit
Clock Rise and Fall Times
≤3ns
Input Rise and Fall Times
≤4ns
Input Pulses Voltages
1.3V
0V to VDDQ
Input and Output Timing Ref. Voltages
1N914
VDDQ /2
3.3kΩ
Figure 7. AC Testing Input Output Waveform
DEVICE
UNDER
TEST
VDDQ
OUT
CL = 30pF
VDDQ/2
0V
C L includes JIG capacitance
AI00610
AI03229
Note: VDD = VDDQ.
Table 21. Capacitance (TA = 25°C, f = 1 MHz)
Symbol
C IN
C OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Typ
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
27/53
M58LW064A, M58LW064B
Table 22. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V≤ VIN ≤ V DDQ
±1
µA
ILO
Output Leakage Current
0V≤ VOUT ≤VDDQ
±5
µA
ICC
Supply Current (Random Read)
E = VIL, G = VIH, fadd = 6MHz
30
mA
ICCB
Supply Current (Burst Read)
E = VIL, G = VIH, fclock = 50MHz
50
mA
40
mA
Supply Current (Auto Low-Power)
E = VDD ± 0.2V,
RP = VDD ± 0.2V
2
mA
ICC2
Supply Current (Reset/Power-down)
RP = VSS ± 0.2V
1
µA
ICC3 (1)
Supply Current (Program or Erase,
Set Lock Bit, Erase Lock Bit)
Write to Buffer and program
Block Erase in progress
30
mA
E = VIH
40
µA
ICC1
Supply Current (Standby)
ICC4
Supply Current
(Erase/Program Suspend)
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.3
V
VOL
Output Low Voltage
0.1
V
VOH
Output High Voltage CMOS
VHH (2)
V LKO
RP Hardware Block Unlock Voltage
IOL = 100µA
IOH = –100µA
VDDQ –0.1
Block Erase in progress,
Write to Buffer and Program
8.5
VDD Supply Voltage (Erase and
Program lockout)
Note: 1. Sampled only, not 100% tested.
2. Biasing RP pin to VHH is allowed for a maximum cumulative period of 80 hours.
3. Current increases to ICC + ICC5 during a read operation.
28/53
V
9.5
V
2.2
V
M58LW064A, M58LW064B
Table 23. Asynchronous Random Read
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDDQ = 1.8V to VDD)
Symbol
Parameter
Test Condition
Min
150
Max
Unit
tAVAV
Address Valid to Address Valid
E = VIL, G = VIL
tAVQV
Addrss Valid to Output Valid
E = VIL, G = VIL
tAXQX
Address Transition to Output Transition
E = VIL, G = VIL
tEHLX
Chip Enable High to Latch Enable Transition
tEHQX
Chip Enable High to Output Transition
G = VIL
tEHQZ
Chip Enable High to Output Hi-Z
G = VIL
10
ns
tELQV(1)
Chip Enable Low to Output Valid
G = VIL
150
ns
tELQX
Chip Enable Low to Output Transition
G = VIL
0
ns
tGHQX
Output Enable High to Output Transition
E = VIL
0
ns
tGHQZ
Output Enable High to Output Hi-Z
E = VIL
10
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
50
ns
tGLQX
Output Enable to Output Transition
E = VIL
tLLEL
Latch Enable Low to Chip Enable Low
ns
150
ns
0
ns
0
ns
0
ns
0
ns
10
ns
Note: 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV.
Figure 9. Asynchronous Random Read AC Waveforms
Asynchronous Read (M15 = 1), Random (M3 = 0)
tAVQV
A1-A22
(1)
VALID
tELQV
tELQX
tAXQX
E
tGLQX
tGLQV
tEHQZ
tEHQX
G
tGHQX
tGHQZ
DQ0-DQx
(2)
OUTPUT
tLLEL
tEHLX
L
See also Page Read
(1) A1 is not used (Don’t Care) in x32 organization
(2) DQ0-DQ15 in x16 or DQ0-DQ31 in x32 organization
AI03250
29/53
M58LW064A, M58LW064B
Table 24. Asynchronous Latch Enable Controlled Read and Page Read
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDD = 1.8V to VDD)
Symbol
tAVLL
Parameter
Address Valid to Lacth Enable Low
Test Condition
Min
E = VIL
10
Max
Unit
ns
tAVQV1
Address Valid to Output Valid (Page Read)
E = VIL, G = VIL
tAXQX
Address Transition to Output Transition (Page Read)
E = VIL, G = VIL
tEHLX
Chip Enable High to Latch Enable Transition
t EHQX
Chip Enable High to Output Transition
G = VIL
tEHQZ
Chip Enable High to Output Hi-Z
G = VIL
tELLL
Chip ENable Low to Latch Enable Low
tGHQX
Output Enable High to Output Transition
E = VIL
tGHQZ
Output Enable High to Output Hi-Z
E = VIL
10
ns
tGLQV
Output Enable Low to Output Valid
E = VIL
50
ns
tGLQX
Output Enable Low to Output Transition
E = VIL
0
ns
tLHAX
Latch Enable High to Address Transition
E = VIL
10
ns
tLHLL
Lacth Enable High to Latch Enable Low
10
ns
tLLLH
Latch Enable Low to LatchEnable High
10
ns
tLLQV
Latch Enable Low to Output Valid
E = VIL, G = VIL
125
ns
tLLQV1
Lacth Enable Low to Output Valid (Page Read)
E = VIL, G = VIL
25
ns
tLLQX
Latch Enable Low to Output Transition
E = VIL, G = VIL
25
6
ns
0
ns
0
ns
10
E = VIL
ns
ns
10
ns
0
ns
0
ns
Figure 10. Asynchronous Read Latch Enable Controlled Read AC Waveforms (x16, x32 organisation)
Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)
A1-A22
(1)
VALID
tAVLL
L
tLHAX
tLHLL
tLLLH
tEHLX
tELLL
E
tGLQX
tGLQV
tEHQX
tEHQZ
G
tLLQV
tLLQX
DQ0-DQX
(2)
(1) A1 is not used (Don’t Care) in x32 organization
(2) DQ0-DQ15 in x16 or DQ0-DQ31 in x32 organization
30/53
tGHQX
GHQZ
OUTPUT
See also Page Read
AI03251
M58LW064A, M58LW064B
Figure 11. Asynchronous Page Read for Random or Latch Enable Controlled Read
Asynchrouns Read (M15 = 1), Random (M3 = 0) or Latch Enable Controlled (M3 = 1)
A1-A2
L
(1)
A1 and/or A2 (x16), A2 (x32)
(2)
tLLQV1
tAVQV1
tAXQX
OUTPUT
DQ0-DQX
See Asynchronous
Random Read
or
Asynchronous Latch
Enable Controlled Read
OUTPUT + 1
Page Read up to
- 4 Words in x16 organization
- 2 Double-Words in x32 orognization
(1) A1 and/or A2 only may change in x16 organization, A2 only in x32 organization
(2) Only for Latch Enable Controlled Read
AI03699
31/53
M58LW064A, M58LW064B
Table 25. Synchronous Burst Read
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDD = 1.8V to VDD)
Symbol(2)
Parameter
Test Condit ion
Min
Max
Unit
E = VIL
10
ns
tAVLL
Address Valid to Latch Enable Low
tBHKH
Burst Address Advance High toValid Clock Edge
E = VIL , G = VIL, L = VIH
10
ns
tBLKH
Burst Address Advance Low to Valid Clock Edge
E = VIL , G = VIL, L = VIH
10
ns
tELLL
Chip Enable Low to Latch Enable low
0
ns
t GLKH
Output Enable Low to Valid Clock Edge
E = VIL, L = VIH
20
ns
t KHAX
Valid Clock Edge to Address Transition
E = VIL
0
ns
tKHLL
Valid Clock Edge to Latch Enable Low
E = VIL
0
ns
tKHLX
Valid Clock Edge to Latch Enable Transition
E = VIL
0
ns
tKHQX
Valid Clock Edge to Output Transition
E = VIL , G = VIL, L = VIH
tLLKH
Latch Enable Low to Valid Clock Edge
E = VIL
10
ns
Output Valid to Valid Clock Edge
E = VIL , G = VIL, L = VIH
10
ns
Valid Data Ready Low to Valid Clock Edge
E = VIL , G = VIL, L = VIH
10
ns
tQVKH(1)
tRLKH
6
ns
Note: 1. Data output should be read on the valid clock edge.
2. For paramters not listed see Asynchronous Read.
Figure 12. Synchronous Burst Read (9.1.1.1 example)
X-Latency = 0 (M14-M11 = 0100), Y-Latency = 1 (M9 = 0), Burst Length = 4 (M2-M0 = 001),
Burst Type = Sequential (M7 = 1), Valid Clock Edge = Rising (M6 = 1)
9
10
11
12
13
14
K
tQVKH
DQ0-DQx
Q0
Q1
Q2
Q3
Q0
Q1
tKHQX
SETUP
(1)
Burst Read
Q0 to Q3
Burst Read Wraps if Device
remains Selected (E = VIL)
(1) For set up signals and timings see Synchronous Burst Read 8.1.1.1
AI03698
32/53
M58LW064A, M58LW064B
tQVKH
DQ0-DQx (1)
G
E
(1) A1 is not used (Don’t Care) in x32 organization
(2) DQ0-DQ15 in x16 or DQ0-DQ31 in x32 organization
tELLL
tLLKH
L
A1-A22 (1)
K
tKHLL
0
VALID
1
tAVLL
tKHLX
2
tKHAX
3
Setup
4
5
6
7
tGLKH
8
OUTPUT
9
10
tEHQX
tEHQZ
tGHQX
tGHQZ
AI03256
Figure 13. Synchronous Burst Read (8.1.1.1 example)
X-Latency = 8 (M14-M11 = 0010), Y-Latency = 1 (M9 = 0), Burst Length = 1 (M2-M0 = 100),
Burst Type = Any (M7 = 0 or 1), Valid Clock Edge = Rising (M6 = 1)
33/53
M58LW064A, M58LW064B
Figure 14. Synchronous Burst Read - Continuous - Valid Data Ready Output
Valid Data Ready = Valid Low during valid clock edge (M8 = 0)
K
Output (1)
V
V
V
NV
NV
V
V
tBLKH
R
(2)
(1) V = Valid output; NV = Not Valid output.
(2) R is an open drain output with an internal pull up resistor of 1MΩ.
The internal timing of R follows DQ. An external resistor, typically 300kΩ for a single memory on the R Bus, should
be used to give a data valid set up time required to recognize valid data is evailable on the next valid clock edge.
AI03696
Figure 15. Synchronous Burst Pipeline Read (8.1.1.1 example)
X-Latency = 8 (M14-M11 = 0010), Y-Latency = 1 (M9 = 0), Burst Length = 1 (M2-M0 = 100),
Burst Type = Any (M7 = 0 or 1), Valid Clock Edge = Rising (M6 = 1)
Valid
Clock
Edges
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
8
8
Addresses
Outputs
1st
Address
Latch
2nd
Address
Latch
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Not Valid
AI03695
34/53
M58LW064A, M58LW064B
Figure 16. Synchronous Burst Read - Burst Address Advance
9
10
11
12
13
14
K
OUTPUTS
Q0
Q1
B
tBLKH
(1)
(2)
tBHKH
(3)
(1) Valid clock edge ’9’ is valid and outputs Q0.
(2) B goes low before valid clock edge ’10’ and output increments to Q1.
(3) B goes high before valid clock edge ’12’ and output remains Q1.
AI03697
35/53
M58LW064A, M58LW064B
Table 26. Asynchronous Write and Latch Enable Controlled Write
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDD = 1.8V to VDD)
Symbol
Parameter
tAVLH
Address Valid to Latch Enable High
tAVWH
Address Valid to Write Enable High
tDVWH
Data Input Valid to Write Enable High
tELWL
Test Conditio n
Min
Max
Unit
10
ns
E = VIL
50
ns
E = VIL
50
ns
Chip Enable Low to Write Enable Low
0
ns
tLHAX
Latch Enable High to Address Transition
3
ns
tLLLH
Latch Enable low to Latch Enable High
10
ns
tLLWH
latch Enable Low to Write Enable High
50
ns
tQVRH
Output Valid to Reset/Power Down VDD
0
ns
tQVVPL
Output Valid to Program/Erase Enable Low
0
ns
tRHHWH
Reset/Power Down VHH to Write Enable High
0
ns
tVPHWH
Program/Erase Enable High to Write Enable High
0
ns
10
ns
tWHAX
Write Enable High to Address Transition
tWHBL
Write Enable High to Read/Busy low
tWHDX
Write Enable High to Input Transition
tWHEH
Write Enable High to Chip Enable High
tWHGL
E = VIL
90
E = VIL
ns
10
ns
0
ns
Write Enable High to Output Enable Low
35
ns
tWHWL
Write Enable High to Write Enable Low
30
ns
tWLWH
Write Enable Low to Write Enable High
70
ns
36/53
E = VIL
RP
VPP
RB
DQ0-DQ31
W
G
E
A1-A22
tWHEH
INPUT
tDVWH
tWHDX
tWHWL
tWHAX
tWLWH
Write Cycle
tELWL
tAVWH
VALID
INPUT
RP = VHH
Write Cycle
tRHHW
tVPHWH
VALID
tWHBL
tWHQV
tWHGL
VALID
Read Status Register
RP = VDD
tQVRH
tQVVPL
VALID SR
AI03694
M58LW064A, M58LW064B
Figure 17. Asynchronous Write
37/53
38/53
DQ0-DQx
W
G
E
L
A1-A22
tLLLH
tWHDX
Write Cycle
tWLWH
tELWL
tLHAX
INPUT
tLLWH
tAVWH
tAVLH
VALID
tDVWH
tWHWL
tWHEH
tWHAX
VALID
Write Cycle
INPUT
tWHQV
tWHGL
VALID
VALID SR
AI03693
M58LW064A, M58LW064B
Figure 18. Asynchronous Latch Enabled Controlled Write
M58LW064A, M58LW064B
Table 27. Reset, Power-down and Power-up
(TA = 0 to 70°C, –40 to 85°C, VDD = 2.7V to 3.6V, VDD = 1.8V to VDD)
Symbol
Parameter
Min
Max
Unit
µs
tPHEL
Reset/Power-down High to Chip Enable Low
tPHQV
Reset/Power-down High to Output Valid
tPHWL
Reset/Power-down High to Write Enable Low
tPLPH
Reset/Power-down Low to Reset/Power-down High
tPLRH
Reset/Power-down Low to Ready High
tPUR
Power-up to Read
10
µs
tPUW
Power-up to Write
10
µs
50
10
µs
50
µs
500
ns
22
µs
tVDHEL
Supply Voltages High to Chip Enable low
50
ms
tVDHPH
Supply Voltages High to Reset/Power-down High
1
µs
tVDHWL
Supply Voltages High to Write Enable Low
50
ms
Table 28. Program, Erase Times and Program Erase Endurance Cycles
(TA = 0 to 70°C; VDD = 2.7V to 3.6V; VDDQ =1.7V to 1.9V)
M58LW064A/B
Typ
Typical after
100k W/E Cycles
Unit
Max
1.5
0.75
0.75
sec
Chip Program
54
54
sec
Write Buffer
192
192
µs
Parameters
Min
Uniform Block (1Mb) Erase
Program Suspend Latency Time
10
3
µs
Erase Suspend Latency Time
30
10
µs
Program/Erase Cycles (per Block)
100,000
cycles
39/53
M58LW064A, M58LW064B
Figure 19. Reset, Power-down and Power-up AC Waveform
Reset during Read Mode
tPLPH
tPHQV
RP
Reset
Recovery to Read
Reset during Program/Erase
tPHWL
tPHEL
tPLRH
tPLPH
RP
Reset
Recovery
Abort
tPHWL
tPHEL
tPLRH
tPLPH
RP
Power
Down
Abort
Recovery
Reset during Power up
tPHR, tPKW
tVDHPH
RP
VDD, VDDQ
tVDHEL
tVDHWL
E
Power-up
AI03692
40/53
M58LW064A, M58LW064B
Figure 20. Write Buffer Program Flowchart and Pseudo Code
Start
Write to Buffer E8h
Command, Block Address
Read Status
Register
NO
b7 = 1
NO
Write to Buffer
Timeout
YES
YES
Write Word or Byte
Count, Block Address
Try Again Later
Write Buffer Data,
Start Address
X= 0
YES
X=N
NO
Write Next Buffer Data,
Device Address
X=X+ 1
Program Buffer to Flash
Confirm D0h
Read Status
Register
b7 = 1
NO
YES
Full Status Check
(Optional)
End
AI03635
41/53
M58LW064A, M58LW064B
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
Write 70h
Command
PES instruction:
– write B0h command
(memory enters read register
state after the PES instruction)
do:
– read status register
(E or G must be toggled)
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b4 = 1
NO
Program Complete
If b4 = 0, Program completed
(at this point the memory will
accept only the RD or PER instruction)
YES
Write FFh
Command
RD instruction:
– write FFh command
– one or more data reads
from another block
Read data from
another block
Write D0h
Command
Write FFh
Command
Program Continues
Read Data
PER instruction:
– write D0h command
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase suspend
was not issued).
AI00612
42/53
M58LW064A, M58LW064B
Figure 22. Erase Flowchart and Pseudo Code
Start
Write 20h
Command
EE instruction:
– write 20h command
– write Block Address
(A12-A17) & command D0h
(memory enters read status
state after the EE instruction)
Write Block Address
& D0h Command
NO
Read Status
Register
Suspend
b7 = 1
YES
NO
Suspend
Loop
do:
– read status register
(E or G must be toggled)
if EE instruction given execute
suspend erase loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1)
NO
Command
Sequence Error
NO
Erase
Error (1)
NO
Erase to Protected
Block Error
If b3 = 1, VPP invalid error:
– error handler
YES
b4, b5 = 0
If b4, b5 = 1, Command Sequence error:
– error handler
YES
b5 = 0
If b5 = 1, Erase error:
– error handler
YES
b1 = 0
If b1 = 1, Erase to Protected Block Error:
– error handler
YES
End
AI00613B
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
43/53
M58LW064A, M58LW064B
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
Write 70h
Command
PES instruction:
– write B0h command
(memory enters read register
state after the PES instruction)
do:
– read status register
(E or G must be toggled)
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b6 = 1
NO
Erase Complete
If b6 = 0, Erase completed
(at this point the memory wich
accept only the RD or PER instruction)
YES
Write FFh
Command
RD instruction:
– write FFh command
– one o more data reads
from another block
Read data from
another block
or Program
PG instruction:
– write 40h command
– write Address & Data
Write D0h
Command
Write FFh
Command
Program Continues
Read Data
PER instruction:
– write D0h command
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase suspend
was not issued).
AI00615
44/53
M58LW064A, M58LW064B
Figure 24. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE (1)
90h
NO
YES
READ
SIGNATURE
98h
NO
YES
CFI
QUERY
70h
NO
YES
READ
STATUS
50h
READ
ARRAY
NO
YES
CLEAR
STATUS
E8h
NO
YES
PROGRAM
BUFFER
LOAD
20h
NO
YES
READ
STATUS
C
ERASE
SET-UP
NO
FFh
YES
D0h
NO
YES
B
A
ERASE
COMMAND
ERROR
AI03618
Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or
if VDD falls below V LKO, the Command Interface defaults to Read Array mode.
2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
45/53
M58LW064A, M58LW064B
Figure 25. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
YES
(READ STATUS)
READY
(2)
NO
B0h
NO
YES
READ
STATUS
ERASE
SUSPEND
YES
READY
(2)
NO
ERASE
NO
SUSPENDED
READ
STATUS
YES
READ
STATUS
YES
70h
NO
READ
SIGNATURE
YES
90h
NO
CFI
QUERY
YES
98h
NO
PROGRAM
BUFFER
LOAD
YES
c
READ
ARRAY
E8h
NO
NO
D0h
YES
AI03618
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
46/53
READ
STATUS
(ERASE RESUME)
M58LW064A, M58LW064B
Figure 26. Command Interface and Program Erase Controller Flowchart (c)
C
B
PROGRAM
YES
(READ STATUS)
READY
(2)
NO
B0h
NO
YES
READ
STATUS
PROGRAM
SUSPEND
YES
READY
(2)
NO
NO
PROGRAM
SUSPENDED
READ
STATUS
YES
READ
STATUS
YES
70h
NO
READ
SIGNATURE
YES
90h
NO
CFI
QUERY
YES
98h
NO
READ
ARRAY
NO
D0h
YES
READ
STATUS
(PROGRAM RESUME)
AI00618
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
47/53
M58LW064A, M58LW064B
Table 29. Ordering Information Scheme
Example:
M58LW064A
150 N
1
T
Device Type
M58
Architecture
L = Multi-Bit Cell, Burst Mode, Page Mode
Operating Voltage
W = VDD = 2.7V to 3.6V; V DDQ = 1.8 to VDD
Device Function
064A = 64 Mbit (x16), Equal Block, Boot Block
064B = 64 Mbit (x16/x32), Equal Block, Boot Block
Speed
150 = 150 ns
Package
NF = TSOP56: 14 x 20 mm
NH = TSOP86 Type II
T = PQFP80
ZA = LBGA64
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Optio n
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Configuration, Package, etc...) or for further information on any aspect of
this device, please contact the STMicroelectronics Sales Office nearest to you.
48/53
M58LW064A, M58LW064B
Table 30. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
A
Typ
Min
1.20
Max
0.0472
A1
0.05
0.15
0.0020
0.0059
A2
0.95
1.05
0.0374
0.0413
B
0.17
0.27
0.0067
0.0106
C
0.10
0.21
0.0039
0.0083
D
19.80
20.20
0.7795
0.7953
D1
18.30
18.50
0.7205
0.7283
E
13.90
14.10
0.5472
0.5551
–
–
–
–
L
0.50
0.70
0.0197
0.0276
α
0°
5°
0°
5°
N
40
e
0.50
0.0197
40
CP
0.10
0.0039
Figure 27. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
49/53
M58LW064A, M58LW064B
Table 31. TSOP86 Type II, Package Mechanical Data
mm
inch
Symbol
Typ
Min
Max
A
Typ
Min
Max
1.200
A1
0.050
A2
0.950
1.150
0.0472
0.0020
0.0374
0.0453
b
0.220
0.170
0.300
0.0087
0.0067
0.0118
C
0.145
–
–
0.0057
–
–
D
22.220
22.120
22.320
0.8748
0.8709
0.8787
E
11.760
11.560
11.960
0.4630
0.4551
0.4709
E1
10.160
10.060
10.260
0.4000
0.3961
0.4039
e
0.500
–
–
0.0197
L
0.450
0.750
0.0177
0.0295
α
0°
8°
0°
8°
N
86
86
CP
0.100
0.0039
Figure 28. TSOP86 Type II, Package Outline
D
N
E1
1
E
N/2
b
e
A2
A
C
A1
CP
α
L
TSOP-e
Drawing is not to scale.
50/53
M58LW064A, M58LW064B
Table 32. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
Max
3.40
A1
0.1339
0.25
A2
2.80
0.0098
2.55
3.05
b
0.30
c
0.1102
0.1004
0.1201
0.45
0.0118
0.0177
0.11
0.23
0.0043
0.0091
D
23.90
–
–
0.9409
–
–
D1
20.00
–
–
0.7874
–
–
e
0.80
–
–
0.0315
–
–
E
17.90
–
–
0.7047
–
–
E1
14.00
–
–
0.5512
–
–
L
0.88
0.73
1.03
0.0346
0.0287
0.0406
α
3.5 °
0°
7°
3.5 °
0°
7°
N
80
80
Nd
24
24
Ne
16
16
CP
0.250
0.0098
Figure 29. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
D
D1
D2
A2
e
Ne
E2 E1 E
b
N
1
Nd
A
CP
c
TQFP
A1
α
L
Drawing is not to scale.
51/53
M58LW064A, M58LW064B
Table 33. LBGA54 - 6 x 8 balls, 1 mm pitch, Package Mechanical Data
mm
inch
Symbol
Typ
Min
Max
Typ
Min
Max
A
1.090
0.980
1.200
0.0429
0.0386
0.0472
A1
0.290
0.220
0.360
0.0114
0.0087
0.0142
A2
0.800
0.760
0.840
0.0315
0.0299
0.0331
b
0.430
0.300
0.560
0.0169
0.0118
0.0220
D
10.000
9.800
10.200
0.3937
0.3858
0.4016
D1
7.000
–
–
0.2756
–
–
ddd
0.150
0.0059
e
1.000
0.925
1.075
0.0394
0.0364
0.0423
E
13.000
12.800
13.200
0.5118
0.5039
0.5197
E1
7.000
–
–
0.2756
–
–
FD
3.000
–
–
0.1181
–
–
FE
1.500
–
–
0.0591
–
–
SD
0.500
–
–
0.0197
–
–
SE
0.500
–
–
0.0197
–
–
Figure 30. LBGA54 - 6 x 8 balls, 1 mm pitch, Package Outline
E
E1
FE
FD
D
SE
SD
D1
ddd
BALL ”A1”
A
e
b
A2
A1
BGA-Z11
Drawing is not to scale.
52/53
M58LW064A, M58LW064B
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.
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