AVAGO HCPL-6430 Hermetically sealed, very high speed, logic gate optocouplers high radiation immunity Datasheet

HCPL-540X*, 5962-89570, HCPL-543X,
HCPL-643X, 5962-89571
Hermetically Sealed, Very High Speed,
Logic Gate Optocouplers
Data Sheet
*See matrix for available extensions.
Description
Features
These units are single and dual channel, hermetically
sealed optocouplers. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from the appropriate DLA Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line
and are included in the DLA Qualified Manufacturers List,
QML-38534 for Hybrid Microcircuits.
 Dual marked with device part number and DLA
standard microcircuit drawing
 Manufactured and tested on a MIL-PRF-38534 certified
line
 QML-38534, Class H and K
 Three hermetically sealed package configurations
 Performance guaranteed over full military temperature
range: -55° C to +125° C
 High Speed: 40 M bit/s
 High common mode rejection 500 V/s guaranteed
 1500 Vdc withstand test voltage
 Active (totem pole) outputs
 Three stage output available
 High radiation immunity
 HCPL-2400/30 function compatibility
 Reliability data
 Compatible with TTL, STTL, LSTTL, and HCMOS logic
families
Functional Diagram
Multiple channel devices available
VCC
VE
VO
GND
Truth Tables (Positive Logic)
Applications
Multichannel Devices
Input
Output
On (H)
L
Off (L)
H
Single Channel DIP
Input
Enable
Output
On (H)
L
L
Off (L)
L
H
On (H)
H
Z
Off (L)
H
Z
The connection of a 0.1 F bypass capacitor between VCC and GND is
recommended.












Military and space
High reliability systems
Transportation, medical, and life critical systems
Isolation of high speed logic systems
Computer-peripheral interfaces
Switching power supplies
Isolated bus driver (networking applications) –
(5400/1/K only)
Pulse transformer replacement
Ground loop elimination
Harsh industrial environments
High speed disk drive I/O
Digital isolation for A/D, D/A conversion
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains an AlGaAs light emitting diode
which is optically coupled to an integrated high gain
photon detector. This combination results in very high
data rate capability. The detector has a threshold with
hysteresis, which typically provides 0.25 mA of differential mode noise immunity and minimizes the potential for
output signal chatter. The detector in the single channel
units has a three state output stage which eliminates the
need for a pull-up resistor and allows for direct drive of a
data bus.
All units are compatible with TTL, STTL, LSTTL, and HCMOS
logic families. The 35 ns pulse width distortion specification guarantees a 10 MBd signaling rate at +125° C
with 35% pulse width distortion. Figures 13 through 16
show recommended circuits for reducing pulse width
distortion and optimizing the signal rate of the product.
Package styles for these parts are 8 pin DIP through hole
(case outlines P), and leadless ceramic chip carrier (case
outline 2). Devices may be purchased with a variety of
lead bend and plating options. See Selection Guide Table
for details. Standard Microcircuit Drawing (SMD) parts are
available for each package and lead style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and performance characteristics shown in the figures are similar
for all parts. Occasional exceptions exist due to package
variations and limitations and are as noted. Additionally,
the same package assembly processes and materials are
used in all devices. These similarities give justification for
the use of data obtained from one part to represent other
part’s per formance for die related reliability and certain
limited radiation test results.
Selection Guide–Package Styles and Lead Configuration Options
Package
8 Pin DIP
8 Pin DIP
20 Pad LCCC
Lead Style
Through Hole
Through Hole
Surface Mount
Channels
1
2
2
Common Channel Wiring
None
VCC , GND
None
Commercial
HCPL-5400
HCPL-5430
HCPL-6430
MIL-PRF-38534, Class H
HCPL-5401
HCPL-5431
HCPL-6431
Avago Part # & Options
MIL-PRF-38534, Class K
HCPL-540K
HCPL-543K
HCPL-643K
Standard Lead Finish
Gold Plate
Gold Plate
Solder Pads*
Solder Dipped*
Option 200
Option 200
Butt Cut/Gold Plate
Option 100
Option 100
Gull Wing/Soldered*
Option 300
Option 300
5962-
5962-
Gold Plate
8957001PC
8957101PC
Solder Dipped*
8957001PA
8957101PA
Butt Cut/Gold Plate
8957001YC
8957101YC
Butt Cut/Soldered*
8957001YA
8957101YA
Gull Wing/Soldered*
8957001XA
8957101XA
5962-
5962-
Gold Plate
8957002KPC
8957103KPC
Solder Dipped*
8957002KPA
8957103KPA
Butt Cut/Gold Plate
8957002KYC
8957103KYC
Butt Cut/Soldered*
8957002KYA
8957103KYA
Gull Wing/Soldered*
8957002KXA
8957103KXA
Class H SMD Part #
Prescript for all below
596289571022A
Class K SMD Part #
Prescript for all below
*Solder contains lead.
2
59628957104K2A
Functional Diagrams
8 Pin DIP
8 Pin DIP
20 Pad LCCC
Through Hole
Through Hole
Surface Mount
1 Channel
2 Channels
2 Channels
1
VCC
8
1
2
VE
7
2
3
VO
4
GND
6
3
5
4
VCC
VO1
8
7
VO2
GND
6
5
19
20
15
VCC2
VO2
GND2
2
3
VO1
13
12
VCC1 10
GND1
7 8
Note:
All DIP devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground
connections.
Outline Drawings
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
Note: Dimensions in millimeters (inches).
Solder thickness 0.127 (0.005) max.
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
3.81 (0.150)
MIN.
0.51 (0.020)
MAX.
Note: Dimensions in millimeters (inches).
3
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Leaded Device Marking
Avago LOGO
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
ESD IDENT
Avago QYYWWZ
XXXXXX
XXXXXXX
XXX USA
* 50434
Leadless Device Marking
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
Avago LOGO
Avago P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
COUNTRY OF MFR.
Avago FSCN*
Avago QYYWWZ
XXXXXX
* XXXX
XXXXXX
USA 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DLA SMD*
DLA SMD*
Avago FSCN*
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
Note: Dimensions in millimeters (inches).
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in
8 pin DIP. DLA Drawing part numbers contain provisions for leadfinish. All leadless chip carrier devices are
delivered with solder dipped terminals as a standard feature.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is
available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has
solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
5° MAX.
Note: Dimensions in millimeters (inches).
*Solder contains lead.
4
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
1.07 (0.042)
1.32 (0.052)
Absolute Maximum Ratings
No derating required up to +125° C.
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-65
+150
°C
Operating Temperature
TA
-55
+125
°C
Case Temperature
TC
+170
°C
Junction Temperature
TJ
+175
°C
260 for 10 sec
°C
Lead Solder Temperature
Average Forward Current (each channel)
IF(AVG)
10
mA
Peak Input Current (each channel)
IF(PEAK)
20
mA
Reverse Input Voltage (each channel)
VR
3
V
Supply Voltage
VCC
0.0
7.0
V
Average Output Current (each channel)
IO(AVG)
-25
25
mA
Output Voltage (each channel)
VO
-0.5
10
V
Output Power Dissipation (each channel)
PO
130
mW
Package Power Dissipation (each channel)
PD
200
mW
10
V
Single Channel Product Only
Three State Enable Voltage
VE
-0.5
8 Pin Ceramic DIP Single Channel Schematic
ANODE
2
+
ICC 8
IF
VF
3
–
CATHODE
IE
VCC
7
VE
6
VO
5
GND
Note: Enable pin 7. An external 0.01 F to 0.1 μF bypass capacitor
must be connected between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5400/01/0K
(
), Class 2
HCPL-5430/31/3K and HCPL-6430/31/3K
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current (High)
IF(ON)
6
10
mA
Supply Voltage, Output
VCC
4.75
5.25
V
Input Voltage (Low)
VF(OFF)
–
0.7
V
Fan Out (Each Channel)
N
–
5
TTL Loads
High Level Enable Voltage
VEH
2.0
VCC
V
Low Level Enable Voltage
VEL
0
0.8
V
Single Channel Product Only
5
Note
1
Electrical Characteristics
TA = -55° C to +125° C, 4.75 V ≤ VCC ≤ 5.25 V, 6 mA ≤ IF(ON) ≤ 10 mA, 0 V ≤ VF(OFF) ≤ 0.7 V, unless otherwise specified.
Group A10
Parameter
Sym.
Test Conditions
Subgroups
Low Level Output Voltage
VOL
IOL = 8.0 mA
(5 TTL Loads)
1, 2, 3
High Level Output Voltage
VOH
IOH = -4.0 mA
1, 2, 3
Output Leakage Current
IOHH
VO = 5.25 V,
VF = 0.7 V
1, 2, 3
Logic High
Supply Current
ICCH
VCC = 5.25 V,
VE = 0 V
1, 2, 3
Logic Low
Supply Current
Single Channel
Dual Channel
Single Channel
Min.
Typ.*
Max.
Units
Fig.
Notes
0.3
0.5
V
1
9
V
2
9
2.4
1, 2, 3
ICCL
Limits
Dual Channel
100
A
17
26
mA
34
52
19
26
38
52
1.85
Input Forward Voltage
VF
IF = 10 mA
1, 2, 3
1.0
1.35
Input Reverse Breakdown
Voltage
VR
IR = 10 A
1, 2, 3
3.0
4.8
Input-Output Insulation
Leakage Current
II-O
VI-O = 1500 Vdc,
RH ≤ 65%,
t=5s
1
Propagation Delay Time
Logic Low Output
tPHL
9, 10, 11
Propagation Delay Time
Logic High Output
tPLH
9, 10, 11
9, 10, 11
9
13
mA
13
V
4
9
V
9
1.0
A
2, 3
33
60
ns
5, 6, 7
4, 9
30
60
ns
5, 6, 7
4, 9
3
35
Pulse Width Distortion
PWD
ns
5, 6, 7
4, 9
Logic High Common
Mode Transient Immunity
|CMH|
VCM = 50 VP-P,
IF = 0 mA
9, 10, 11
500
3000
V/s
11
5, 9, 11
Logic Low Common
Mode Transient Immunity
|CML|
VCM = 50 VP-P,
IF = 6 mA
9, 10, 11
500
3000
V/s
11
5, 9, 11
Units
Fig.
Notes
Single Channel Product Only
Test Conditions
Group A10
Limits
Subgroups
Min.
Max.
2.0
Parameter
Sym.
Typ.*
Logic High Enable Voltage
VEH
1, 2, 3
Logic Low Enable Voltage
VEL
1, 2, 3
0.8
V
Logic High Enable Current
IEH
VE = 2.4 V
1, 2, 3
20
A
VE = 5.25 V
1, 2, 3
100
V
Logic Low Enable Current
IEL
VE = 0.4 V
1, 2, 3
-0.28
-0.4
mA
High Impedance State
Supply Current
ICCZ
VCC = 5.25 V,
VE = 5.25 V
1, 2, 3
22
28
mA
High Impedance State
Output Current
IOZL
VO = 0.4 V, VE = 2 V
1, 2, 3
-20
A
IOZH
VO = 2.4 V, VE = 2 V
20
VO = 5.25 V, VE = 2 V
100
*All typical values are at VCC = 5 V, TA = 25° C, IF = 8 mA except where noted.
6
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF = 8 mA, unless otherwise specified.
Parameter
Symbol
Typ.
Units
Test Conditions
Fig.
Input Current Hysteresis
IHYS
0.25
mA
VCC = 5 V
3
Input Diode Temperature Coefficient
VF
TA
-1.11
mV/°C
IF = 10 mA
4
Resistance (Input-Output)
RI-O
1012

VI-O = 500 V
2
Capacitance (Input-Output)
CI-O
0.6
pF
f = 1 MHz, VI-O = 0 V
2
Logic Low Short Circuit Output Current
IOSL
65
mA
VO = VCC = 5.25 V, IF = 10 mA
6, 9
Logic High Short Circuit Output Current
IOSH
-50
mA
VCC = 5.25 V, IF = 0 mA,
VO = GND
6, 9
Output Rise Time (10-90%)
tr
15
ns
5
Output Fall Time (90-10%)
tf
10
ns
5
Propagation Delay Skew
tPSK
30
ns
Power Supply Noise Immunity
PSNI
0.5
VP-P
48 Hz ≤ fac ≤ 50 MHz
Parameter
Symbol
Typ.
Units
Test Conditions
Input Capacitance
CIN
15
pF
f = 1 MHz, VF = 0 V,
Pins 2 and 3
Output Enable Time to Logic High
tPZH
15
ns
8, 9
Output Enable Time to Logic Low
tPZL
30
ns
8, 9
Output Disable Time from Logic High
tPHZ
20
ns
8, 9
Output Disable Time from Logic Low
tPLZ
15
ns
8, 9
Input Capacitance
CIN
15
pF
f = 1 MHz, VO = 0 V
Input-Input Leakage Current
II-I
0.5
nA
RH ≤ 65%, VI-I = 500 Vdc
Input-Input Resistance
RI-I
1012

VI-I = 500 V
8
Input-Input Capacitance
CI-I
1.3
pF
f = 1 MHz, VF = 0 V
8
10
Notes
12
7
Single Channel Product Only
Fig.
Notes
Dual and Quad Channel Product Only
Notes:
1. Not to exceed 5% duty factor, not to exceed 50 sec pulse width.
2. All devices are considered two-terminal devices: measured between
all input leads or terminals shorted together and all output leads or
terminals shorted together.
3. This is a momentary withstand test, not an operating condition.
4. tPHL propagation delay is measured from the 50% point on the rising
edge of the input current pulse to the 1.5 V point on the falling edge
of the output pulse. The tPLH propagation delay is measured from the
50% point on the falling edge of the input current pulse to the 1.5 V
point on the rising edge of the output pulse. Pulse Width Distortion,
PWD = |tPHL - tPLH|.
5. CML is the maximum slew rate of the common mode voltage that can
be sustained with the output voltage in the logic low state (VO(MAX)
< 0.8 V). CMH is the maximum slew rate of the common mode voltage
that can be sustained with the output voltage in the logic high state
(VO(MIN) > 2.0 V).
6. Duration of output short circuit time not to exceed 10 ms.
7. Power Supply Noise Immunity is the peak to peak amplitude of the
ac ripple voltage on the VCC line that the device will withstand and
still remain in the desired logic state. For desired logic high state,
VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.
7
8
8. Measured between adjacent input pairs shorted together for each
multichannel device.
9. Each channel.
10. Standard parts receive 100% testing at 25° C (Subgroups 1 and 9).
SMD, Class H and Class K parts receive 100% testing at 25° C, 125° C,
and -55° C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
11. Parameters are tested as part of device initial characterization and
after design and process changes. Parameters are guaranteed to
limits specified for all lots not specifically tested.
12. Propagation delay skew is defined as the difference between the
minimum and maximum propagation delays for any given group of
optocouplers with the same part number that are all switching at the
same time under the same operating conditions.
13. The HCPL-6430, HCPL-6431, and HCPL-643K dual channel parts
function as two independent single channel units. Use the single
channel parameter limits.
Figure 1. Typical logic low output voltage vs. logic low output current
Figure 2. Typical logic high output voltage vs. logic high output current
Figure 3. Typical output voltage vs. input forward current
Figure 4. Typical diode input forward current characteristic
8
PULSE GEN.
tr = tf = 5 ns
f = 500 kHz
25 % DUTY
CYCLE
INPUT
MONITORING
NODE
VCC
D.U.T.
IF
VCC
0.1 µF
100 Ω
30 pF
C2
GND
C1
15 pF
VO
5.0 V
OUTPUT
MONITORING
NODE
1.3 KΩ
2.5 KΩ
THE PROBE AND JIG CAPACITANCES
ARE REPRESENTED BY C1 AND C2.
ALL DIODES ARE 1N4150 OR EQUIVALENT.
Figure 5. Test circuit for tPLH, tPHL, tr, and tf
Figure 6. Typical propagation delay vs. ambient temperature
PULSE
GENERATOR
ZO = 50 Ω
tr = tf = 5 ns
1
IF
INPUT VE
MONITORING
NODE
D.U.T.
VCC
VCC
8
2
7
3
6
4
GND
Figure 7. Typical propagation delay vs. input forward current
5
5.0 V
S1
0.1 µF
VO
D1
1.3 KΩ
C1
30 pF
D2
D3
2.5 KΩ
D4
S2
Figure 8. Test circuit for tPHZ, tPZH, tPLZ, and tPZL . (single channel product only)
9
Figure 9. Typical enable propagation delay vs. ambient temperature.
(single channel product only)
IF
B
VCC = 5.0 V
D.U.T.
VCC
A
+
V
–FF
Figure 10. Propagation delay skew, tPSK, waveform
0.1 µF*
OUTPUT VO
MONITORING
NODE
GND
+ CL
15 pF
VCM
VCC = 5.25 V
+
–
PULSE GEN.
D.U.T.*
IF
+
VIN
VCC
–
2.1 V
100 W TYP.
ICC
IO
100 W
GND
CONDITIONS: IF = 10 mA
IO = 25 mA
TA = +125 °C
VDC = 3.0 V
* FOR SINGLE CHANNEL UNITS,
GROUND ENABLE PIN.
Figure 11. Test diagram for common mode transient immunity and typical
waveforms
10
Figure 12. Operating circuit for burn-in and steady state life tests
0.01 μF
MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DLA drawings
5962-89570, and 5962-89571.
Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
Data Rate and Pulse-Width Distortion Definitions
Propagation delay is a figure of merit which describes the
finite amount of time required for a system to translate information from input to output when shifting logic levels.
Propagation delay from low to high (tPLH) specifies the
amount of time required for a system’s output to change
from a Logic 0 to a Logic 1, when given a stimulus at the
input. Propagation delay from high to low (tPHL) specifies
the amount of time required for a system’s output to
change from a Logic 1 to a Logic 0, when given a stimulus
at the input (see Figure 5).
When tPLH and tPHL differ in value, pulse width distortion
results. Pulse width distortion is defined as |tPHL - tPLH| and
determines the maximum data rate capability of a distortion-limited system. Maximum pulse width distortion
on the order of 25-35% is typically used when specifying
the maximum data rate capabilities of systems. The exact
figure depends on the particular application (RS-232,
PCM, T-1, etc.).
These high performance optocouplers offer the advantages of specified propagation delay (tPLH, tPHL), and pulse
width distortion (|tPLH -t PHL|) over temperature and power
supply voltage ranges.
Applications
VCC1 = +5 V
DATA
IN
A
226 Ω 30 pF
HCPL-5400
VCC
GND 1
TOTEM
POLE
OUTPUT GATE
(e.g. 54AS1000)
DATA
OUT
Y
TTL
LSTTL
STTL
HCMOS
274 Ω
1
VCC2 = 5 V
0.1 μF
GND
GND 2
Y=A
2
Figure 13. Recommended HCPL-5400 interface circuit
VCC1 = +5 V
DATA
IN
A
464 Ω
HCPL-5400
VCC
STTL
DATA
OUT
Y
TTL
LSTTL
STTL
GND 1
1
OPEN
COLLECTOR
OUTPUT
GATE
(e.g. 54S05)
GND
GND 2
Y=A
Figure 14. Alternative HCPL-5400 interface circuit
11
VCC2 = 5 V
0.1 μF
2
226 Ω 30 pF
VCC1 = 5 V
DATA
IN A
TOTEM POLE
OUTPUT GATE
(e.g. 54AS1000)
DATA
IN A
GND 1
274 Ω
HCPL-5430
VCC
0.1 μF
TTL
LSTTL
STTL
HCMOS
TTL
LSTTL
STTL
HCMOS
274 Ω
VCC2 = +5 V
DATA
OUT Y
DATA
OUT Y
GND
Y=A
GND 2
226 Ω 30 pF
2
1
Figure 15. Recommended HCPL-5430 and HCPL-6430 interface circuit
464 Ω
VCC1 = +5 V
HCPL-5430
VCC
DATA
IN A
STTL OPEN COLLECTOR
OUTPUT GATE
(e.g. 54AS05)
DATA
IN A
GND 1
464 Ω
0.1 μF
TTL
LSTTL
HCMOS
STTL
TTL
LSTTL
HCMOS
STTL
VCC2 = +5 V
DATA
OUT Y
DATA
OUT Y
GND
Y=A
GND 2
2
1
Figure 16. Alternative HCPL-5430 and HCPL-6430 interface circuit
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Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9403E
AV02-3838EN - October 2, 2012
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