FAIRCHILD 100LVEL11

Revised January 2003
100LVEL11
3.3V ECL 1:2 Differential Fanout Buffer
General Description
Features
The 100LVEL11 is a low voltage 1:2 differential fanout
buffer. One differential input signal is fanned out to two
identical differential outputs. By supplying a constant reference level to one input pin a single ended input condition is
created.
■ Typical propagation delay of 330 ps
■ Typical IEE of 24 mA
■ Typical skew of 5 ps between outputs
■ Internal pull-down resistors on D
With inputs Open or both inputs at VEE, the differential Q
outputs default LOW and Q outputs default HIGH.
■ Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
The 100 series is temperature compensated.
■ Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up tests
■ Moisture Sensitivity Level 1
■ ESD Performance:
Human Body Model > 2000V
Machine Model > 200V
Ordering Code:
Package
Order Number
Number
Product
Code
Package Description
Top Mark
100LVEL11M
M08A
KVL11
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100LVEL11M8
(Preliminary)
MA08D
KV11
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Top View
Pin Descriptions
Pin Name
Description
Q0, Q0, Q1, Q1
ECL Data Outputs
D, D
ECL Data Inputs
VCC
Positive Supply
VEE
Negative Supply
© 2003 Fairchild Semiconductor Corporation
DS500775
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100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer
January 2003
100LVEL11
Absolute Maximum Ratings(Note 1)
PECL Supply Voltage (VCC) VEE = 0V
0.0V to +8.0V
Recommended Operating
Conditions
NECL Supply Voltage (VEE) VCC = 0V
0.0V to −8.0V
PECL Power Supply Operating
PECL DC Input Voltage (VI) VEE = 0V
0.0V to +6.0V
NECL DC Input Voltage (VI) VCC = 0V
0.0V to −6.0V
(VEE = 0V)
VCC = 3.0V to 3.8V
NECL Power Supply Operating
(VCC = 0V)
DC Output Current (IOUT)
Continuous
50 mA
Surge
100 mA
−40°C to +85°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
Storage Temperature (TSTG)
VEE = −3.8V to −3.0V
Free Air Operating Temperature (TA)
LVPECL DC Electrical Characteristics VCC = 3.3V; VEE = 0.0V (Note 2)
Symbol
−40°C
Parameter
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
IEE
Power Supply Current
24
28
24
28
25
30
mA
VOH
Output HIGH Voltage (Note 3)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 3)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single Ended)
1490
1825
1490
1825
1490
1825
mV
VIHCMR
Input HIGH Voltage Common Mode
VPP < 500mV
1.2
3.1
1.1
3.1
1.1
3.1
VPP ≥ 500mV
1.4
3.1
1.3
3.1
1.3
3.1
Range (Differential) (Note 4)
IIH
Input HIGH Current (Note 5)
IIL
Input LOW Current (Note 5)
150
150
150
D
0.5
0.5
0.5
D
−600
−600
−600
V
µA
µA
Note 2: Input and output parameters vary 1 to 1 with VCC. VEE can vary ± 0.3V.
Note 3: Outputs are terminated through a 50Ω Resistor to VCC − 2.0V.
Note 4: VIHCMR minimum varies 1 to 1 with VEE. VIHCMR maximum varies 1-to-1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPMIN and
1V.
Note 5: Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated Min or Max specification.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
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Symbol
−40°C
Parameter
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
IEE
Power Supply Current
24
28
24
28
25
30
mA
VOH
Output HIGH Voltage (Note 7)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 7)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single Ended)
−1810
−1475
−1810
−1475
−1810
-1475
mV
VIHCMR
Input HIGH Voltage Common Mode
VPP < 500mV
−2.1
−0.2
−2.2
−0.2
−2.2
−0.2
VPP ≥ 500mV
−1.9
−0.2
−2.0
−0.2
−2.0
−0.2
Range (Differential) (Note 8)
IIH
Input HIGH Current (Note 9)
IIL
Input LOW Current (Note 9)
150
150
150
D
0.5
0.5
0.5
D
−600
−600
−600
V
µA
µA
Note 6: Input and output parameters vary 1 to 1 with VCC. VEE can vary ±0.3V.
Note 7: Outputs are terminated through a 50Ω Resistor to VCC − 2.0V.
Note 8: VIHCMR minimum varies 1-to-1 with VEE. VIHCMR maximum varies 1 to 1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPMIN and
1V.
Note 9: Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated Min or Max specification.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
AC Electrical Characteristics VCC = 3.3V; VEE = 0.0V or VCC = 0.0V; VEE = −3.3V (Note 10)(Note 11)
Symbol
Parameter
−40°C
Min
Typ
25°C
Max
Min
385
235
85°C
Typ
Max
Min
330
405
250
Typ
Max
fMAX
Maximum Toggle Frequency
1
tPLH, tPHL
Propagation Delay to Output
215
tSKEW
Within Device Skew (Note 12)
5
20
5
20
5
20
Duty Cycle Skew (Note 13)
5
20
5
20
5
20
1
TBD
1
TBD
Units
Figure
Number
GHz
435
ps
Figure 1
ps
tJITTER
Cycle-to-Cycle Jitter
VPP
Input Swing
200
1000
200
1000
200
TBD
1000
mV
Figure 1
tr, tf
Output Rise Times Q (20% to 80%)
120
320
120
320
120
320
ps
Figure 2
Note 10: VEE can vary ±0.3V.
Note 11: Measured using a 750 mV input swing centered at VCC − 1.32V; 50% duty cycle clock source; tr = tf = 250 ps (20% - 80%) at fIN =1 MHz. All loading
with 50Ω to VCC − 2.0V.
Note 12: Within-device skew defined as identical transitions on similar paths through a device.
Note 13: Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device under identical conditions.
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100LVEL11
LVNECL DC Electrical Characteristics VCC = 0.0V; VEE = −3.3V (Note 6)
100LVEL11
Switching Waveforms
FIGURE 1. Differential to Differential Propagation Delay
FIGURE 2. Differential Output Edge Rates
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100LVEL11
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
5
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100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Number MA08D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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