HUF76445P3, HUF76445S3S
Data Sheet
October 1999
File Number
4676.3
75A, 60V, 0.0075 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
Features
JEDEC TO-220AB
JEDEC TO-263AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
HUF76445P3
HUF76445S3S
• Ultra Low On-Resistance
- rDS(ON) = 0.0065Ω, VGS = 10V
- rDS(ON) = 0.0075Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.semi.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Switching Time vs RGS Curves
D
Ordering Information
PART NUMBER
G
S
Absolute Maximum Ratings
PACKAGE
BRAND
HUF76445P3
TO-220AB
76445P
HUF76445S3S
TO-263AB
76445S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76445S3ST.
TC = 25oC, Unless Otherwise Specified
HUF76445P3,
HUF76445S3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
60
V
60
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±16
V
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
75
75
75
75
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
2.08
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
-55 to 175
oC
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Harris Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999.
HUF76445P3, HUF76445S3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
60
-
-
V
ID = 250µA, VGS = 0V , TC = -40oC (Figure 12)
55
-
-
V
VDS = 55V, VGS = 0V
-
-
1
µA
VDS = 50V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figures 9, 10)
-
0.0054
0.0065
Ω
ID = 75A, VGS = 5V (Figure 9)
-
0.0063
0.0075
Ω
ID = 75A, VGS = 4.5V (Figure 9)
-
0.0066
0.008
Ω
TO-220 and TO-263
-
-
0.48
oC/W
-
-
62
oC/W
-
-
515
ns
-
18
-
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
tr
-
325
-
ns
td(OFF)
-
39
-
ns
tf
-
135
-
ns
tOFF
-
-
260
ns
-
-
205
ns
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 75A
VGS = 4.5V, RGS = 2.2Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 75A
VGS = 10V,
RGS = 2.4Ω
(Figures 16, 21, 22)
-
12
-
ns
-
126
-
ns
td(OFF)
-
62
-
ns
tf
-
135
-
ns
tOFF
-
-
295
ns
-
124
150
nC
-
68
81
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 30V,
ID = 75A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
5
6
nC
Gate to Source Gate Charge
Qgs
-
14
-
nC
Reverse Transfer Capacitance
Qgd
-
30
-
nC
-
4965
-
pF
-
1250
-
pF
-
150
-
pF
MIN
TYP
MAX
UNITS
ISD = 75A
-
-
1.25
V
ISD = 35A
-
-
1.00
V
trr
ISD = 75A, dISD/dt = 100A/µs
-
-
100
ns
QRR
ISD = 75A, dISD/dt = 100A/µs
-
-
260
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
HUF76445P3, HUF76445S3S
Typical Performance Curves
80
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 10V
60
VGS = 4.5V
40
20
0.2
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
1000
175 - TC
I = I25
150
VGS = 10V
VGS = 5V
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
10-1
100
101
HUF76445P3, HUF76445S3S
Typical Performance Curves
(Continued)
1000
100µs
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
STARTING TJ = 25oC
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
1
10
STARTING TJ = 150oC
10
0.01
100
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
90
60
TJ = 175oC
30
120
TJ = 25oC
TJ = -55oC
0
VGS = 3.5V
90
60
VGS = 3V
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0
4
FIGURE 7. TRANSFER CHARACTERISTICS
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.5
20
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 75A
4
FIGURE 8. SATURATION CHARACTERISTICS
25
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 4V
0
3
2
2.5
3.5
VGS, GATE TO SOURCE VOLTAGE (V)
1.5
VGS = 10V
VGS = 5V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
150
ID = 35A
15
10
ID = 20A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 75A
2.0
1.5
1.0
0.5
5
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
200
HUF76445P3, HUF76445S3S
Typical Performance Curves
(Continued)
1.2
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
1.1
1.0
0.4
0.9
-80
-40
0
40
80
120
160
200
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS = CGS + CGD
CRSS = CGD
1000
COSS ≅ CDS + CGD
VGS = 0V, f = 1MHz
120
200
160
VDD = 30V
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 35A
2
0
0
1.0
10
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
60
90
120
150
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
800
1200
VGS = 10V, VDD = 30V, ID = 75A
VGS = 4.5V, VDD = 30V, ID = 75A
1000
td(OFF)
tr
SWITCHING TIME (ns)
SWITCHING TIME (ns)
80
8
100
0.1
40
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
10000
0
TJ , JUNCTION TEMPERATURE (oC)
800
600
tf
400
td(OFF)
600
tf
400
tr
200
200
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
50
HUF76445P3, HUF76445S3S
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76445P3, HUF76445S3S
PSPICE Electrical Model
.SUBCKT HUF76445 2 1 3 ;
rev 23 April1999
CA 12 8 6.50e-9
CB 15 14 6.50e-9
CIN 6 8 4.71e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
EBREAK 11 7 17 18 66.30
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
5
51
ESLC
11
-
RDRAIN
6
8
ESG
IT 8 17 1
LGATE
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 5.05e-9
LSOURCE 3 7 2.64e-9
+
17
EBREAK 18
50
EVTHRES
+ 19 8
+
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S2A
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.90e-3
RGATE 9 20 0.87
RLDRAIN 2 5 10
RLGATE 1 9 50.5
RLSOURCE 3 7 26.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.0e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DRAIN
2
5
12
14
13
13
8
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*453),3))}
.MODEL DBODYMOD D (IS = 4.45e-12 RS = 2.08e-3 TRS1 = 1.75e-3 TRS2 = 1.03e-6 CJO = 7.22e-9 TT = 7.21e-8 M = 0.60)
.MODEL DBREAKMOD D (RS = 1.23e-1 TRS1 = 0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 4.13e-9 IS = 1e-30 Vj = 1.0 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 1.90 KP = 5.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87)
.MODEL MSTROMOD NMOS (VTO = 2.31 KP = 275 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.16e-3 TC2 = 1.17e-7)
.MODEL RDRAINMOD RES (TC1 = 1.48e-2 TC2 = 2.93e-5)
.MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.87e-3 TC2 = -1.02e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.42e-3 TC2 = 9.21e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5.7 VOFF= -2.7)
VON = -2.7 VOFF= -5.7)
VON = -1.0 VOFF= 0.5)
VON = 0.5 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
HUF76445P3, HUF76445S3S
SABER Electrical Model
REV 23 April 1999
template ta76445 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 4.45e-12, cjo = 7.22e-9, tt = 7.21e-8, xti = 4.5, m = 0.60)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.13e-9, is = 1e-30, vj=1.0, m = 0.85 )
m..model mmedmod = (type=_n, vto = 1.90, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.31, kp = 275, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.65, kp = 0.12, is = 1e-30, tox = 1)
DPLCAP
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.7, voff = -2.7)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.7, voff = -5.7)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
LDRAIN
DRAIN
2
5
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
c.ca n12 n8 = 6.50e-9
c.cb n15 n14 = 6.50e-9
c.cin n6 n8 = 4.71e-9
72
ISCL
EVTHRES
+ 19 8
+
LGATE
i.it n8 n17 = 1
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.05e-9
l.lsource n3 n7 = 2.64e-9
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
21
DBODY
EBREAK
+
17
18
MSTRO
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/453))** 3))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 66.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
8
MWEAK
MMED
CIN
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.16e-3, tc2 = 1.17e-7
res.rdbody n71 n5 = 2.08e-3, tc1 = 1.75e-3, tc2 = 1.03e-6
res.rdbreak n72 n5 = 1.23e-1, tc1 = 0, tc2 = 0
res.rdrain n50 n16 = 1.9e-3, tc1 = 1.48e-2, tc2 = 2.93e-5
res.rgate n9 n20 = 0.87
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 50.5
res.rlsource n3 n7 = 26.4
res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 0
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.0e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.42e-3, tc2 = 9.21e-7
res.rvthres n22 n8 = 1, tc1 = -2.87e-3, tc2 = -1.02e-5
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76445P3, HUF76445S3S
SPICE Thermal Model
th
JUNCTION
REV 8 April 1999
HUF76445T
CTHERM1 th 6 6.45e-3
CTHERM2 6 5 3.00e-2
CTHERM3 5 4 1.40e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 tl 12.55
RTHERM1
RTHERM1 th 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1.28e-1
RTHERM5 3 2 1.93e-1
RTHERM6 2 tl 2.56e-2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76445T
4
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.45e-3
ctherm.ctherm2 6 5 = 3.00e-2
ctherm.ctherm3 5 4 = 1.40e-2
ctherm.ctherm4 4 3 = 1.65e-2
ctherm.ctherm5 3 2 = 4.85e-2
ctherm.ctherm6 2 tl = 12.55
RTHERM4
CTHERM4
3
RTHERM5
rtherm.rtherm1 th 6 = 3.24e-3
rtherm.rtherm2 6 5 = 8.08e-3
rtherm.rtherm3 5 4 = 2.28e-2
rtherm.rtherm4 4 3 = 1.28e-1
rtherm.rtherm5 3 2 = 1.93e-1
rtherm.rtherm6 2 tl = 2.56e-2
}
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
9
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029