IDT IDT70125L High-speed 2k x 9 dual-port static ram with busy & interrupt Datasheet

HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
– Commercial: 25/35/45/55ns (max.)
• Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
• BUSY output flag on Master; BUSY input on Slave
• INT flag for port-to-port communication
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by CE, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
OER
OE L
CE L
R/ WL
CER
R/WR
I/O0L - I/O8L
I/O0R-I/O 8R
I/O
Control
I/O
Control
(1,2)
BUSY R
BUSY L
A10L
A0L
Address
Decoder
MEMORY
ARRAY
11
NOTES:
1. 70121 (MASTER):
BUSY is non-tristated push-pull
output.
70125 (SLAVE):
BUSY is input.
2. INT is totem-pole
output.
CE L
OE L
R/ WL
(1,2)
A11R
Address
Decoder
A0R
11
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
INTL(2)
CE R
OE R
R/WR
INTR
(2)
2654 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
OCTOBER 1996
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.10
DSC-2654/4
1
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
DESCRIPTION (Cont'd):
Fabricated using IDT’s CMOS high-performance
technology, these devices typically operate on only 500mW of
power. Low-power (L) versions offer battery backup data
COMMERCIAL TEMPERATURE RANGE
retention capability with each port typically consuming 200µW
from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin
PLCC.
INTR
A10R
48
47
WR
BUSYR
49
CER
R/
50
52
VCC
51
CEL
WL
BUSYL
R/
INTL
4
46
1
8
9
45
10
44
11
43
IDT70121/125
J52-1
12
13
14
42
41
40
PLCC
TOP VIEW(3)
15
39
32
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O8R
I/O7R
Grade
Ambient Temperature
GND
VCC
Commercial
0°C to +70°C
0V
5.0V ± 10%
2654 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
33
31
30
29
28
27
34
26
35
20
25
36
19
24
18
23
37
22
38
17
21
16
I/O4L
I/O5L
I/O6L
I/O7L
I/O8L
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
2
OEL
A10L
5
7
A0L
6
INDEX
3
PIN CONFIGURATIONS (1,2)
2654 drw 02
Symbol
VCC
GND
Parameter
Supply Voltage
Supply Voltage
VIH
Input High Voltage
VIL
ABSOLUTE MAXIMUM RATINGS(1)
VTERM
(2)
TA
TBIAS
TSTG
IOUT
Typ.
5
0
Max.
5.5
0.0
Unit
V
V
2.2
–
6.0(2)
V
–
0.8
–0.5
(1)
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the orientation of the actual part-marking.
Symbol
Input Low Voltage
Min.
4.5
0
V
2654 tbl 03
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Rating
Commercial
Unit
Terminal Voltage
with Respect to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
–0.5 to +7.0
V
0 to +70
°C
–55 to +125
°C
–55 to +125
°C
50
mA
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Condition(2)
VIN = 3dV
VOUT = 3dV
Max.
9
10
Unit
pF
pF
NOTES:
2654 tbl 13
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
NOTES:
2654 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +
0.5V.
6.10
2
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
Symbol
|ILI|
Parameter
Test Condition
Input Leakage Current(5)
VCC = 5.5V, VIN = 0V to VCC
VCC = 5.5V, CE = VIH
VOUT = 0V to VCC
IOL = 4mA
IOH = –4mA
(5)
|ILO|
Output Leakage Current
VOL
VOH
Output Low Voltage
Output High Voltage
70121S
70125S
Min. Max.
70121L
70125L
Min. Max. Unit
—
10
—
5
µA
—
10
—
5
µA
—
2.4
0.4
—
—
2.4
0.4
—
V
V
NOTE:
1. At Vcc < 2.0V leakages are undefined.
2654 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (VCC = 5V ± 10%)
Symbol
Parameter
ICC
Dynamic Operating
Current (Both Ports
Active)
ISB1
Standby Current
(Both Ports—TTL
Level Inputs)
ISB2
Standby Current
(One Port—TTL
Level Inputs)
ISB3
ISB4
Full Standby
Current (Both Ports
CMOS Level Inputs)
Full Standby
Current (One Port
CMOS Level Inputs)
70121X25
70125X25
Test
Condition
Version
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
CE = VIL,Outputs Open,
Com’l.
S
L
CE"A" and CE"B" = VIH,
f = fMAX(2)
Com’l.
S
L
30
30
65
45
30
30
65
45
30
30
65
45
30
30
65
45
mA
CE"A"=VIL and CE"B"=VIH(5)
Com’l.
S
L
80
80
175
145
80
80
165
135
80
80
160
130
80
80
155
125
mA
Com’l.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
Com’l.
S
L
70
70
170
140
70
70
160
130
70
70
155
125
70
70
150
120
mA
f = fMAX(2)
Active Port Outputs Open,
f = fMAX(2)
CE"A" and CE"B" ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0(3)
CE"A"<0.2V and CE"B">VCC-0.2V(5
)
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V, Active Port
Outputs Open, f = fMAX(2)
125 260 125 250 125 245 125 240
125 220 125 210 125 205 125 200
NOTES:
1. “X” in part numbers indicates power rating (S or L).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST
CONDITIONS” of input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, TA=+25°C for Typical values, and they are not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6.10
mA
2654 tbl 05
3
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS (L Version Only)
70121L/70125L
Symbol
VDR
ICCDR
tCDR(3)
tR(3)
Parameter
Test Condition
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
VCC = 2.0V, CE ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V
Com’l.
Min.
Typ.(1)
Max.
Unit
2
—
0
—
100
—
—
—
1500
—
—
V
µA
ns
ns
tRC(2)
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
2654 tbl 06
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
VDR ≥ 2V
4.5V
4.5V
tCDR
CE
tR
VDR
VIH
VIH
2654 drw 03
5V
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1250Ω
1250Ω
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
DATAOUT
BUSY
INT
DATAOUT
775Ω
775Ω
30pF
5pF
2654 drw 04
2654 tbl 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
70121X25
70125X25
Symbol
Parameter
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1,2)
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power-Up Time(2)
tPD
Chip Disable to Power-Down Time(2)
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
—
—
—
0
0
—
0
—
—
25
25
12
—
—
10
—
50
35
—
—
—
0
0
—
0
—
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. “X” in part numbers indicates power rating (S or L).
6.10
—
35
35
25
—
—
15
—
50
45
—
—
—
0
0
—
0
—
—
45
45
30
—
—
20
—
50
55
—
—
—
0
0
—
0
—
—
55
55
35
—
—
30
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
2654 tbl 08
4
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2654 drw 05
tBDD
(3,4)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5,6)
tACE
CE
tAOE
(4)
(2)
tHZ
OE
tLZ
(1)
tHZ
VALID DATA
DATAOUT
tLZ
ICC
CURRENT
ISS
(2)
(1)
tPD
tPU
50%
(4)
50%
2654 drw 06
NOTES:
1. Timing depends on which signal is aserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low.
6. R/W = VIH, CE = V IL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.
6.10
5
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
70121X25
70125X25
Symbol
Parameter
Write Cycle
Write Cycle Time(3)
tWC
tEW
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
tWP
Write Pulse Width(6)
tWR
Write Recovery Time
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(5)
tWZ
Write Enabled to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2)
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
20
20
0
20
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
45
35
35
0
35
0
20
—
0
—
0
—
—
—
—
—
—
—
20
—
20
—
55
40
40
0
40
0
20
—
0
—
0
—
—
—
—
—
—
—
30
—
30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2654 tbl 09
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
4. “X” in part numbers indicates power rating (S or L).
5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.Although tDH and tow values will vary over voltage
and temperature. The actual tDH will always be smaller than the actual tOW.
6. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
(3)
tAW
tWR
CE
W
R/
tAS
tWP
tWZ
DATAOUT
(7)
(2)
(6)
tHZ
(7)
tOW
(4)
(4)
tDW
tDH
DATAIN
NOTES:
2654 drw 07
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
6.10
6
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC
ADDRESS
tAW
CE
tAS
R/
(6)
tEW
(3)
(2)
tWR
W
tDW
tDH
DATAIN
2654 drw 08
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
70121X25
70125X25
Symbol
Parameter
Busy Timing (For Master IDT70121 Only)
tBAA
tBDA
tBAC
tBDC
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
—
(1)
20
—
20
—
20
—
30
ns
—
20
—
20
—
20
—
30
ns
—
20
—
20
—
20
—
30
ns
—
20
—
20
—
20
—
30
ns
tWDD
Write Pulse to Data Delay
—
50
—
60
—
70
—
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
—
35
—
45
—
55
—
65
ns
tAPS
tBDD
tWH
(2)
Arbitration Priority Set-up Time
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
5
—
5
—
5
—
5
—
ns
—
30
—
30
—
35
—
45
ns
15
—
20
—
20
—
20
—
ns
0
—
0
—
0
—
0
—
ns
Busy Timing (For Slave IDT70125 Only)
tWB
Write to BUSY Input(4)
tWH
Write Hold After BUSY
15
—
20
—
20
—
20
—
ns
tWDD
Write Pulse to Data Delay(1)
—
50
—
60
—
70
—
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
—
35
—
45
—
55
—
65
ns
(5)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY“.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. “X” in part numbers indicates power rating (S or L).
6.10
2654 tbl 10
7
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
BUSY (1,2,3)
tWC
MATCH
ADDR 'A'
tWP
W'A'
R/
tDW
tDH
VALID
DATAIN 'A'
tAPS
(1)
MATCH
ADDR'B'
tBDA
tBDD
BUSY'B'
tWDD
VALID
DATAOUT 'B'
tDDD
(4)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT 70125).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
2654 drw 09
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
W'A'
R/
tWB
BUSY'B'
(1)
tWH
W'B'
R/
(2)
2654 drw 10
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
6.10
8
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1)
ADDR
L and R
ADDRESSES MATCH
CER
tAPS
CEL
tBAC
tBDC
BUSYL
2654 drw 12
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only).
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS (1)
tRC OR tWC
ADDR'A'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
tAPS
ADDR'B'
tBAA
tBDA
BUSY'B'
2654 drw 13
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
70121X25
70125X25
Symbol
Parameter
Interrupt Timing
tAS
Address Set-up Time
tWR
Write Recovery Time
tINS
Interrupt Set Time
tINR
Interrupt Reset Time
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
0
0
—
—
NOTE:
1. "X" in part numbers indicates power rating (S or L).
—
—
25
25
0
0
—
—
—
—
25
35
0
0
—
—
—
—
40
40
0
0
—
—
—
—
45
45
ns
ns
ns
ns
2654 tbl 11
6.10
9
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF INTERRUPT MODE
tWC
INTERRUPT SET ADDRESS
ADDR'A'
tAS(3)
(2)
tWR (4)
W'A'
R/
tINS(3)
INT'B'
NOTES:.
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2654 drw 14
TRUTH TABLES
TRUTH TABLE I –
NON-CONTENTION READ/WRITE CONTROL(4)
Left or Right Port(1)
OE
R/W CE
D0–8
X
H
X
Z
X
H
X
Z
L
H
H
L
L
L
X
L
H
DATAIN
DATAOUT
Z
Function
Port Disabled and in PowerDown Mode, ISB2 or ISB4
CER = CEL = H, Power-Down
Mode, ISB1 or ISB3
Data on Port Written Into Memory(2)
Data in Memory Output on Port(3)
High-impedance Outputs
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = VIL, data is not written.
3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
2654 tbl 12
TRUTH TABLE II – INTERRUPT FLAG(1,4)
R/WL
L
X
X
X
CEL
L
X
X
L
Left Port
OEL
X
X
X
L
A0L – A10L
7FF
X
X
7FE
INTL
X
X
L(3)
H(2)
R/WR
X
X
L
X
Right Port
CER
OER
X
L
L
X
X
L
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = VIH,' L' = VIL,' X' = DON’T CARE.
A0L – A10R
X
7FF
7FE
X
INTR
(2)
L
H(3)
X
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2654 tbl 13
6.10
10
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location 7FE (HEX), where a write is defined
as the CE = R/W = VIL per the Truth Table. The left port clears
the interrupt by access address location 7FE access when
CER = OER = VIL, R/W is a "Don't Care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
memory location 7FF (HEX) and to clear the interrupt flag
(INTR), the right port must access the memory location 7FF.
The message (9 bits) at 7FE or 7FF is user-defined, since it is
an addressable SRAM location. If the interrupt function is not
used, address locations 7FE and 7FF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
unintended write operations can be prevented to a port by
tying the busy pin for that port low.
The busy outputs on the IDT70121/125 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70121/125 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70121 RAM the busy pin
is an output of the part, and the busy pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the BUSY pins high. Once in slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation
can be programmed by tying the BUSY pins high. If desired,
IDT70125
IDT70121
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
MASTER
Dual Port
RAM
BUSYL
CE
BUSYR
BUSYL
BUSYL
BUSYL
CE
BUSYR
IDT70125
IDT70121
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
DECODER
FUNCTIONAL DESCRIPTION
The IDT70121/125 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70121/125 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
COMMERCIAL TEMPERATURE RANGE
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
BUSYR
2654 drw 15
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70121 (Master) and IDT70125 (Slave) RAMs.
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/ signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.10
W
11
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
J
52-pin PLCC (J52-1)
25
35
45
55
Speed in nanoseconds
L
S
Low Power
Standard Power
70121
18K (2K x 9-Bit) MASTER Dual-Port RAM
w/ Interrupt
18K (2K x 9-Bit) SLAVE Dual-Port RAM
w/ Interrupt
70125
2654 drw 16
6.10
12
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