ON NB7L572MNR4G 2.5v / 3.3v differential 4:1 mux input to 1:2 lvpecl clock/data fanout / translator Datasheet

NB7L572
2.5V / 3.3V Differential 4:1
Mux Input to 1:2 LVPECL
Clock/Data Fanout /
Translator
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Multi−Level Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The
INx/INx inputs includes internal 50 W termination resistors and will
accept differential LVPECL, CML, or LVDS logic levels. The
NB7L572 incorporates a pair of Select pins that will choose one of
four differential inputs and will produce two identical LVPECL output
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The NB7L572 INx/INx inputs, outputs and core logic are powered
by a 2.5 V $5% V or 3.3 V $10% power supply. The two differential
LVPECL outputs will swing 750 mV when externally terminated with
a 50 W resistor to VCC – 2 V, and are optimized for low skew and
minimal jitter.
The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN
Pb-free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7L572 is a member of the GigaComm™ family of high
performance clock products.
Input Data Rate > 10.7 Gb/s Typical
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 7 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, Accepts LVPECL, CML LVDS
150 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical
Operating Range: VCC = 2.375 V to 3.6 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 2
32
1
1
32
NB7L
572
AWLYYWWG
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
IN0
50W
VT0
50W
IN0
VREFAC0
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAM*
1
0
IN1
50W
VT1
50W
IN1
1
VREFAC1
IN2
50W
VT2
50W
IN2
2
Q0
Q0
Q1
Q1
3
VREFAC2
IN3
50W
VT3
50W
IN3
VREFAC3
SEL0
SEL1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NB7L572/D
IN3
VREFAC3
VT3
IN3
IN2
VREFAC2
VT2
IN2
32
31
30
29
28
27
26
25
NB7L572
Exposed Pad (EP)
IN0
1
24
GND
VT0
2
23
VCC
VREFAC0
3
22
Q1
IN0
4
21
Q1
IN1
5
20
VCC
VT1
6
19
NC
VREFAC1
7
18
SEL1
IN1
8
17
VCC
9
10
11
12
13
14
15
16
GND
VCC
Q0
Q0
VCC
NC
SEL0
VCC
NB7L572
Figure 1. Pinout Configuration (Top View)
Table 1. INPUT SELECT FUNCTION TABLE
SEL1*
SEL0*
Clock / Data Input Selected
0
0
IN0 Input Selected
0
1
IN1 Input Selected
1
0
IN2 Input Selected
1
1
IN3 Input Selected
*Defaults HIGH when left open.
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NB7L572
Table 2. PIN DESCRIPTION
Pin
Name
I/O
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML,
LVDS Input
Description
2, 6
26, 30
VT0, VT1
VT2, VT3
15
18
SEL0
SEL1
LVTTL/LVCMOS
Input
14, 19
NC
−
No Connect
10, 13, 16
17, 20, 23
VCC
−
Positive Supply Voltage. All VCC pins must be connected to the positive power supply
for correct DC and AC operation.
11, 12
21, 22
Q0, Q0
Q1, Q1
LVPECL Output
9, 24
GND
3
7
27
31
VREFAC0
VREFAC1
VREFAC2
VREFAC3
−
Output Voltage Reference for Capacitor−Coupled Inputs
−
EP
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND.
Non−inverted, Inverted, Differential Clock or Data Inputs.
Internal 100 W Center−tapped Termination Pin for INx / INx
Input Select pins, default HIGH when left open through a 28k−W pull−up resistor. Input
logic threshold is VCC/2. See Select Function, Table 1.
Inverted, Non−inverted Differential Outputs.
Negative Supply Voltage, connected to Ground
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left
open, and if no signal is applied on INx / INx input, then the device will be susceptible to self−oscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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NB7L572
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
> 4 kV
> 150 V
QFN32
Level 1
Input Pullup Resistor (RPU)
28 kW
Moisture Sensitivity (Note 3)
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
205
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
−0.5 to +4.0
V
VIN
Positive Input Voltage
GND = 0 V
−0.5 to VCC +0.5
V
VINPP
Differential Input Voltage |IN – IN|
1.89
V
Iout
LVPECL Output Current
50
100
mA
mA
IIN
Input Current Through RT (50 W Resistor)
$40
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient) (Note 4)
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case) (Note 4)
QFN−32
12
°C/W
Tsol
Wave Solder
265
°C
Continuous
Surge
0 lfpm
500 lfpm
v 20 sec
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
(Note 6)
Characteristic
Symbol
Min
Typ
Max
Unit
2.375
3.0
2.5
3.3
2.625
3.6
V
90
110
mA
POWER SUPPLY
VCC
Power Supply Voltage
VCC = 2.5V
VCC = 3.3 V
ICC
Power Supply Current for VCC (Inputs and Outputs Open)
LVPECL OUTPUTS
VOH
Output HIGH Voltage (Note 6)
VOL
Output LOW Voltage (Note 6)
VCC = 2.5 V
VCC = 3.3 V
VCC – 1145
1355
2155
VCC – 900
1600
2400
VCC – 825
1675
2475
mV
VCC = 2.5 V
VCC = 3.3 V
VCC – 2000
500
1300
VCC – 1700
800
1600
VCC – 1500
1000
1800
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 7)
VIH
Single−Ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth – 100
mV
Vth
Input Threshold Reference Voltage Range (Note 8)
1100
VCC – 100
mV
VISE
Single−Ended Input Voltage (VIH – VIL)
200
2400
mV
VCC – 1000
mV
VREFAC
VREF−AC
VCC – 1500
Output Reference Voltage (100 mA Load)
VCC – 1200
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 9)
VIHD
Differential Input HIGH Voltage (IN, IN)
1200
VCC
mV
VILD
Differential Input LOW Voltage (IN, IN)
0
VIHD – 100
mV
VID
Differential Input Voltage (IN, IN) (VIHD – VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 8)
800
VCC – 50
mV
IIH
Input HIGH Current IN/IN (VT IN/VT IN Open)
−150
150
mA
IIL
Input LOW Current IN/IN (VT IN/VT IN Open)
−150
150
mA
V
CONTROL INPUT (SELx Pin)
VIH
Input HIGH Voltage for Control Pin
2.0
VCC
VIL
Input LOW Voltage for Control Pin
GND
0.8
V
IIH
Input HIGH Current
40
mA
IIL
Input LOW Current
0
mA
55
W
−215
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with VCC.
6. LVPECL outputs loaded with 50 W to VCC − 2V for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB7L572
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 11)
Min
Typ
fMAX
Maximum Input Clock Frequency VOUT w 400 mV
Characteristic
7
8
GHz
fDATAMAX
Maximum Operating Data Rate NRZ, (PRBS23)
10
11
Gbps
VOUTPP
Output Voltage Amplitude (@ VINPPmin) (Figure 2 & 9)
(Note 12)
550
400
750
500
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs
Measured at Differential Cross−Point
125
300
150
tPD Tempco
Differential Propagation Delay Temperature Coefficient
tskew
Output – Output skew (within device) (Note 13)
Device – Device skew (tpd max – tpd min)
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
tJITTER
Additive Random Clock Jitter, RJ(RMS) (Note 14)
Data Dependent Jitter, DDJ (Note 15)
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
100
tr,, tf
Output Rise/Fall Times @ 1 GHz; (20% − 80%), VIN = 800 mV Q, Q
25
Symbol
fin ≤ 5 GHz
fin ≤ 7 GHz
@ 1 GHz INx/INx to Qx/Qx (Figure 9)
@ 50 MHz SELx to Qx (Figure 10)
Max
175
1000
115
45
fin v 7.0 GHz
fin v 10 Gbps
Unit
ps
fs/°C
0
10
50
ps
50
55
%
0.5
6
0.8
15
ps rms
ps pk−pk
1200
mV
65
ps
45
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC − 2 V. Input edge
rates 40 ps (20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at K28.5.
16. Input voltage swing is a single−ended measurement operating in differential mode.
800
VCC
750
700
INx
50 W
VTx
650
50 W
INx
600
0
1
2
3
4
5
6
7
8
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Input Structure
Figure 2. CLOCK Output Voltage Amplitude
(VOUTPP) / RMS Jitter vs. Input Frequency (fin) at
Ambient Temperature (typical)
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NB7L572
IN
VIH
Vth
IN
VIL
IN
IN
Vth
Figure 4. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 5. Differential Inputs
Driven Differentially
VIHmax
VILmax
Vth
VIH
Vth
VIL
IN
IN
IN
VIHmin
Vthmin
VIHD
VILD
VILmin
GND
Figure 6. Vth Diagram
VCC
Figure 7. Differential Inputs Driven Differentially
VIHDmax
VCMmax
VCMR
VID = |VIHD(IN) − VILD(IN)|
IN
VILDmax
IN
Q
VILDtyp
tPHL
VILDmin
GND
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHDmin
VCMmin
VINPP = VIH(IN) − VIL(IN)
IN
VIHDtyp
VID = VIHD − VILD
IN
tPLH
Figure 8. VCMR Diagram
SELx
Figure 9. AC Reference Measurement
VCC/2
VCC/2
tPHL
tPLH
Qx
Qx
Figure 10. SELx to Qx Timing Diagram
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NB7L572
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 11. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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NB7L572
VCC
VCC
VCC
VCC
NB7L572
LVPECL
Driver
IN
ZO = 50 W
50 W
VT = VCC − 2 V
ZO = 50 W
LVDS
Driver
50 W
ZO = 50 W
VEE
NB7L572
ZO = 50 W
VEE
VEE
VCC
VCC
50 W
VT = Open
IN
Figure 12. LVPECL Interface
IN
50 W
IN
VCC
VCC
NB7L572
CML
Driver
NB7L572
IN
ZO = 50 W
50 W
VT = VCC
ZO = 50 W
Differential
Driver
50 W
ZO = 50 W
IN
50 W
VT = VREFAC*
ZO = 50 W
IN
VEE
VEE
Figure 13. LVDS Interface
50 W
IN
VEE
VEE
Figure 15. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
Figure 14. Standard 50 W Load CML Interface
VEE
*VREFAC bypassed to ground with a 0.01 mF capacitor
VCC
VCC
ZO = 50 W
Single−
Ended Driver
VT = VREFAC*
NB7L572
IN
50 W
50 W
IN (open)
GND
GND
Figure 16. Capacitor−Coupled
Single−Ended Interface
(VT Connected to External VREFAC)
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NB7L572
ORDERING INFORMATION
Package
Shipping†
NB7L572MNG
QFN32
(Pb−Free)
79 Units / Rail
NB7L572MNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB7L572
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
SOLDERING FOOTPRINT*
5.30
EXPOSED PAD
16
K
3.20
32 X
17
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
8
32 X
0.63
E2
1
3.20
24
32
25
32 X b
0.10 C A B
5.30
e
32 X
0.05 C
0.28
BOTTOM VIEW
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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For additional information, please contact your local
Sales Representative
NB7L572/D
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