OKI MSM6782-01 Real time clock Datasheet

¡ Semiconductor
MSM6782-01
MSM6782-01
¡ Semiconductor
REAL TIME CLOCK
GENERAL DESCRIPTION
The MSM6782 - 01 is a CMOS Serial Interface Real Time Clock/Calendar.
The serial interface that can be controlled by mere 3 signal lines has minimized the number of
CPU terminals required .
The MSM6782 - 01 provides 30-second adjustment, oscillation stop detection, and periodic flag
setting and signal output in 4 diferent cycle periods.
The clock ranges are seconds, minutes, hours, days, months, years, and days of the week.
The interface supply voltage is 2.7V to 5.5V and the clock supply voltage is 2.0V to 5.5V.
The MSM6782 - 01 comes in an 8-pin DIP package or an 8-pin SOP package.
The MSM6782 - 01 is highly integrated and is suitable for use in a variety of portable applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Real time clock providing seconds, minutes, hours, days, months, and days of the week.
Serial interface controlled by 3 signal lines
A periodic interrupt output in 4 different cycle periods (or periodic waveform output)
Automatic leap year calendar
30-second adjustment controlled by software
Stop and restart of clock
Wide range of interface power supply: 2.7V to 5.5V
Wide range of clock power supply: 2.0V to 5.5V
32.768kHz external quart crystal
Low current consumption
8-pin plastic DIP (DIP8-P-300) (MSM6782-01RS)
8-pin plastic SOP (SOP8-P-250-K) (MSM6782-01MS-K)
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¡ Semiconductor
MSM6782-01
BLOCK DIAGRAM
XT
Clock/calendar
registers
OSC
XT
Control registers
(CD, CE, CF)
STD.P
Decoder
DATA I/O
Data buffer
Address counter
VDD
CLK
VSS
CE
PIN CONFIGURATION
STD.P 1
8 VDD
STD.P 1
8 VDD
DATA I/O 2
7 XT
DATA I/O 2
7 XT
CLK 3
6 XT
CLK 3
6 XT
CE 4
5 VSS
CE 4
5 VSS
8-Pin Plastic DIP
Note : The actual type name is displayed
as 6782-01.
8-Pin Plastic SOP
Note : The actual type name is displayed
as 82-01.
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MSM6782-01
¡ Semiconductor
PIN DESCRIPTION
• STD.P (Pin No. 1)
Periodic output of N-CH OPEN DRAIN type or interrupt signal output of N-CH OPEN
DRAIN type for the CPU. The periodic output is used to check the reference signal and
oscillation frequency.
This pin is set as periodic output or interrupt signal output by writing “1” or “0” to the INT/
STND bit.
This output is not inhibited by CE. For more information, see “FUNCTIONAL DESCRIPTION OF REGISTERS”.
• DATA I/O (Pin No.2)
Input/output pin for setting of WRITE mode or READ mode, writing of addresses, or
writing/reading of data.
This pin is used as an input or output pin in high impedance state depending on whether
WRITE mode or READ mode is selected in the first 8-bit data cycle after the rising of the CE
input pulse.
• CLK (Pin No. 3)
Shift clock input pin. Data is taken in on the rising edge of a shift clock pulse when in WRITE
mode and data is output when in READ mode.
• CE (Pin No. 4)
Chip enable input pin. “H” level on this pin means “enable”.
When this pin is low, the DATA I/O pin goes into high impedance state, and DATA I/O and
CLK are disabled inside the LSI and current stops flowing through those pins.
“L” level on this pin forces the TEST and REST bits of the CF registers and the fr flag to be set
to “0”.
When turning the power ON, set this pin to “L” level.
• XT, XT (Pin Nos. 7 and 6)
32.768kHz crystal is to be connected to these pins.
XT
C1
XT
MSM6782-01
XT
VDD
C2
When an external clock is used, it is to be input from XT, while XT should be left open.
The oscillation crystal and capacitors should be placed as close to the IC as possible.
The oscillation circuit and other signal lines on any side of the LSI should be distant from each
other.
• VDD, VSS (Pin No.5)
Power supply pins. VDD is used for positive supply and VSS is for negative supply.
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MSM6782-01
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Symbol
Rating
Ta = 25°C
Vss–0.3 to VDD+0.3
VDD
Input voltage
VI
Output voltage
VO
Storage temperature
Condition
Unit
–0.3 to 7.0
V
Vss–0.3 to VDD+0.3
—
TSTG
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Rating
Unit
Power supply voltage
Parameter
VDD
—
2.7 to 5.5
V
Clock power supply
VCLK
—
2.0 to 5.5
V
fX
—
32.768
kHz
TOP
—
–40 to +85
°C
Crystal frequency
Operating temperature
(Note) Clock power supply : Crystal oscillation and clock must be assured
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5.V, Ta = –40 to +85°C)
Parameter
Condition
MIN
—
0.8VDD
—
—
V
—
—
—
0.2VDD
V
All input pins
except XT
VI=VDD
—
—
1
mA
CE, CLK
—
–1
mA
CE, CLK
"H" Input Voltage
VIH
"L" Input Voltage
VIL
"H" Input Current (1)
IIH1
TYP MAX Unit
Applicable
terminal
Symbol
"L" Input Current (1)
IIL1
VI=VSS
—
"H" Input Current (2)
IIH2
VI=VDD
—
—
10
mA
DATA I/O
—
–10
mA
DATA I/O
0.2VDD
V
DATA I/O
"L" Input Current (2)
IIL2
VI=VSS
—
"L" Output Current (1)
VOL1
IO=1.0mA
—
—
"H" Output Current
VOH
IO=–400mA
0.8VDD
—
—
V
DATA I/O
"L" Output Current (2)
VOL2
IO=1.0mA
—
—
0.2VDD
V
STD.P
OFF Leak Current
VOFLK
VO=VDD
—
—
10.0
mA
STD.P
Current Consumption(1)
VDD1
—
—
20.0
mA
VDD
Current Consumption(2)
VDD2
fX=32.768kHz VDD=5V
VI(CE)=0V
VDD=2V
—
—
2.5
mA
VDD
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¡ Semiconductor
• AC Characteristics
(VDD = 2.7 to 5.5V, Ta = –40 to +85°C)
Symbol
Condition
MIN
TYP
MAX
Unit
CLK "H" Pulse Width
Parameter
tWH
—
300
—
—
ns
CLK "L" Pulse Width
tWL
—
300
—
—
ns
CE Setup Time
tCS
—
150
—
—
ns
CE Hold Time
tCH
—
200
—
—
ns
CE Recovery Time
tCR
—
300
—
—
ns
CLK Setup Time
tCKS
—
20
—
—
ns
—
—
ns
CLK Hold Time
tCKH
—
20
WRITE Data Setup Time
tDS
—
50
—
—
ns
—
—
ns
WRITE Data Hold Time
tDH
—
50
READ Data Delay Time
tRD
CL = 50pF
—
—
250
ns
Output Disable Delay Time
tRZ
—
—
—
100
ns
Input Rise, Fall Time
tRF
—
—
—
20
ns
(Note) See Timing Chart.
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MSM6782-01
TIMING CHART
tCKS
tCS
tWL
tWH
VIH
tCH
tCKH
VIH
CLK
VIL
CE
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
tCR
WRITE mode
CLK
tDS
tDH
VIL
VIH
VIH
VIL
DATA I/O
VIH
VIL
READ mode
tRF tRD
CLK
DATA I/O
VIH
VIL
tRF
VIH
VIL
VOH
VOL1
HiZ
tRZ
CE
VIL
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FUNCTIONAL DESCRIPTION
REGISTER TABLE
HEX A3A2A1A0
Register
name
D3
(MSB)
D2
D1
D0
(LSB)
Count
range
S1
s8
s4
s2
s1
0 to 9
1-second digit register
Note
0
0 0 0 0
1
0 0 0 1
S10
fO
s40
s20
s10
0 to 5
10-second digit register
2
0 0 1 0
MI1
mi8
mi4
mi2
mi1
0 to 9
1-minute digit register
3
0 0 1 1
MI10
fr
mi40
mi20
mi10
0 to 5
10-minute digit register
4
0 1 0 0
H1
h8
h4
h2
h1
0 to 9
1-hour digit register
5
0 1 0 1
H10
fr
PM/AM
h20
h10
6
0 1 1 0
D1
d8
d4
d2
d1
0 to 9
1-day digit register
7
0 1 1 1
D10
fr
*
d20
d10
0 to 3
10-day digit register
8
1 0 0 0
MO1
mo8
mo4
mo2
mo1
0 to 9
1-month digit register
9
1 0 0 1
MO10
fr
*
*
mo10
0 to 1
10-month digit register
A
1 0 1 0
Y1
y8
y4
y2
y1
0 to 9
1-year digit register
B
1 0 1 1
Y10
y80
y40
y20
y10
0 to 9
10-year digit register
0 to 1, 2 10-hour digit register
C
1 1 0 0
W
fr
w4
w2
w1
0 to 6
Week digit register
D
1 1 0 1
CD
30-secADJ
IRQ-F
CAL/HW
HOLD
—
Control register D
E
1 1 1 0
CE
t1
t0
INT/STND
MASK
—
Control register E
F
1 1 1 1
CF
TEST
24/12
STOP
REST
—
Control register F
• The relation between the register's bit 0 and bit 1 is logically positive as 0=”L” and 1=”H”.
• The counted values are in BCD notation.
For example, with 1-year register (Y1), (y8, y4, y2, y1) = (0, 0, 1, 0) means the last digit (“2”) of
“1992”.
• Bit * also can be used as RAM.
• It is unexecutable to write data into the IRQ-F bit.
The IRQ-F bit is set to “1” when a specified carry determined by the combination of t1 and t0
is executed.
The IRQ-F bit holds “1” until the reading of CD is complete and is reset to “0” automatically
after the reading of CD is complete .
• The bit fo (OSC FLAG) memorizes that oscillation stops.
This bit is used to monitor the battery.
This bit is cleared by writing a “0”. (A “1” also can be written into this bit.)
• The bit fr (READ FLAG) goes “0” when the CE pin is set at “L” level and goes “1” when a carry
occurs for 1-second digit while the CE input is at “H” level.
Thus, it is possible to judge whether a carry occurs for 1-second digit during the reading of
the clock register (CE input = “H”).
If the bit fr is set at “1”, it is required to read the clock register once more.
• The “1” of the PM/AM bit indicates PM and its “0” indicates AM.
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MSM6782-01
FUNCTIONAL DESCRIPTION OF REGISTERS
Registers S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W
• These are abbreviations for Second1, Second10, MInute1, MInute10, Hour1, Hour10, Day1,
Day10, MOnth1, MOnth10, Year1, Year10, Week.
These values are in BCD notation.
• Refer to the REGISTER TABLE for more detalied information.
All registers are logically positive.
For example, (S8, S4, S2, S1) = 1001 means 9 seconds.
The * bit in the register table is writable/readable and can be used as RAM.
• Writing non-existant data may cause a clocking error.
• PM/AM, h20, h10
a) In 12-hour mode
The existant time is AM 12:00 through AM 11:00 and PM 12:00 through PM 11:00.
It is impossble to write data into the h20 bit which is fixed to “0” unconditionally. The h20
bit is not set by clocking.
b) In 24-hour mode
The existant time is 0:00 clock through 23:00 clock.
The PM/AM bit written is ignored and read out as “0” unconditionally.
• Registers Y1, Y10, and Leap Year
When using the Christian Era calendar, Y1 and Y10 are assigned to the last 2 digits of the year
of Christian Era.
The MSM6782 - 01 is capable of automatically identifying a leap year when the last 2-digit
number of the year can be divided by four. The last 2-digit number 99 changes to 00 next year.
• Register W
The count range of the register W is 0 ~ 6. The following table shows a possible bit data
definition.
W4
W2
0
0
0
Sunday
0
0
1
Monday
0
1
0
Tuesday
0
1
1
Wednesday
1
0
0
Thursday
1
0
1
Friday
1
1
0
Saturday
W1 Day of Week
• fo Flag
The fo flag bit memorizes that oscillation stops and is used to monitor the output of the battery.
The “1” of this bit indicates stop of oscillation. This bit is cleared by writing “0”. It is not
permitted to write “1” into this bit.
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• fr Flag
The fr flag bit indicates a carry when the CE input is at “H” level.
This bit is checked when the clock/calendar registers are read out. If this bit is set to “1”, it
is possible to read out these registers without using the HOLD bit.
This bit is cleared by setting the CE input to “L” level.
CD REGISTER (Control D Register)
• 30-sec ADJ (30-second adjustment bit)
When writing to this bit, if the second digits are smaller than 30, the second digits are reset
to 00, and if it is larger than 30, the second digits are reset to 00 and a carry into the minute
digit is executed. Data can not be written into the S1 ~ W registers and a “1” can not be written
into the REST bit of the CF register 125ms after writing into this bit because internal processing
is being executed. This bit holds “1” 125ms after writing, and returns to “0” automatically.
Therefore, data should be written into the S1 ~ W registers after checking that this bit has
returned to “0”.
• IRQ - F
This bit is set to “1” and the STD.P output goes low in the cycle period specified by the
combination of bit t1 and bit t0 of the CE register. If INT/STND = “1”, the bit status “1” and
output level “L” are kept until reading of the CD register is complete.
After the CD register is read out, the IRQ - F bit returns to “0” and the STD.P output goes into
high impedance automatically.
If INT/STD = “0”, the IRQ -F bit returns to “0” about 7.8 ms later or immediately after the CD
register is read out, and the STD.P returns to “high impedance” about 7.8 ms later.
• CAL/HW (Clock range switching bit)
CAL/HW = “1” : Seconds, minutes, hours, days, month, year, day of week
CAL/HW = “0” : Seconds, minutes, hours, day of week
If this bit is “0”, the D1, D10, MO1, MO10, Y1, Y10 registers can be used as 4-bit data RAM and
the * bits and fr bits of the D10 and MO10 registers also can be used as independent RAM,
because these registers stop clock operation.
• HOLD
“1” of this bit inhibits a carry into 1-second digit.
Clock operation continues before reaching a second.
During Hold = “1”, if a carry occurs, the S1 counter is incremented by 1 second after Hold =
“0”.
This bit is cleared to zero by writing “0”.
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CE REGISTER (Control E Register)
•
t1, t0
INT/STND bit = “1” : Setting of interrupt period
INT/STND bit = “0” : Setting of periodic waveform
t1
t0
0
0
1/64 second
Period
0
1
1 second
1
0
1 minute
1
1
1 hour
The duration that the periodic waveform output is at “L” level is about 7.8ms.
t1 and t0 determine the output timing of the STD.P output.
e.g.) When t1=“1”, t0=“1”, MASK=“0”
12:00PM
STD.P output
when INT/STND="1"
STD.P output
when INT/STND="0"
1:00PM
High impedance
"L" level
High impedance
"L" level
When writing into the 30-sec ADJ bit, a carry can occur.
Therfore, if (t1, t0) = (1, 0), (1, 1), the STD.P output may sometime be at “L” level. When INT/
STND=”0", this “L” level is kept for a maximum of 9.8ms after under-second digits in 30-sec
ADJ is cleared (the 30-sec ADJ flag returns to “0”).
If the selected interrupt period is 1 second, 1 minute, or 1 hour, and if a carry occurs during the
time the S1, S10, MI1, MI10 registers are overwritten using the HOLD bit, and if data written
in these registers determines the interrupt timing set by the carry, the STD.P output will go to “L”
level after HOLD=”0". (IRQ-F will is set to “1”)
In other cases, writing to the S1, S10, MI1, MI10, H1 registers do not change the STD.P output.
• INT/STND (interrupt-to-Standard waveform switching bit)
INT/STND = “1” : “1” of the IRQ-F bit and “L” level on the STD.P output are kept until IRQF (CD register) is read out.
INT/STND = “0” : “1” of the IRQ-F bit returns to “0” after a certain time elapses (after about
7.8ms) or when IRQ-F is read out.
“L” level on the STD.P output returns to high impedance after a certain
time elapses.
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• MASK
“1” of the MASK bit inhibits the setting of “1” to the IRQ-F flag and sets the STD.P output to
the high impedance state.
Interrupt mode (INT/STND=”1")
"1"
MASK bit
"1"
"0"
"0"
No interrupt is generated because
of MASK bit="1".
High impedance
STD.P output
"L" level
"1"
IRQ-F
"0"
Interrupt timing
IRQ-F is read out.
Periodic timing waveform output mode (INT/STND=”0")
"1"
MASK bit
"0"
"1"
"0"
No "L" level is output because
of MASK bit ="1".
High impedance
STD.P output
"L" level
"1"
IRQ-F
"0"
Output timing
Auto-return
(duration of "L" is about 7.8ms)
When the IRQ-F bit is read out before auto-return, the IRQ-F bit goes to “0”, and the STD.P
output keeps “L” level for about 7.8ms, then goes into the high impedance state.
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MSM6782-01
CF REGISTER (Control F Register)
• TEST
The TEST bit is used for testing by OKI and should be set to “0”.
This bit can be cleared to “0” by setting the CE pin to “L” level.
•
24/12
This bit is used to switch between 24-hour system and 12-hour system.
24/12 = “1” : 24-hour system without PM/AM
24/12 = “0” : 12-hour system with PM/AM
When the 24/12 bit is overwritten, data in the H1 ~ W registers may become undefined.
Therefore, it is required to newly set those registers again.
• STOP
“1” of this bit stops clocking and “0” restarts clocking.
• REST
“1” of this bit clears under-second-time to zero and at the same time stops clocking. “0” of
this bit restarts clocking.
Take care not to set the TEST bit to “1” when writing “0” into the REST bit.
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Usage
Functional Description
Writing and reading are executed in units of 4 bits after the CE input goes high. If the CE input
goes low before 4-bit data input is complete, the 4-bit data written when the CE input goes low
is ignored. (Data written before the CE input goes low is valid)
Writing and reading are executed starting from the LSB.
(WRITE)
1) The first 4 bits that are input after the CE input goes high are specified as “3” indicating the
WRITE mode. The address to be written is set into the second 4 bits.
2) The third 4 bits are written into the previously-set address.
The following 4-bit data are sequentially written into automatically-incremented addresses.
3) The address is automatically incremented in a loop way where address F is followed by
address 0.
CE
CLK
Ø
I/O
Ø
Ø
Ø
Ø
Ø
Ø
Ø
D0 D1 D2 D3 D0 D1 D2 D3
WRITE mode
setting code
Ø
Ø
Ø
Ø
D0 D1 D2 D3
Setting address
(N)
Data WRITE
address(N)
Ø
Ø
Ø
Ø
Ø
D0 D1 D2 D3
D0
Data WRITE
address(N+1)
(READ)
1) The first 4 bits that are input after the CE input goes high are specified as “C” indicating the
READ mode.
The address to be read is set into the second 4 bits.
2) The third 4-bit data is read from the previously-set address.
The following 4-bit data are sequentially read from automatically incremented addresses.
3) The address is automatically incremented in a loop way where address F is followed by
address 0.
CE
Æ The LSI is in the output mode.
CLK
Ø
I/O
Ø
Ø
Ø
Ø
Ø
Ø
Ø
D0 D1 D2 D3 D0 D1 D2 D3
READ mode
setting code
Setting address
(N)
Ø
Ø
Ø
Ø
D0 D1 D2 D3
Data READ
address(N)
Ø
Ø
Ø
Ø
D0 D1 D2 D3
Ø
D
Data READ
address(N+1)
If a character other than “C” or “3” is specified to the mode setting code, the following data
is ignored and the DATA I/O pin keeps the input state.
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Power Supply
Start
• When the power is turned ON, all registers
and the STD.P output are undefined.
Power ON
TEST ¨ 0
24/12 ¨ *1
STOP ¨ 1
REST ¨ 1
*1 = "0" OR "1"
Write data into registers S1 - W
TEST ¨ 0
24/12 ¨ *1
STOP ¨ 0
REST ¨ 0
30-sec.ADJ ¨ 0
IRQ-F ¨ 0
CAL/HW ¨ *2
HOLD ¨ 0
*2 = "0" OR "1"
Clock starts
Reading of registers S1 ~ W
Reading data from
registers S1 - W
N
fr = 0
Y
Note 1)
Note 2)
Data in registers CD, CE, CF, or registers S1 to W which are used as RAM can be read
out without using fr.
Checking fr is complete by checking only the last digit of fr which has been read out.
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Writing data to S1 - W
Method 1 : When under-second data is not stored
TEST ¨ 0
24/12 ¨ *1
STOP ¨ 1
REST ¨ 1
*1 = "0" OR "1"
Write data into S1 ~ W
TEST ¨ 0
24/12 ¨ *1
STOP ¨ 0
REST ¨ 0
Clock starts
Method 2 : When under-second data is stored ( This method is used for switching summer time).
HOLD ¨ 1
100ms WAIT
Write data into
S1 ~ W
HOLD ¨ 0
200ms WAIT
134
All the operations must be finished within 1 second.
Otherwise, seconds may be lost.
¡ Semiconductor
MSM6782-01
Writing 30-sec ADJ bit
Method 1
30-sec ADJ ¨ 1
Read 30-sec ADJ bit
30-sec ADJ = 0
N
Y
Method 2
30-sec ADJ ¨ 1
125ms WAIT
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REFERENCE DATA
MSM6782-01
XT
XT
Crystal quartz : Citizen-made CFS-308
CG
CG = 18pF
CD = 18pF
CD
Capacitance dependency of oscillation frequency
60
C = 15pF
Supply voltage dependency of oscillation frequency
10
D
Df/f(ppm)
20
Df/f(ppm)
CD = 18pF
CD = 24pF
CD = 33pF
40
0
–20
0
–40
–10
–60
0
10
20
CG(pF)
30
40
Supply voltage dependency of IDD
IDD(mA)
20
10
0
2
136
3
4
VDD(V)
5
6
2
3
4
VDD(V)
5
6
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