Sony CXD3511AQ Digital signal driver/timing generator Datasheet

CXD3511AQ
Digital Signal Driver/Timing Generator
Description
The CXD3511AQ incorporates digital signal
processor type RGB driver, color shading correction,
selectable delay line and timing generator functions
onto a single IC. Operation is possible with a system
clock up to 200 [MHz] (max.). This IC can process
video signals in bands up to UXGA standard, and
can output the timing signals for driving various Sony
LCD panels such as UXGA, SXGA and XGA.
Features
• Various picture quality adjustment functions such
as user adjustment, white balance adjustment and
gamma correction
• OSD MIX, black frame processing, mute and
limiter functions
• LCD panel color shading correction function
• Selectable delay line
• Drives various Sony data projector LCD panels
such as UXGA, SXGA and XGA
• Controls the CXA3562AR and CXA7000R sampleand-hold drivers
• Line inversion and field inversion signal generation
• Supports AC drive of LCD panels during no signal
240 pin QFP (Plastic)
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VDD1
VSS – 0.5 to +3.0
V
VDD2
VSS – 0.5 to +4.0
V
• Input voltage
VI
VSS – 0.5 to VDD1 + 0.5 V
• Output voltage
VO
VSS – 0.5 to VDD1 + 0.5 V
• Storage temperature
Tstg
–55 to +125
°C
• Junction temperature
Tj
125
°C
Recommended Operating Conditions
2.3 to 2.7
• Supply voltage
VDD1
VDD2
3.0 to 3.6
• Operating temperature
Topr
–20 to +75
V
V
°C
Applications
LCD projectors and other video equipment
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02401-PS
CXD3511AQ
Block Diagram
8×2×3
R, G, B IN
2×2×3
R, G, B OSD
10 × 2 × 3
DSD
2
YM
R, G, B OUT
2
YS
PCTL
PARALLEL I/F
PCLK
PDAT
10
CLKOUT
CTRL
PLL
TG
CLKC
CLKP
RGT, DWN
PCG, BLK, HST,
ENBR, ENBL, VSTR,
VSTL, VCKR, VCKL,
HCK1, DCK1, DCK2,
HCK2, DCK1X, DCK2X,
XRGT, FRP, XFRP,
PRG, DENB, CLP,
PO1, PO2, PO3, PO4,
PO5, PST, HD1, HD2
D Q
Q
CLKN
CLKSEL1
CLKSEL2
PLLDIV
HDIN
Direct Clear
VDIN
XCLR1
XCLR2
XCLR3
–2–
CXD3511AQ
R1OUT8
R2OUT9
VSTR
VCKR
ENBR
VDD2
VSS
DCK2
DCK2X
VSS
DCK1X
DCK1
VSS
HCK1
HCK2
RGT
XRGT
VDD2
VSS
HST
BLK
ENBL
VCKL
VDD2
VDD1
VSTL
DWN
CTRL
PCG
VSS
PST
PO3
PO2
PO1
HD2
VDD1
FRP
XFRP
SHST
DENB
PRG
VDD1
VSS
PO4
CLP
PO5
HD1
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
VDD2
VSS
R1IN7
R1IN6
R1IN5
R1IN4
R1IN3
Pin Configuration
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
R1IN2 181
120 R1OUT7
R1IN1 182
119 R1OUT6
R1IN0 183
118 R1OUT5
R2IN7 184
117 R1OUT4
R2IN6 185
116 R1OUT3
VDD2 186
115 VSS
VSS 187
114 VDD2
R2IN5 188
113 R1OUT2
R2IN4 189
112 R1OUT1
R2IN3 190
111 R1OUT0
R2IN2 191
110 R2OUT9
R2IN1 192
109 R2OUT8
R2IN0 193
108 R2OUT7
G1IN7 194
107 R2OUT6
G1IN6 195
106 R2OUT5
G1IN5 196
105 R2OUT4
VDD1 197
104 R2OUT3
VSS 198
103 R2OUT2
G1IN4 199
102 VSS
G1IN3 200
101 VDD1
G1IN2 201
100 VDD2
G1IN1 202
99 R2OUT1
G1IN0 203
98 R2OUT0
G2IN7 204
97 G1OUT9
G2IN6 205
96 G1OUT8
G2IN5 206
95 G1OUT7
G2IN4 207
94 G1OUT6
G2IN3 208
93 G1OUT5
VDD1 209
92 G1OUT4
VSS 210
91 G1OUT3
G2IN2 211
90 VSS
G2IN1 212
89 VDD1
G2IN0 213
88 G1OUT2
B1IN7 214
87 G1OUT1
B1IN6 215
86 G1OUT0
B1IN5 216
85 G2OUT9
B1IN4 217
84 VDD2
B1IN3 218
83 G2OUT8
B1IN2 219
82 G2OUT7
B1IN1 220
81 G2OUT6
VDD1 221
80 G2OUT5
VSS 222
79 G2OUT4
B1IN0 223
78 VSS
B2IN7 224
77 VDD1
B2IN6 225
76 G2OUT3
B2IN5 226
75 G2OUT2
B2IN4 227
74 G2OUT1
B2IN3 228
73 G2OUT0
B2IN2 229
72 B1OUT9
B2IN1 230
71 B1OUT8
B2IN0 231
70 B1OUT7
R1OSD1 232
69 B1OUT6
R1OSD0 233
68 B1OUT5
VDD2 234
67 VSS
VSS 235
66 VDD2
–3–
B2OUT9
B2OUT8
B2OUT7
B2OUT6
B2OUT5
VSS
VDD2
B2OUT4
B2OUT3
B2OUT2
B2OUT1
B2OUT0
VSS
VSS
CLKOUT
PLLDIV
CLKSEL2
VSS
VDD1
CLKSEL1
VDD2
CLKP
CLKN
VDD1
VDD1
CLKC
VSS
VSS
VDIN
HDIN
VSS
XCLR3
XCLR2
XCLR1
VDD1
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
B2OSD0
PDAT5
B2OSD1
VSS
VSS
VDD2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PDAT6
8
PDAT7
7
PDAT8
6
PCLK
5
PDAT9
4
PCTL
3
YS2
2
YM2
1
VDD2
61 B1OUT0
G2OSD0
62 B1OUT1
YM1 240
G2OSD1
63 B1OUT2
B1OSD0 239
YS1
64 B1OUT3
B1OSD1 238
R2OSD0
65 B1OUT4
G1OSD0 237
R2OSD1
G1OSD1 236
CXD3511AQ
Pin Description
Pin
No.
Symbol
I/O
Description
Input pin
processing for
open status
1
YS1
I
OSD YS input (port 1)
L
2
R2OSD1
I
OSD Red data input (port 2)
—
3
R2OSD0
I
OSD Red data input (port 2)
—
4
G2OSD1
I
OSD Green data input (port 2)
—
5
G2OSD0
I
OSD Green data input (port 2)
—
6
VDD2
—
I/O power supply
—
7
VSS
—
GND
—
8
B2OSD1
I
OSD Blue data input (port 2)
—
9
B2OSD0
I
OSD Blue data input (port 2)
—
10
YM2
I
OSD YM input (port 2)
L
11
YS2
I
OSD YS input (port 2)
L
12
PCTL
I
Parallel I/F control signal input
H
13
PCLK
I
Parallel I/F clock input
—
14
PDAT9
I
Parallel I/F data input
—
15
PDAT8
I
Parallel I/F data input
—
16
PDAT7
I
Parallel I/F data input
—
17
PDAT6
I
Parallel I/F data input
—
18
VDD2
—
I/O power supply
19
VSS
—
GND
—
20
PDAT5
I
Parallel I/F data input
—
21
PDAT4
I
Parallel I/F data input
—
22
PDAT3
I
Parallel I/F data input
—
23
PDAT2
I
Parallel I/F data input
—
24
PDAT1
I
Parallel I/F data input
—
25
VDD1
Internal operation power supply
—
26
PDAT0
I
Parallel I/F data input
—
27
XCLR1
I
External clear (Low: reset)
H
28
XCLR2
I
External clear (Low: reset)
H
29
XCLR3
I
External clear (Low: reset)
H
30
VSS
GND
—
31
HDIN
I
Horizontal sync signal input
—
32
VDIN
I
Vertical sync signal input
—
33
VSS
—
GND
—
34
VSS
—
GND
—
35
CLKC
I
Clock input (CMOS input)
—
36
VDD1
—
Internal operation power supply
—
37
VDD1
—
Internal operation power supply
—
—
—
–4–
CXD3511AQ
Pin
No.
Symbol
I/O
Description
Input pin
processing for
open status
38
CLKP
I
Clock input (small-amplitude differential input, positive polarity)
—
39
CLKN
I
Clock input (small-amplitude differential input, negative polarity)
—
40
VDD2
—
I/O power supply
—
41
CLKSEL1
Input clock selection. (High: CLKC, Low: CLKP, CLKN)
L
42
VDD1
—
Internal operation power supply
—
43
VSS
—
GND
—
44
CLKSEL2
I
Internal clock path selection.
(High: no frequency division, Low: frequency division)
L
45
PLLDIV
I
Internal PLL setting. (High: 55MHz or less, Low: 55MHz or more)
L
46
VSS
—
GND
—
47
CLKOUT
O
Internal clock output (inverted output)
—
48
VSS
—
GND
—
49
B2OUT0
O
Blue data output (port 2)
—
50
B2OUT1
O
Blue data output (port 2)
—
51
B2OUT2
O
Blue data output (port 2)
—
52
B2OUT3
O
Blue data output (port 2)
—
53
B2OUT4
O
Blue data output (port 2)
—
54
VDD2
—
I/O power supply
—
55
VSS
—
GND
—
56
B2OUT5
O
Blue data output (port 2)
—
57
B2OUT6
O
Blue data output (port 2)
—
58
B2OUT7
O
Blue data output (port 2)
—
59
B2OUT8
O
Blue data output (port 2)
—
60
B2OUT9
O
Blue data output (port 2)
—
61
B1OUT0
O
Blue data output (port 1)
—
62
B1OUT1
O
Blue data output (port 1)
—
63
B1OUT2
O
Blue data output (port 1)
—
64
B1OUT3
O
Blue data output (port 1)
—
65
B1OUT4
O
Blue data output (port 1)
—
66
VDD2
—
I/O power supply
—
67
VSS
—
GND
—
68
B1OUT5
O
Blue data output (port 1)
—
69
B1OUT6
O
Blue data output (port 1)
—
70
B1OUT7
O
Blue data output (port 1)
—
71
B1OUT8
O
Blue data output (port 1)
—
72
B1OUT9
O
Blue data output (port 1)
—
73
G2OUT0
O
Green data output (port 2)
—
74
G2OUT1
O
Green data output (port 2)
—
I
–5–
CXD3511AQ
Pin
No.
Symbol
I/O
Description
Input pin
processing for
open status
75
G2OUT2
O
Green data output (port 2)
—
76
G2OUT3
O
Green data output (port 2)
—
77
VDD1
—
Internal operation power supply
—
78
VSS
—
GND
—
79
G2OUT4
O
Green data output (port 2)
—
80
G2OUT5
O
Green data output (port 2)
—
81
G2OUT6
O
Green data output (port 2)
—
82
G2OUT7
O
Green data output (port 2)
—
83
G2OUT8
O
Green data output (port 2)
—
84
VDD2
—
I/O power supply
—
85
G2OUT9
O
Green data output (port 2)
—
86
G1OUT0
O
Green data output (port 1)
—
87
G1OUT1
O
Green data output (port 1)
—
88
G1OUT2
O
Green data output (port 1)
—
89
VDD1
—
Internal operation power supply
—
90
VSS
—
GND
—
91
G1OUT3
O
Green data output (port 1)
—
92
G1OUT4
O
Green data output (port 1)
—
93
G1OUT5
O
Green data output (port 1)
—
94
G1OUT6
O
Green data output (port 1)
—
95
G1OUT7
O
Green data output (port 1)
—
96
G1OUT8
O
Green data output (port 1)
—
97
G1OUT9
O
Green data output (port 1)
—
98
R2OUT0
O
Red data output (port 2)
—
99
R2OUT1
O
Red data output (port 2)
—
100
VDD2
—
I/O power supply
—
101
VDD1
—
Internal operation power supply
—
102
VSS
—
GND
—
103
R2OUT2
O
Red data output (port 2)
—
104
R2OUT3
O
Red data output (port 2)
—
105
R2OUT4
O
Red data output (port 2)
—
106
R2OUT5
O
Red data output (port 2)
—
107
R2OUT6
O
Red data output (port 2)
—
108
R2OUT7
O
Red data output (port 2)
—
109
R2OUT8
O
Red data output (port 2)
—
110
R2OUT9
O
Red data output (port 2)
—
111
R1OUT0
O
Red data output (port 1)
—
–6–
CXD3511AQ
Pin
No.
Symbol
I/O
Description
Input pin
processing for
open status
112
R1OUT1
O
Red data output (port 1)
—
113
R1OUT2
O
Red data output (port 1)
—
114
VDD2
—
I/O power supply
—
115
VSS
—
GND
—
116
R1OUT3
O
Red data output (port 1)
—
117
R1OUT4
O
Red data output (port 1)
—
118
R1OUT5
O
Red data output (port 1)
—
119
R1OUT6
O
Red data output (port 1)
—
120
R1OUT7
O
Red data output (port 1)
—
121
R1OUT8
O
Red data output (port 1)
—
122
R1OUT9
O
Red data output (port 1)
—
123
VSTR
O
Vertical display start timing pulse output
—
124
VCKR
O
Vertical display transfer clock output
—
125
ENBR
O
Gate enable pulse output
—
126
VDD2
—
I/O power supply
—
127
VSS
—
GND
—
128
DCK2
O
DCK2 pulse output
—
129
DCK2X
O
DCK2X pulse output
—
130
VSS
—
GND
—
131
DCK1X
O
DCK1X pulse output
—
132
DCK1
O
DCK1 pulse output
—
133
VSS
—
GND
—
134
HCK1
O
Horizontal display transfer clock output 1
—
135
HCK2
O
Horizontal display transfer clock output 2
—
136
RGT
I/O
Horizontal scan direction switching signal I/O
—
137
XRGT
O
Horizontal scan direction switching signal output (reversed
polarity of RGT)
—
138
VDD2
—
I/O power supply
—
139
VSS
—
GND
—
140
HST
O
Horizontal display start timing pulse output
—
141
BLK
O
BLK pulse output
—
142
ENBL
O
Gate enable pulse output
—
143
VCKL
O
Vertical display transfer clock output
—
144
VDD2
—
I/O power supply
—
145
VDD1
—
Internal operation power supply
—
146
VSTL
O
Vertical display start timing pulse output
—
147
DWN
I/O
Vertical scan direction switching signal I/O
—
–7–
CXD3511AQ
Pin
No.
Symbol
I/O
Description
Input pin
processing for
open status
148
CTRL
I
Scan direction control method switching
(Low: internal register, High: external)
L
149
PCG
O
Collective precharge timing pulse output
—
150
VSS
—
GND
—
151
PST
O
Dot sequential precharge start timing pulse output
—
152
PO3
O
Parallel output 3
—
153
PO2
O
Parallel output 2
—
154
PO1
O
Parallel output 1
—
155
HD2
O
Horizontal auxiliary pulse output 2
—
156
VDD1
—
Internal operation power supply
—
157
FRP
O
AC drive inversion timing pulse output
—
158
XFRP
O
AC drive inversion timing pulse output (reversed polarity of FRP)
—
159
SHST
O
SHST pulse output
—
160
DENB
O
DENB pulse output
—
161
PRG
O
2-step precharge timing pulse output
—
162
VDD1
—
Internal operation power supply
—
163
VSS
—
GND
—
164
PO4
O
Parallel output 4
—
165
CLP
O
CLP pulse output
—
166
PO5
O
Parallel output 5
—
167
HD1
O
Horizontal auxiliary pulse output 1
—
168
TEST1
—
Test pin (Connect to GND.)
—
169
TEST2
—
Test pin (Connect to GND.)
—
170
TEST3
—
Test pin (Connect to VDD1.)
—
171
TEST4
—
Test pin (Connect to VDD1.)
—
172
TEST5
—
Test pin (Connect to VDD1.)
—
173
TEST6
—
Test pin (Connect to VDD1.)
—
174
VDD2
—
I/O power supply
—
175
VSS
—
GND
—
176
R1IN7
I
Red data input (port 1)
—
177
R1IN6
I
Red data input (port 1)
—
178
R1IN5
I
Red data input (port 1)
—
179
R1IN4
I
Red data input (port 1)
—
180
R1IN3
I
Red data input (port 1)
—
181
R1IN2
I
Red data input (port 1)
—
182
R1IN1
I
Red data input (port 1)
—
183
R1IN0
I
Red data input (port 1)
—
184
R2IN7
I
Red data input (port 2)
—
–8–
CXD3511AQ
Pin
No.
Symbol
185
R2IN6
186
VDD2
187
VSS
188
R2IN5
189
I/O
I
Description
Input pin
processing for
open status
Red data input (port 2)
—
—
I/O power supply
—
—
GND
—
I
Red data input (port 2)
—
R2IN4
I
Red data input (port 2)
—
190
R2IN3
I
Red data input (port 2)
—
191
R2IN2
I
Red data input (port 2)
—
192
R2IN1
I
Red data input (port 2)
—
193
R2IN0
I
Red data input (port 2)
—
194
G1IN7
I
Green data input (port 1)
—
195
G1IN6
I
Green data input (port 1)
—
196
G1IN5
I
Green data input (port 1)
—
197
VDD1
—
Internal operation power supply
—
198
VSS
—
GND
—
199
G1IN4
I
Green data input (port 1)
—
200
G1IN3
I
Green data input (port 1)
—
201
G1IN2
I
Green data input (port 1)
—
202
G1IN1
I
Green data input (port 1)
—
203
G1IN0
I
Green data input (port 1)
—
204
G2IN7
I
Green data input (port 2)
—
205
G2IN6
I
Green data input (port 2)
—
206
G2IN5
I
Green data input (port 2)
—
207
G2IN4
I
Green data input (port 2)
—
208
G2IN3
I
Green data input (port 2)
—
209
VDD1
—
Internal operation power supply
—
210
VSS
—
GND
—
211
G2IN2
I
Green data input (port 2)
—
212
G2IN1
I
Green data input (port 2)
—
213
G2IN0
I
Green data input (port 2)
—
214
B1IN7
I
Blue data input (port 1)
—
215
B1IN6
I
Blue data input (port 1)
—
216
B1IN5
I
Blue data input (port 1)
—
217
B1IN4
I
Blue data input (port 1)
—
218
B1IN3
I
Blue data input (port 1)
—
219
B1IN2
I
Blue data input (port 1)
—
220
B1IN1
I
Blue data input (port 1)
—
221
VDD1
Internal operation power supply
—
—
–9–
CXD3511AQ
Pin
No.
Symbol
222
VSS
223
B1IN0
224
I/O
—
Description
Input pin
processing for
open status
GND
—
I
Blue data input (port 1)
—
B2IN7
I
Blue data input (port 2)
—
225
B2IN6
I
Blue data input (port 2)
—
226
B2IN5
I
Blue data input (port 2)
—
227
B2IN4
I
Blue data input (port 2)
—
228
B2IN3
I
Blue data input (port 2)
—
229
B2IN2
I
Blue data input (port 2)
—
230
B2IN1
I
Blue data input (port 2)
—
231
B2IN0
I
Blue data input (port 2)
—
232
R1OSD1
I
OSD red data input (port 1)
—
233
R1OSD0
I
OSD red data input (port 1)
—
234
VDD2
—
I/O power supply
—
235
VSS
—
GND
—
236
G1OSD1
I
OSD green data input (port 1)
—
237
G1OSD0
I
OSD green data input (port 1)
—
238
B1OSD1
I
OSD blue data input (port 1)
—
239
B1OSD0
I
OSD blue data input (port 1)
—
240
YM1
I
OSD YM input (port 1)
L
∗ H: Pull-up, L: Pull-down
– 10 –
CXD3511AQ
Electrical Characteristics
DC Characteristics
Item
(Topr = –20 to +75°C, VSS = 0V)
Symbol
Applicable pins
Supply
voltage
VDD1
—
VDD2
—
Input
voltage 1
VIH1
Input
voltage 2
VIH2
Input
voltage 3
VIH3
Min.
Typ.
Max.
2.3
2.5
2.7
3.0
3.3
3.6
2.0
—
VDD2 + 0.3
–0.3
—
0.8
0.8VDD2
—
VDD2 + 0.3
–0.3
—
0.2VDD2
1.718
2.0
2.281
1.868
VC + 0.4
VDD2
VSS
VC – 0.4
2.131
—
VDD2 – 0.5
—
VDD2
—
VSS
—
0.2
CLKP = 200MHz
—
2600
3120
—
∗1
CMOS input cell
VIL1
VIL2
VC∗2
Conditions
HDIN, VDIN, PCTL,
CMOS Schmitt
PCLK, PDAT0 to PDAT9 trigger input cell
Small-amplitude
differential input
CLKP, CLKN
VIL3
Output
voltage
VOH
Current
consumption
PD∗3
VOL
All output pins
—
Unit
V
mW
∗1 Input pins other than those indicated in items Input voltage 2 and Input voltage 3.
∗2 VIH3 > VC (max.) and VIL3 < VC (min.).
∗3 Tj [°C] ≥ Toprmax [°C] + θja [°C/W] × PD [W].
(Tj = 125 [°C], Toprmax = 75 [°C], θja = 16 [°C/W], when mounted on a 4-layer substrate)
AC Characteristics
(Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item
Symbol
—
Clock input period
Applicable pins
Conditions
Min.
Typ.
Max.
CLKP, CLKN, CLKC
—
5
—
—
RGB input, OSD input,
HDIN, VDIN
—
2.5
—
—
—
1.5
—
—
Input setup time
tis
Input hold time
tih
Output rise/fall
delay time
tor/tof
∗4
CL = 20pF
2.0
4.0
8.0
Output rise/fall
delay time
tor/tof
CLKOUT
CL = 50pF
2.5
4.5
8.5
Cross-point time
difference
∆t
HCK1, HCK2, DCK1,
DCK1X, DCK2, DCK2X
CL = 20pF
–5.0
—
5.0
HCK1 duty
th/(th + tl)
tl/(th + tl)
HCK1
CL = 20pF
48
50
52
HCK2
CL = 20pF
48
50
52
PLLDIV = L
55
—
100
PLLDIV = H
27.5
—
55
HCK2 duty
Phase compensation
PLL operating
frequency
—
—
Unit
ns
%
MHz
∗4 Output pins other than CLKOUT, PO1 to PO5, RGT, XRGT and DWN.
– 11 –
CXD3511AQ
Power-on and Initialization of Internal Circuit
As for this IC, two systems of supply voltage should be turned on simultaneously. The initialization of the
internal circuit should be also performed by maintaining the system clear pin at low during the specified time
after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in
the figure below. Keep in mind that the internal circuit may not be initialized correctly if system clear
cancellation is performed before the supply voltage is set in the range of the recommended operating
conditions.
VDD1, VDD2
VDD1, VDD2
Vss
VDD2
XCLR1, XCLR2,
XCLR3
Vss
TR
TR > 200ns
– 12 –
CXD3511AQ
Timing Definition
VIH3, VDD2
VC, 50%
CLKP, CLKC
VIL3, VSS
VIH3
VC
CLKN
VIL3
VIH3, VDD2
CLKP, CLKC
VC, 50%
1/2 frequencydivided inputs
VIL3, VSS
VIH3
50%
CLKN
VIL3
VDD2
RGB input, OSD input,
HDIN, VDIN
VSS
tis
tih
VIH3, VDD2
CLKP, CLKC VC, 50%
VC, 50%
VIL3, VSS
VIH3
CLKN
VC
VC
VIL3
VIH3, VDD2
CLKP, CLKC VC, 50%
VC, 50%
1/2 frequencydivided inputs
VIL3, VSS
VIH3
CLKN
VC
VC
VIL3
VDD2
CLKOUT
50%
50%
VSS
tor
tof
VDD2
50%
Outputs other than CLKOUT
VSS
tor
VDD2
50%
Outputs other than CLKOUT
VSS
tof
VDD2
HCK1, DCK1, DCK2
50%
50%
VSS
VDD2
50%
50%
HCK2, DCK1X, DCK2X
VSS
∆t
∆t
VDD2
HCK1, HCK2
50%
50%
50%
VSS
th
tl
– 13 –
CXD3511AQ
Parallel I/F Block AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item
Symbol
tcs
tch
tds
tdh
tw
PCTL setup time with respect to rise of PCLK
PCTL hold time with respect to rise of PCLK
PDAT[9:0] setup time with respect to rise of PCLK
PDAT[9:0] hold time with respect to rise of PCLK
PCLK pulse width
Min.
8T∗5
Typ.
Max.
—
—
8T
—
—
4T
—
—
4T
—
—
4T
—
—
∗5 T: Master clock (CLKP, CLKN, CLKC) period [ns]
Timing Definition
tcs
tch
VDD2
PCTL
50%
50%
VSS
tw
tw
VDD2
PCLK
50%
50%
VSS
tds
tdh
VDD2
PDAT[9:0]
50%
50%
VSS
– 14 –
CXD3511AQ
Description of Operation
1. Description of Input Pins
(a) System clear pins (XCLR1, XCLR2 and XCLR3)
All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by
setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low.
Initialization should be performed when power is turned on. There are no particular restrictions on the
initialization order.
(b) Sync signal input pins (HDIN and VDIN)
Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The
CXD3511AQ supports only non-interlace sync signals with a dot clock of 200MHz or less.
(c) Master clock input pins (CLKP/CLKN and CLKC)
Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The
master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude
differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be
sure to make the number of dot clocks in 1H as even number.
Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate
properly.
(d) Clock selection pins (CLKSEL1 and CLKSEL2)
The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The
internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44).
Symbol
Setting
Function
L
H
CLKSEL1
Input clock selection
CLKP/CLKN input
CLKC input
CLKSEL2
Clock input pin selection
Dot clock input
1/2 frequency-divided clock input
(e) PLL setting pin (PLLDIV)
PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when
the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency
of the clock input to the CXD3511AQ must be within the phase compensation PLL operating range, even during
free running.
– 15 –
CXD3511AQ
(f) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN)
These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 176
to 183) and R2IN (Pins 184, 185 and 188 to 193), the Green signal to G1IN (Pins 194 to 196 and 199 to 203)
and G2IN (Pins 204 to 208 and 211 to 213), and the Blue signal to B1IN (Pins 214 to 220 and 223) and B2IN
(Pins 224 to 231).
(g) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2)
These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins
232 and 233) and R2OSD (Pins 2 and 3), the Green signal to G1OSD (Pins 236 and 237) and G2OSD (Pins
4 and 5), and the Blue signal to B1OSD (Pins 238 and 239) and B2OSD (Pins 8 and 9). In addition, the YM
signal is input to YM1 (Pin 240) and YM2 (Pin 10), and the YS signal to YS1 (Pin 1) and YS2 (Pin 11).
– 16 –
CXD3511AQ
2. RGB Signal and OSD Signal Pipeline Delay
The RGB signal I/O pipeline delay is 72 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 56
dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the
figures below. This relationship is the same for the OSD, YM and YS signals.
(1) CLKPOL = L
HDIN input (negative polarity)
Dot clock
1/2 frequency-divided clock
R1, G1, B1IN
N–2
N
N+2
N+4
N+6
N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
R2, G2, B2IN
N–1
N+1
N+3
N+5
N+7
N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
CLKOUT
R1, G1, B1OUT
N – 74 N – 72 N – 70 N – 68 N – 66 N – 64 N – 62 N – 60 N – 58 N – 56 N – 54
R2, G2, B2OUT
N – 73 N – 71 N – 69 N – 67 N – 65 N – 63 N – 61 N – 59 N – 57 N – 55 N – 53
(2) CLKPOL = H
HDIN input (negative polarity)
Dot clock
1/2 frequency-divided clock
R1, G1, B1IN
N–2
N
N+2
N+4
N+6
N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
R2, G2, B2IN
N–1
N+1
N+3
N+5
N+7
N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
CLKOUT
R1, G1, B1OUT
N – 74 N – 72 N – 70 N – 68 N – 66 N – 64 N – 62 N – 60 N – 58 N – 56 N – 54
R2, G2, B2OUT
N – 73 N – 71 N – 69 N – 67 N – 65 N – 63 N – 61 N – 59 N – 57 N – 55 N – 53
– 17 –
CXD3511AQ
3. Description of DSD Block Signal Processing Functions
The DSD block signal processing flow is shown below.
R, G, B IN
Data path
switch
Pre gain
Pre bright
User gain
User bright
Sub gain
YS, YM, R, G, B OSD
Sub bright
Selectable
delay line
Black
frame
Pattern
generator
Mute 1
Mute 2
Limiter
Gamma
correction
OSD
Post gain
Post bright
Color shading
correction
Ghost
cancel
Cycle
offset
R, G, B OUT
The various signal processing functions are described below. Note that the coefficients used for each
arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F
block item for a detailed description of the parallel I/F block.
(a) Data path switch block
This block can switch the path of the data input to ports 1 and 2. The setting is as follows.
Select signal: 1 = Path switched, 0 = Path not switched (Set independently for R, G and B)
Select signal (R, G, B_DAT_SW)
Input (port 1)
Input (port 2)
8
8
Selector
Selector
– 18 –
8
8
Output (port 1)
Output (port 2)
CXD3511AQ
(b) Pre gain block
This block performs calculation processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps
(Set independently for R, G and B ports 1 and 2)
Calculation is performed using the 8-bit input and an 8-bit coefficient, and the upper 10 bits c[15:6] of the
operation results are output. Next, the c[6] value is checked and rounding is performed to 9 bits. The MSB of
the rounded 9 bits is checked, clipping is performed, and the lower 8 bits are output.
Coefficient 8
b[7:0]
Input
a[7:0]
8
a×b
10
c[15:6]
Rounding
and
clipping
8
Output
(c) Pre bright block
This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as
follows.
Coefficient: 5 bits with code, MSB = code bit
Bright setting: –16 to +15 graduation, variable with an accuracy of 1 bit
(Set independently for R, G and B ports 1 and 2)
Calculation is performed using the 8-bit input and a 5-bit coefficient with code. The coefficient MSB is the code
bit. Addition is performed when b[4] = 0, and subtraction when b[4] = 1. However, when performing subtraction,
set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow,
clipping is performed.
Coefficient 5
b[4:0]
Input
a[7:0]
8
Addition/subtraction
and
clipping
8
Output
(d) User gain block
This block performs calculation processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 7.96875 (= 255/32) times, variable in 256 steps
(Settings shared by R, G and B)
Calculation is performed using the 8-bit input and an 8-bit coefficient, and the upper 12 bits c[15:4] of the
operation results are output. Next, the c[4] value is checked and rounding is performed to 11 bits. The MSB of
the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient 8
b[7:0]
Input
a[7:0]
8
a×b
12
c[15:4]
– 19 –
Rounding
and
clipping
10
Output
CXD3511AQ
(e) User bright block
This block performs addition and subtraction processing as the user control bright adjustment. The settings are
as follows.
Coefficient: 11 bits with code, MSB = code bit
Bright setting: –1024 to +1023 graduation, variable with an accuracy of 1 bit
(Settings shared by R, G and B)
Calculation is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Coefficient 11
b[10:0]
Addition/subtraction
and
clipping
Input 10
a[9:0]
10
Output
(f) Sub gain block
This block performs calculation processing as the white balance gain adjustment. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 3.984375 (255/64) times, variable in 256 steps
(Set independently for R, G and B)
Calculation is performed using the 10-bit input and an 8-bit coefficient, and the upper 13 bits c[17:5] of the
operation results are output. Next, the c[5] value is checked and rounding is performed to 12 bits. The upper 2
bits of the rounded 12 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient 8
b[7:0]
Input 10
a[9:0]
a×b
13
c[17:5]
Rounding
and
clipping
10
Output
(g) Sub bright block
This block performs addition and subtraction processing as the white balance bright adjustment. The settings
are as follows.
Coefficient: 11 bits with code, MSB = code bit
Bright setting: –1024 to +1023 graduation, variable with an accuracy of 1 bit
(Set independently for R, G and B)
Calculation is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Coefficient 11
b[10:0]
Input 10
a[9:0]
Addition/subtraction
and
clipping
– 20 –
10
Output
CXD3511AQ
(h) Black frame block
This block performs processing to fix the blanking period of the video signal to the desired level regardless of
the front-end signal processing results.
If the number of pixels calculated from the effective period of the video signal to be displayed is less than the
number of pixels of the LCD panel on which the signal is to be displayed, the blanking period of the video
signal is displayed in the excess pixels. At this time, the displayed blanking period can be fixed to the desired
level regardless of the gain and bright adjustment or other picture quality adjustment results by processing with
this block. The settings are as follows.
FRM_ON: 1 = Black frame processing ON, 0 = OFF
FRM_DAT: Black frame level setting
FRM_H1, FRM_H2: Set the black frame horizontal display range in 1-dot units
FRM_V1, FRM_V2: Set the black frame vertical display range in 1-line units
(All settings shared by R, G and B)
Here, the desired range of the video signal is replaced with 10-bit data (FRM_DAT) by switching the video
signal (port 1 and port 2) and the coefficients using the pulse output from the pulse decoder.
12
Internal HD
12
Internal VD
Pulse decoder
11
Internal MCLK
11
Horizontal display range (FRM_H1)
Horizontal display range (FRM_H2)
Vertical display range (FRM_V1)
Vertical display range (FRM_V2)
Processing ON/OFF
(FRM_ON)
Input (port 1)
Coefficient (FRM_DAT)
Input (port 2)
10
Selector
10
Output (port 1)
10
10
Selector
Output (port 2)
10
(i) Mute 1 block
This block performs mute processing by replacing the video signal with data of the desired level. The settings
are as follows.
MUTE1_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B)
R, G, B_MUTE1: RGB mute data (Set independently for R, G and B)
Select signal (MUTE1_ON)
Input
Coefficient
(R, G, B_MUTE1)
10
10
Selector
Output
10
– 21 –
CXD3511AQ
(j) Pattern generator block
This block generates and outputs the set fixed pattern independently of the input signal. This function is valid
when PG_ON = 1. When PG_R (G, B)_ON is "0", the signal level goes to 000h respectively for R, G and B.
The raster display pattern is displayed in the effective area, and all other display patterns are displayed in the
window area. Here, the effective area is set by PG_HST, PG_HSTP, PG_VST and PG_VSTP, and the window
area is set by PG_HWST, PG_HWSTP, PG_VWST and PG_VWSTP.
The display pattern signal level is set independently for R, G and B by PG_SIG1R (G, B)[9:0] and PG_SIG2R
(G, B)[9:0]. Within the effective area, the pattern and non-pattern signal levels can be switched by PG_R (G,
B)_SEL. At this time, the signal level outside the effective area goes to 000h. During horizontal ramp, horizontal
stair, vertical ramp and vertical stair display, the PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are
invalid.
The display patterns and signal levels are as follows.
(1) Raster display
When PG_PAT[2:0] = 0h, a raster is displayed.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
0h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
0h
PG_STRP_SW
x
PG_STAIR_SW
x
x: Don't care
– 22 –
CXD3511AQ
(2) Window display
When PG_PAT[2:0] = 1h, a window is displayed.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
1h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
1h
PG_STRP_SW
x
PG_STAIR_SW
x
x: Don't care
– 23 –
CXD3511AQ
(3) Vertical stripe display
When PG_PAT[2:0] = 2h and PG_STRP_SW = 0, vertical stripes are displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
2h
PG_STRP_SW
0
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
2h
PG_STRP_SW
0
PG_STAIR_SW
x
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
x: Don't care
– 24 –
CXD3511AQ
(4) Diagonal stripes
When PG_PAT[2:0] = 2h and PG_STRP_SW = 1, diagonal stripes are displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_R (G, B)_SEL
0
PG_PAT[2:0]
2h
PG_STRP_SW
1
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
2h
PG_STRP_SW
1
PG_STAIR_SW
x
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
x: Don't care
– 25 –
CXD3511AQ
(5) Horizontal stripes
When PG_PAT[2:0] = 3h, horizontal stripes are displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
3h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
3h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
x: Don't care
– 26 –
CXD3511AQ
(6) Cross hatch
When PG_PAT[2:0] = 4h, a cross hatch is displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
4h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
4h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
x: Don't care
– 27 –
CXD3511AQ
(7) Dots
When PG_PAT[2:0] = 5h, a dot pattern is displayed.
The dot period is set by PG_STEP in 2-dot units. The dot width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
5h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_R (G, B)_SEL
1
PG_PAT[2:0]
5h
PG_STRP_SW
x
PG_STAIR_SW
x
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
x: Don't care
– 28 –
CXD3511AQ
(8) Horizontal ramp
When PG_PAT[2:0] = 6h and PG_STAIR_SW = 0, a horizontal ramp is displayed.
The signal level is incremented from 000h by one bit for each dot.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
6h
PG_STRP_SW
x
PG_STAIR_SW
0
PG_R (G, B)_SEL
1
PG_PAT[2:0]
6h
PG_STRP_SW
x
PG_STAIR_SW
0
x: Don't care
– 29 –
CXD3511AQ
(9) Horizontal stair
When PG_PAT[2:0] = 6h and PG_STAIR_SW = 1, a horizontal stair is displayed.
The signal level is incremented from 000h by 64 bits for each 64 dots.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
6h
PG_STRP_SW
x
PG_STAIR_SW
1
PG_R (G, B)_SEL
1
PG_PAT[2:0]
6h
PG_STRP_SW
x
PG_STAIR_SW
1
x: Don't care
– 30 –
CXD3511AQ
(10) Vertical ramp
When PG_PAT[2:0] = 7h and PG_STAIR_SW = 0, a vertical ramp is displayed.
The signal level is incremented from 000h by one bit for each line.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
7h
PG_STRP_SW
x
PG_STAIR_SW
0
PG_R (G, B)_SEL
1
PG_PAT[2:0]
7h
PG_STRP_SW
x
PG_STAIR_SW
0
x: Don't care
– 31 –
CXD3511AQ
(11) Vertical stair
When PG_PAT[2:0] = 7h and PG_STAIR_SW = 1, a vertical stair is displayed.
The signal level is incremented from 000h by 64 bits for each 32 lines.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
0
PG_PAT[2:0]
7h
PG_STRP_SW
x
PG_STAIR_SW
1
PG_R (G, B)_SEL
1
PG_PAT[2:0]
7h
PG_STRP_SW
x
PG_STAIR_SW
1
x: Don't care
– 32 –
CXD3511AQ
(k) OSD block
This block performs video signal half-tone processing and OSD-MIX processing by inputting the 2-bit OSD
signal for each color and the YS and YM signals. The half-tone processing setting is as follows.
YM signal input: 1 = Half-tone processing ON, 0 = OFF
Here, the video signal level is halved by shifting the input data by one bit to the LSB side when YM = 1. For
example, when 0F0h is input, 078h is output.
The selector selects one of four types of data with respect to the OSD signal value as shown in the table below.
The selected data becomes the OSD signal gradual data. The selected gradual data can be set independently
in 10 bits for R, G and B, so 4 graduation can be selected as desired from among 1024 graduation for each of
R, G and B. Therefore, the desired 64 (= 2^6) colors can be selected from among the total 1.07374 billion (= 2^30)
colors for R, G and B.
OSD signal input
Selected gradual data
0h
R, G, B_OSD_DAT1
1h
R, G, B_OSD_DAT2
2h
R, G, B_OSD_DAT3
3h
R, G, B_OSD_DAT4
The OSD-MIX processing setting is as follows.
YS signal input: 1 = OSD-MIX processing ON, 0 = OFF
OSD signal
Gradual data (R, G, B_OSD_DAT1)
Gradual data (R, G, B_OSD_DAT2)
Gradual data (R, G, B_OSD_DAT3)
Gradual data (R, G, B_OSD_DAT4)
2
10
10
10
10
Selector
10
YS signal
YM signal
Input
10
Half-tone processing
– 33 –
10
OSD-MIX
10
Output
CXD3511AQ
(l) Gamma block
This block performs gamma correction for the user- and white balance-adjusted signal. Gamma correction
uses the LUT system, and the RAM size is 10 bits × 1024 words. The settings are as follows.
GAM_ON: 1 = Normal operation, 0 = Standby mode
GAM_SEL: 1 = Path passing through the RAM, 0 = Path not passing through the RAM
(All settings shared by R, G and B)
When operating the RAM, be sure to set GAM_ON = 1. Data cannot be written to or read from the RAM in
standby mode. The RAM data is set through the parallel I/F block.
Note that the RAM output is undetermined while data is being set in this RAM, and also during power-on.
RAM ON/OFF
(GAM_ON)
Select signal
(GAM_SEL)
Input
10
RAM
10 bits × 1024 words
10
– 34 –
Selector
10
Output
CXD3511AQ
(m) Color shading correction
This block corrects color shading by adding a correction signal to the video signal. Correction points are set at
fixed intervals in the horizontal, vertical and gradual directions of the video signal. The correction data for these
correction points is written in the RAM, and a correction curve is created by reading this data and performing
interpolation operations. The settings are as follows.
CSC_ON: 1 = Color shading correction processing ON, 0 = Processing OFF
CSC_R (G, B)_RGT∗: 1 = Reflects the TG block RGT setting,
0 = Reflects the inverse of the TG block RGT setting
CSC_DWN: 1 = Reflects the TG block DWN setting,
0 = Reflects the inverse of the TG block DWN setting
CSC_HP: Sets the horizontal correction start position
CSC_VP: Sets the vertical correction start position
CSC_HNUM: Sets the number of horizontal correction points
CSC_VNUM: Sets the number of vertical correction points
CSC_HINT: Sets the horizontal correction interval
CSC_VINT: Sets the vertical correction interval
CSC_HOS: Sets the expansion of the horizontal correction area
CSC_VOS: Sets the expansion of the vertical correction area
CSC_GNUM: Sets the gradual correction points
CSC_R (G, B) GP1 to 8∗: Sets the gradual correction points
CSC_R (G, B) GD1 to 8∗: Sets the expansion of the correction data
CSC_XH_ON: 1 = Cross hatch insertion ON, 0 = OFF
CSC_XH_DAT: Sets the cross hatch display level
∗: Set independently for R, G and B, Others: Settings shared by R, G and B
The color shading correction data of the desired gradual level up to 8 screens (max.) can be set in RAM. The
RAM size is 8 bits × 4096 words, so up to 4096 correction points can be set. The correction data is set as 8-bit
data with code. Correction data can be set in the range of –128 to +127 graduation. The example shown on
page 37 is for a 1024-dot × 768-line XGA video signal divided into 9 points at 128-dot intervals in the horizontal
direction and 7 points at 128-line intervals in the vertical direction. The relationship between the correction
point coordinates (m, n) and the RAM address is obtained as follows.
RAM address = (m – 1) + (n – 1) × (Number of horizontal correction points)
For the example in the figure below, this is as follows.
(9 – 1) + (7 – 1) × 9 = 62
Thus, the correction data must be set in the RAM from address 0 to address 62.
– 35 –
CXD3511AQ
If correction is to be performed in the gradual direction as well, the RAM address is found based on the relationship
between the coordinates (m, n) of the correction points and the number of gradual correction points using the
formula below:
RAM address = (m – 1) + (n – 1) × (number of horizontal correction points)
+ (number of horizontal correction points) × (number of vertical correction points)
× (number of gradual correction points – 1)
If the number of gradual correction points is eight, it is necessary to set correction data into RAM from Address
0 to Address 503 as calculated below:
(9 – 1) + (7 – 1) × 9 + 9 × 7 × 7 = 503
Correction data in the gradual direction for the screen 2 and subsequent planes is set in order from Address 63.
This IC supports up/down and/or right/left inversion of the LCD panel by controlling the direction in which
correction data that has been set into RAM is read. Up/down and/or right/left inversion are set from DWN and
RGT of the TG block.
CSC_DWN and CSC_R (G, B)_RGT control the link with the TG block settings. It is therefore unnecessary to
reset correction data. The table below gives an example of setting correction points.
Correction gap
Signal specification
UXGA (1600 × 1200)
SXGA (1280 × 1024)
SXGA+ (1400 × 1050)
Full-HD (1920 × 1080)
XGA (1024 × 768)
Number of correction points
H
V
H
V
G
Total
64
64
25
19
8
3800
80
80
21
16
8
2688
64
64
21
17
8
2856
64
64
20
16
8
2560
64
64
23
18
8
3312
80
80
19
15
8
2280
64
64
30
17
8
4080
80
80
25
15
8
3000
64
64
17
13
8
1768
64
64
16
12
8
1536
Example of Setting Correction Points
– 36 –
CXD3511AQ
This IC has two ways it can handle interpolation in the horizontal and vertical directions: by dividing the screen
into a uniform grid and setting data for points at the intersections or by setting data for points in the center of
each area.
(1) When setting data for intersection points (pixels) on the screen
The correction area is set for the entire screen. An interpolation operation uses 4 values nearby intermediate
points to perform calculations. The correction start position is set using CSC_HP and CSC_VP. Be sure to set
the start position for the effective period of the video signal.
HDIN
VDIN
Correction start position
1
2
3
4
5
6
Number of correction points
7
8
9
Correction start position
1
(m, n)
Number of correction points
4
5
6
7
Correction interval (128 dots)
768 lines
3
Correction interval (128 lines)
2
: Correction data that has been set in RAM
: Interpolation operation results for the vertical
direction
: Interpolation operation results for the horizontal
direction
1024 dots
(2) When setting the correction point to the center of the areas dividing the screen
The correction area is set to inside the screen. At this time, be sure to set the correction start position so it lies
inside the screen. When the correction point is set to the center of the areas dividing the screen, it is
necessary to virtually perform correction outside the correction area for which correction data is set. It is
therefore assumed that the same data as at the edge of the correction area applies to outside the interpolation
area, and linear interpolation is performed.
Use CSC_HOS and CSC_VOS to set correction areas that are to be expanded.
HDIN
Correction start position
VDIN
Correction start position
: Correction data that has been set in RAM
: Data assumed to lie in invalid period
: Area to be virtually corrected
– 37 –
CXD3511AQ
The number of correction points to be used by this IC for correction in the gradual direction can be set using
CSC_GNUM. The number of correction points can be varied from 1 to 8 and settings are available for each
RGB signal. This means that the gradual level for which correction is to be performed can be independently
and freely set for each RGB signal using CSC_R (G, B) GP1 to 8. An interpolation operation uses 2 values
nearby intermediate points to perform linear interpolation.
If the number of correction points is 1, no interpolation operation is performed in the gradual direction. The
results of interpolation for one screen are added to the video signal regardless of the gradual level of the video
signal being input. Correction data for one screen is entered into RAM beginning from Address 0.
When two or more correction points are used, interpolation in the gradual direction is performed according to the
gradual level of the video signal being input. At this time, set data into RAM for the number of screens equal to
"the number of correction points", beginning from Address 0. In the example shown in the figure below, correction
data is assigned when there are 5 correction points. In addition to the 5 correction points, data for Screen 1
(Correction Point 1) is assigned to 3FFh. Data for the Screen 5 (Correction Point 5) is assigned to 000h.
Data for Screen 1
(Correction Point 1)
3FFh
Screen 1 (Correction Point 1)
300h
Screen 2 (Correction Point 2)
Screen 3 (Correction Point 3)
200h
Screen 4 (Correction Point 4)
Screen 5 (Correction Point 5)
100h
Data for Screen 5
(Correction Point 5)
000h
: Correction data that has been set in RAM
: Interpolation operation results for the gradual direction
Example of Settings for Five Correction Points
Furthermore, with this IC, correction data can be extended from 8 bits with code to 9 bits with code. This
setting is made using CSC_R (G, B) GD1 to 8. This setting can be made separately for each correction point in
the gradual direction as well as independently for each RGB signal.
– 38 –
CXD3511AQ
(n) Selectable delay line block
This block supports signal shifting in 1-dot units, performs signal port switching linked with right/left inversion
and signal processing that supports dot/line inversion.
This block is comprised of five selectors: dot shift selector, right/left inversion selector, dot/line selector, up/
down inversion pre-selector, and up/down inversion post-selector.
The delay line size is 1200 words.
The data paths for this block are shown in the figure below. Port switching during right/left inversion depends
on the Cond1 value, and port switching during up/down inversion (when dot/line inversion support is ON)
depends on the Cond2 value.
Cond1 = (RGT_SEL_ON) NAND [(RGT) Ex-OR (DLY_R (G, B)_RGT)]
Cond2 = (DWN) Ex-NOR (DLY_DWN)
Note) RGT and DWN are TG block settings.
Input port 1
Output port 1
Delay line
Dot shift
selector
Right/left
inversion
selector
Dot/line
selector
Up/down
inversion
pre-selector
Up/down
inversion
post-selector
HP[0]
Cond1
DLY_ON
Cond2
Cond2
Output port 2
Input port 2
Solid lines: 1
Dotted lines: 0
– 39 –
CXD3511AQ
(1) 1-dot shift
When HP[0] = 0, the output data is delayed by one dot compared to when HP[0] = 1.
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15
port2 out
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16
(2) Right/left inversion
When Cond1 = 0, signal port switching is performed for the output data.
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17
IN2
port2 out
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16
IN1
– 40 –
CXD3511AQ
(3) Dot/line inversion support
When DLY_ON = 1, signal processing that supports dot/line inverted drive is performed. The output data is
output as shown in the figures below according to the Cond1 and Cond2 values. D and the dotted lines in the
figures indicate that the signal is delayed by 1H.
Cond1
Cond2
1
1
Cond1
Cond2
0
1
Cond1
Cond2
1
0
Cond1
Cond2
0
0
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16
D1
port2 out
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17
IN2
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17
D2
port2 out
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16
IN1
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16
IN1
port2 out
0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17
D2
clk
port1 in
1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18
port2 in
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19
port1 out
1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17
IN2
port2 out
0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16
D1
– 41 –
CXD3511AQ
(o) Mute 2 block
This block performs mute processing by replacing the video signal with data of the desired level. The settings
are as follows.
MUTE2_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B)
R, G, B_MUTE2: RGB mute data (Set independently for R, G and B)
Select data (MUTE2_ON)
Input
Coefficient
10
Selector
10
Output
10
(R, G, B_MUTE2)
(p) Limiter block
This block performs limiter processing so that the output signal does not exceed a certain range. The settings
are as follows.
L_LIM_DAT: Low side limiter level
When input data ≤ L_LIM_DAT, the output is clipped to L_LIM_DAT.
H_LIM_DAT: High side limiter level
When H_LIM_DAT ≤ input data, the output is clipped to H_LIM_DAT.
(Both settings shared by R, G and B)
Set data so that the relationship L_LIM_DAT < H_LIM_DAT is constantly maintained. When both coefficient
values are 000h, limiter processing is not performed.
Input
Coefficient (H_LIM_DAT)
Coefficient (L_LIM_DAT)
10
10
Limiter
10
Output
10
(q) Post gain block
This block performs calculation processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps
(Set independently for R, G and B ports 1 and 2)
Calculation is performed using the 10-bit input and an 8-bit coefficient, and the upper 12 bits c[17:6] of the
operation results are output. Next, the c[6] value is checked and rounding is performed to 11 bits. The MSB of
the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient 8
b[7:0]
Input 10
a[9:0]
a×b
12
c[17:6]
Rounding
and
clipping
– 42 –
10
Output
CXD3511AQ
(r) Post bright block
This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as
follows.
Coefficient: 7 bits with code, MSB = code bit
Bright setting: –64 to +63 graduation, variable with an accuracy of 1 bit
(Set independently for R, G and B ports 1 and 2)
Calculation is performed using the 10-bit input and a 7-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[6] = 0, and subtraction when b[6] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Coefficient 7
b[6:0]
Input 10
a[9:0]
Addition/subtraction
and
clipping
10
Output
(s) Ghost cancel
This block uses signal processing to correct ghosting generated internally within the LCD panel.
GC_ON: 1 = Ghost cancel processing ON; 0 = OFF (Settings shared by R, G and B)
GC_MODE: 1 = 24-dot period processing ON; 0 = 12-dot period processing (Settings shared by R, G and B)
R (G, B)_GC_LIM_DAT: Threshould value setting (set independently for R, G and B)
R (G, B)_GC_ATT: 8-bit gain data (Set independently for R, G and B)
The difference between the video signal prior to 12 or 24 dots and the video signal of dots for which processing
is to be performed is found. Attenuation is performed based on this difference and added to the video signal to
correct ghosting. In addition, settings can be made so that a limiter is used to ensure processing is performed
only when the difference in the video signals is of a set level or higher.
Level selection
Input
10
Shift
Register
Processing
Coefficient
Coefficient ON/OFF
Arithmetic
unit
Limiter
Attenuator
12 levels or 24 levels
+
– 43 –
–
Clip
processing
Output
CXD3511AQ
(t) Cycle offset block
This block performs addition and subtraction processing independently for ports 1 and 2. Arithmetic
coefficients are selected sequentially using the counter output value as the select signal. Therefore, a cyclic
offset relative to the video signal can be attached. The settings are as follows.
OFFSET_ON: 1 = Offset processing ON, 0 = OFF (Setting shared by R, G and B)
OFFSET_MODE: 0h = 6-dot period, 1h = 12-dot period, 2h = 24-dot period (Setting shared by R, G
and B)
R, G, B_OFFSET1 to R, G, B_OFFSET24: 5-bit offset data with code
–16 to +15 graduation, variable with an accuracy of 1 bit
(Set independently for R, G and B)
The coefficients selected according to the counter operating period are as shown in the table below. In all
cases, the coefficients are assigned in ascending order from the smallest number. The coefficient MSB is the
code bit. Addition is performed when MSB = 0, and subtraction when MSB = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Coefficient number output from selector
Period
Port 1 side
Port 2 side
6 dots
1, 3, 5
2, 4, 6
12 dots
1, 3, 5, 7, 9, 11
2, 4, 6, 8, 10, 12
24 dots
1, 3, 5, 7, 9, 11, 13,
15, 17, 19, 21, 23
1, 4, 6, 8, 10, 12, 14,
16, 18, 20, 22, 24
The counter reset timing is delayed by 8 dot clocks from the front edge of the HDIN input.
HDIN input (negative polarity)
Dot clock
1/2 frequency-divided clock
R1, G1, B1OUT
1
3
5
7
9
11
R2, G2, B2OUT
2
4
6
8
10
12
8 clocks
Internal HD
Counter
Internal MCLK
OFFSET_MODE
4
Selector
5 × 24
2
Coefficient (R, G, B_OFFSET1 to R, G, B_OFFSET24)
5
5
OFFSET_ON
Input (port 1)
Input (port 2)
10
Addition/subtraction
and
clipping
10
10
Addition/subtraction
and
clipping
10
– 44 –
Output (port 1)
Output (port 2)
CXD3511AQ
4. Timing Generator (TG) Block
This block generates the timing pulses required to drive Sony LCD panels. Of the output pulses, the required
pulses differ according to the LCD panel type, so be sure to also check the specifications of the panel used.
The output timing pulses are all set by the parallel I/F. For a detailed description, see the description of the
parallel I/F TG block.
The TG block diagram is shown below.
HDIN
HSYNC Detect
PLL Counter
HP Counter
HRS
H Pulse 1
Generator
H Pulse 2
Generator
INT_VD
VDIN
VSYNC Detect
HST, PST, HCK1, HCK2,
DCK1, DCK1X, DCK2,
DCK2X, ENBR, ENBL,
DENB, PCG, PRG,
SHST, HD2
CLP, HD1
INT_HD
VP Counter
V Pulse Generator
VSTR, VSTL, VCKR,
VCKL, FRP, XFRP,
BLK
CTRL
Parallel I/F
Control Register
RGT, DWN
XRGT, PO1, 2, 3, 4, 5
Timing Generator Block Diagram
– 45 –
CXD3511AQ
5. Parallel I/F Block
Register data settings in this IC are performed by parallel data. As shown in the Timing Chart below, the parallel
I/F comprises a total 12-bit wide bus consisting of control signal PCTL (Pin 12), clock signal PCLK (Pin 13) and
10-bit wide data signal PDAT[9:0] (Pins 14 to 17, 20 to 24 and 26).
The data signal is input in the order of main address, sub address and data. When setting data in this IC,
divide the data into 19 blocks as shown in the table on the next page. Next, the sub address specifies the initial
address of the data to be written in the block designated by the main address. The data is set sequentially from
the data at the address designated by the sub address. The address of each data set thereafter is
automatically incremented by +1 from the address designated by the sub address, so further address setting
is unnecessary. This makes it possible to set only the necessary data from the desired address of the desired
block.
(1) Timing chart
PCTL (Pin 12)
PCTL (Pin 13)
PDAT[9:0]
(Pins 14 to 17, 20 to 24 and 26)
Main
Sub
Address Address
– 46 –
Data
CXD3511AQ
(2) Main address table
This IC has the RAM size of color shading correction block is 4096 words. One address is divided into four
main addresses and mapped.
Main address
Set block
000h
TG
001h
DSD1
002h
DSD2
003h
Red Gamma
004h
Green Gamma
005h
Blue Gamma
006h
Red CSC (000h to 3FFh)
007h
Red CSC (400h to 7FFh)
008h
Red CSC (800h to BFFh)
009h
Red CSC (C00h to FFFh)
00Ah
Green CSC (000h to 3FFh)
00Bh
Green CSC (400h to 7FFh)
00Ch
Green CSC (800h to BFFh)
00Dh
Green CSC (C00h to FFFh)
00Eh
Blue CSC (000h to 3FFh)
00Fh
Blue CSC (400h to 7FFh)
010h
Blue CSC (800h to BFFh)
011h
Blue CSC (C00h to FFFh)
012h
Pattern Generator
– 47 –
– 48 –
—
—
017h
—
—
DEND[10:1]
013h
—
DENU[10:1]
012h
—
SHSTD[10:1]
011h
016h
SHSTU[10:1]
010h
—
FRPP[10:1]
00Fh
—
HD1D[10:1]
00Eh
015h
HD1U[10:1]
00Dh
—
PRGD[10:1]
00Ch
—
PRGU[10:1]
00Bh
—
CLPD[10:1]
00Ah
014h
CLPU[10:1]
009h
—
—
VP[9:0]
—
008h
—
HP[9:0]
—
007h
006h
PLLP[10:1]
005h
—
—
HCKFIX
HCKPOL
PO5
PDAT4
VFRRN[10:2]
Data
004h
—
—
—
—
003h
—
HSTFIX
DCKFIX
DCKFINV
—
HSTPOL
DCKPOL
VPOL
HPOL
—
001h
FRPM[1:0]
DWN
RGT
HR
CLKPOL
POLDET
000h
002h
PDAT5
PDAT6
PDAT7
PDAT8
PDAT9
Sub address
The TG block data format is as follows.
5-1. TG Block (Main Address: 000h)
—
—
PO3
PDAT2
PSTPC[7:0]
HSTPF[5:0]
HSTPC[7:0]
—
RGVLNK
VCKFIX
VCKPOL
SHP[5:0]
VSTFIX
VSTPOL
PO4
PDAT3
3FFh
PLLP[11]
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
3FFh
PSTM
SLXBLK
1FFh
000h
Initial value
BLKON
PO1
PDAT0
HP[11:10]
FRVC1LNK
HSTM
BLKPOL
PO2
PDAT1
CXD3511AQ
– 49 –
PSTOE
HCK1OE
HCK2OE
BLKD[10:1]
02Bh
HSTOE
BLKU[10:1]
02Ah
02Dh
HD2D[10:1]
029h
DCKOE
DCKXOE
PRGOE
HD2U[10:1]
028h
CLPOE
VST2P[11:2]
027h
HD2OE
VST1P[11:2]
026h
HD1OE
VCK2P[10:1]
025h
CLKOUT
VCK1P[10:1]
024h
—
ENB2D[10:1]
023h
02Ch
ENB2U[10:1]
022h
—
ENB1D[10:1]
—
—
021h
—
—
01Dh
—
—
ENB1U[10:1]
—
—
01Ch
—
—
020h
—
—
01Bh
—
—
PDAT4
PDGD[10:1]
—
—
01Ah
—
—
PDAT5
01Fh
—
—
019h
—
PDAT6
PCGU[10:1]
—
—
018h
PDAT7
Data
01Eh
PDAT8
PDAT9
Sub address
PDAT2
V1OE
SHSTOE
V2OE
DENOE
DCK2W[5:0]
DCK2F[5:0]
DCK1W[5:0]
DCK1F[5:0]
HCKC[5:0]
PSTPF[5:0]
PDAT3
PCGOE
FRPOE
PDAT1
BLKOE
XFRPOE
PDAT0
—: Don't care
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
Initial value
CXD3511AQ
CXD3511AQ
The detailed setting contents are described below.
(a) Clock settings
(1) CLKPOL (sub address: 000h)
This sets the internal clock polarity.
Setting value: 1 = Inverted, 0 = Not inverted
The clock flow from the clock input pins to the PLL block is shown below.
CLKP
1/2
CLKN
To PLL Block
CLKC
CLKSEL1
CLKSEL2
CLKPOL
(2) CLKOUT (sub address: 02Ch)
This sets the Pin 47 clock output limit.
Setting value: 1 = Inverted clock is output, 0 = Low is output
(b) SYNC polarity settings
(1) POLDET (sub address: 000h)
This sets the sync polarity auto discrimination function ON/OFF.
Setting value: 1 = Auto discrimination function ON, 0 = Auto discrimination function OFF
When POLDET = 1, the HPOL and VPOL settings below are invalid. When using this function, the HDIN sync
portion must be 1/2 or less of 1H, and the VDIN sync portion must come before the rise position of the VSTL/
R pulse.
HDIN (Negative)
N/2 or less
N
VDIN (Negative)
Must come before VSTL/R
VSTL/R
(2) HPOL and VPOL (sub address: 001h)
These set the sync signal polarity when POLDET = 0.
Setting value: 1 = Positive polarity, 0 = Negative polarity
The internal operation of this IC is with the input sync signal fixed to positive polarity. Therefore, these HPOL
and VPOL must be set in accordance with the polarity of the sync signal input from HDIN and VDIN.
Set HPOL and VPOL to "1" when the input sync signal is positive polarity, or to "0" when negative polarity.
– 50 –
CXD3511AQ
(c) Dots per 1H and lines per 1F settings
(1) HR (sub address: 000h)
This sets the PLL counter reset ON/OFF.
Setting value: 1 = Reset enabled, 0 = Reset disabled
When HR = 0, the internal frequency divider is used, and the HD1 pulse output should be used as the return
pulse. The number of dot clocks per 1H is set by PLLP[11:1] below.
(2) PLLP[11:1] (sub addresses: 004h and 005h)
This sets the internal PLL counter reset period in 11 bits. Setting is possible in 2-dot units. When the number of
dot clocks per 1H is N, set the "(N – 2)/2" value.
When HR = 0, free-running occurs at the above N. When HR = 1, if the next HDIN is not input before the
internal PLL counter counts up to 2047, free-running mode is established and free-running occurs at N.
When HDIN is input, free-running is canceled and normal operation is established.
(3) VFRRN[10:2] (sub address: 004h)
This sets the number of lines in 9 bits during vertical free running. Setting is possible in 4-line units. To have
operation run freely at M lines, set the "(M – 4)/4" value. If the next VDIN is not input before the internal vertical
line counter counts up to 2047, free-running mode is established. When VDIN is input, free-running is canceled
and normal operation is established.
(d) Scan direction settings
RGT and DWN (sub address: 000h)
These settings switch the scan directions of the LCD panel.
Setting value: 1 = Forward scan, 0 = Reverse scan
When CTRL (Pin 148) is low, RGT (Pin 136) and DWN (Pin 147) function as output pins, and the data set in
the respective registers is reflected. When CTRL is high, this setting is ignored, RGT and DWN function as
input pins, and are reflected to internal operation.
(e) Register parallel output settings
PO1, PO2, PO3, PO4 and PO5 (sub address: 000h)
These set the register setting parallel output.
Setting value: 1 = High is output, 0 = Low is output
The set data is reflected to the output pins PO1 (Pin 154), PO2 (Pin 153), PO3 (Pin 152), PO4 (Pin 164) and
PO5 (Pin 166) of the same name.
– 51 –
CXD3511AQ
(f) Horizontal display position and horizontal direction pulse settings
(1) HP[11:0] (sub addresses: 006h and 007h)
HP[11:1] sets the horizontal pulse position for the LCD panel in 11 bits. The position can be set in 2-dot units
using the internal pulse INT_HD generated from the front edge of HDIN as the reference. The HP setting range
is from "0 to (N – 2)".
If the HP value is set to the number of frequency divisions N or higher, the HP setting is ignored and "(N – 2)"
is used as the setting value.
The HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X, ENBL, ENBR, VSTL, VSTR, VCKL, VCKR, FRP,
XFRP, PCG, PRG, BLK and HD2 horizontal timing pulses are linked according to the HP setting.
The internal reference pulse INT_HD rises at the 5th clock from the front edge of the HDIN input, and all the
pulses are synchronized using this as the reference. Increasing HP shifts the output positions of the linked
pulses toward the rear of the time series. The example below shows the shortest output position from HDIN
when HP is set to 000h. (Note that the output position changes according to the settings in (2) below.)
HP[0] can shift the video in 1-dot units. See 3. Description of DSD Block Signal Processing Functions, (n)
Selectable delay line block, (1) 1-dot shift for a detailed description.
Internal CLK
HDIN
INT_HD
HD1
HD2
(2) CLPU[10:1], CLPD[10:1], PRGU[10:1], PRGD[10:1], HD1U[10:1], HD1D[10:1], SHSTU[10:1],
SHSTD[10:1], DENU[10:1], DEND[10:1], PCGU[10:1], PCGD[10:1], ENB1U[10:1], ENB1D[10:1],
ENB2U[10:1], ENB2D[10:1], HD2U[10:1], HD2D[10:1]
(sub addresses: 009h to 013h, 01Eh to 023h and 028h to 029h)
These set the horizontal timing pulse output positions in 10 bits. The respective rise and fall positions can be
set in 2-dot units. Settings ending in "U" set the rise position, and settings ending in "D" set the fall position.
Horizontal pulses are divided into the following two types.
(A) CLP and HD1 → Pulses synchronized to the PLL counter
Set the "(rise position/fall position – 10)/2" value.
(B) PRG, SHST, DEN, PCG, ENBL, ENBR and HD2 → Pulses synchronized to the HP counter
Set the "(rise position/fall position – HP setting value – 16)/2" value.
An outline of each type is shown below. When ∗∗U and ∗∗D are set to the same value, "1" is output.
HDIN
0
0
PLL counter
0
0
HP counter
HP[11:1]
(A)
(B)
∗∗U
∗∗D
∗∗U
∗∗D
(3) HD1OE, HD2OE, CLPOE, PRGOE, SHSTOE, DENOE and PCGOE (sub addresses: 02Ch and 02Dh)
These set the output limit of HD1, HD2, CLP, PRG, SHST, DEN and PCG pulses, respectively.
Setting value: 1 = Pulse is output, 0 = Output is fixed to "0"
– 52 –
CXD3511AQ
(g) Vertical display position setting
VP[9:0] (sub address: 008h)
This sets the vertical display start position in 10 bits. The position can be set in 1-line units using the front edge
of VDIN as the reference. The VSTL/VSTR, VCKL/VCKR, FRP and XFRP pulse phases change by linking with
this setting.
Minimum
adjustment
width: 1H
Tvp
VDIN
HDIN
VSTL
VCKL
Tvp minimum and maximum setting values
Min.
Max.
VP[9:0]
000h
3FFh
Tvp
6H
1029H
– 53 –
CXD3511AQ
(h) HST and PST pulse settings
(1) HSTM (sub address: 002h)
This sets the pulse width for horizontal display start timing pulse HST.
Setting value: 1 = Twice the HCK period width, 0 = HCK period width
Set the width according to the LCD panel specifications.
(2) PSTM (sub address: 002h)
This sets the pulse width for dot sequential precharge start timing pulse PST.
Setting value: 1 = Twice the HCK period width, 0 = HCK period width
Set the width according to the LCD panel specifications.
HSTM, PSTM = 0
HSTM, PSTM = 1
HST, PST
HST, PST
HCK1
HCK1
(3) HSTFIX and HSTPOL (sub addresses: 001h and 002h)
These set the HST and PST pulse output polarities. The polarity changes as follows according to the
combination of linked/not linked with control signal RGT. This setting is shared by HST and PST.
HSTFIX
HSTPOL
RGT
Output polarity
0
0
0
Positive
0
0
1
Negative
0
1
0
Negative
0
1
1
Positive
1
0
0
Negative
1
0
1
Negative
1
1
0
Positive
1
1
1
Positive
– 54 –
CXD3511AQ
(4) HSTPC[7:0], HSTPF[5:0], PSTPC[7:0] and PSTPF[5:0] (sub addresses: 015h to 018h)
These set the HST and PST pulse phases. Reset is applied when the internal HP counter reaches "0", and the
HST and PST pulse phases within 1H can be set at the HCK1 and HCK2 period, respectively, by HSTPC and
PSTPC.
HSTPF and PSTPF can set the HST and PST pulse phase relative to HCK1 and HCK2 in 1-dot units.
Do not set HSTPC and PSTPC to 00h, as the pulses may not be output correctly in this case.
The HSTPF and PSTPF values can be set up to "(HCKC × 2 – 2)". If higher values are set, the pulses are not
output. Set the "(phase difference from HCK pulse)" value.
The figures below show the timings for HSTPC: 04h and HSTPF: 04h, respectively. These timings are the
same for the PST pulse.
HSYNC
0
HP counter
HP[11:0]
HCK1
0
1
2
3
4
HST
Setting prohibited
MCLK
HCK1
HST
HSTPF: 04h
(5) HSTOE and PSTOE (sub address: 02Dh)
These set the output limit of HST and PST pulses, respectively.
Setting value: 1 = Pulse is output, 0 = Output is fixed to "0"
– 55 –
HSTPF[5:0]
5
6
7
CXD3511AQ
(i) HCK1 and HCK2 pulse settings
(1) HCKC[5:0] (sub address: 019h)
This sets the HCK1 and HCK2 period (LCD panel sampling period). Settings which result in an odd number for
Tckw in the figure below are prohibited, so be sure to set a value that results in an even number. Set the
"(Tckw – 1)" value according to the LCD panel specifications. When this setting is changed, the HST and PST
pulse phases also change, so first set HCKC to the correct value and then make the HST and PST settings.
Example setting values are shown in the table below.
LCD panel
Tckw
HCKC setting
SVGA, WXGA
6 clk
05h
XGA, SXGA
12 clk
0Bh
UXGA
24 clk
17h
MCLK
HCK1
Tckw
1 clk
(2) HCKFIX and HCKPOL (sub addresses: 001h and 002h)
These set the HCK pulse output polarity. The polarity relative to the HST pulse changes as follows according to
the combination of linked/not linked with control signal RGT.
HCKFIX
HCKPOL
RGT
Output polarity
0
0
0
Positive
0
0
1
Negative
0
1
0
Negative
0
1
1
Positive
1
0
0
Negative
1
0
1
Negative
1
1
0
Positive
1
1
1
Positive
Positive
Negative
HST
HST
HCK1
HCK1
HSTPF[7:0] = 00h
(3) HCK1OE and HCK2OE (sub address: 02Dh)
These set the output limit of HCK1 and HCK2 pulses, respectively.
Setting value: 1 = Pulse is output, 0 = Output is fixed to "0"
– 56 –
CXD3511AQ
(j) DCK1, DCK1X, DCK2 and DCK2X pulse settings
(1) DCK1F[5:0], DCK1W[5:0], DCK2F[5:0] and DCK2W[5:0] (sub addresses: 01Ah to 01Dh)
These set the DCK1, DCK1X, DCK2 and DCK2X pulse phases and widths. DCK1F sets the DCK1 and
DCK1X pulse phases relative to HCK1 and HCK2 in 1-dot units, and DCK2F sets the DCK2 and DCK2X pulse
phases relative to HCK1 and HCK2 in 1-dot units. Set the "Tdck1 (2) f" value.
The DCKFINV, DCKFIX and RGT settings differ according to whether the phase is synchronized with the rising
edge of HCK1 or HCK2.
The DCK1 and DCK1X pulse width and the DCK2 and DCK2X pulse width can be set in 2-dot units by
DCK1W and DCK2W, respectively. Set the "(Tdck1 (2) W – 2)/2" value.
HCK1
HCK2
Tdck1f
Tdck1w
DCK1
DCK1X
Tdck2f
Tdck2w
DCK2
DCK2X
(2) DCKPOL (sub address: 001h)
This setting switches the DCK1 and DCK1X, DCK2 and DCK2X output polarities. Switching this setting, inverts
the polarities each pair of DCK1 and DCK1X, DCK2 and DCK2X at once.
– 57 –
CXD3511AQ
(3) DCKFINV and DCKFIX (sub address: 002h)
This setting switches the DCK1 and DCK1X, DCK2 and DCK2X output phases relative to HCK1 and HCK2.
The phase changes as follows according to the combination of linked/not linked with right/left inversion control
signal RGT.
DCKFIX
DCKFINV
RGT
Output phase
0
0
0
A
0
0
1
B
0
1
0
B
0
1
1
A
1
0
0
B
1
0
1
B
1
1
0
A
1
1
1
A
A
B
HCK1
HCK1
HCK2
HCK2
DCK1
DCK1
DCK2
DCK2
(4) DCKOE (sub address: 02Dh)
This sets the output limit of DCK1 and DCK2 pulses.
Setting value: 1 = DCK1 and DCK2 pulses are output, 0 = Output is fixed to "0"
(5) DCKXOE (sub address: 02Dh)
This sets the output limit of DCK1X and DCK2X pulses.
Setting value: 1 = DCK1X and DCK2X pulses are output, 0 = Output is fixed to "0"
– 58 –
CXD3511AQ
(k) LCD panel sample-and-hold position setting
SHP[5:0] (sub address: 014h)
This sets the horizontal transfer start pulse and clock pulse phases relative to the video signal to the LCD
panel. The phase can be set in 64 positions with 6 bits. Incrementing SHP by +1 shifts the HST, PST, HCK1,
HCK2, DCK1, DCK1X, DCK2 and DCK2X pulses forward by 1 dot (half the internal clock period). The LCD
panel sample-and-hold position can be set by shifting the above pulse phases forward or backward relative to the
video signal. At this time, the phases between the HST, PST, HCK1, HCK2, DCK1, DCK1X, DCK2 and DCK2X
pulses do not change. The figure below shows an example of HCK1 during 12-dot simultaneous sampling.
This setting eliminates the need to set the sample-and-hold position with a Sony sample-and-hold driver IC,
and makes it possible to adjust the phases of the video signal to the LCD panel and the horizontal transfer
clock without changing the position of the video signal on the screen.
Video signal to LCD panel
HCK1
SHP increased
SHP decreased
Internal CLK
– 59 –
CXD3511AQ
(l) VST and VCK pulse settings
(1) VST1P[11:2] and VST2P[11:2] (sub addresses: 026h to 027h)
These set the VSTL and VSTR pulse rise and fall positions within 1H in 10 bits. The positions can be set in 4-dot
units using the internal HP counter "0" position as the reference. Set the "(Tvstp – 4)/4" value.
See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VST1P or VST2P
settings is reflected to VSTL or VSTR.
HDIN
HP counter
0
Tvstp
VST
VCK
Tvckp
(2) VCK1P[10:1] and VCK2P[10:1] (sub addresses: 024h to 025h)
These set the VCKL and VCKR, FRP and XFRP inversion positions within 1H in 10 bits. The positions can be
set in 2-dot units using the internal HP counter "0" position as the reference. Set the "(Tvckp – 2)/2" value.
See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VCK1P, VCK2P or FRPP
settings is reflected to VCKL or VCKR.
(3) VSTFIX and VCKFIX (sub address: 002h), VSTPOL and VCKPOL (sub address: 001h)
These set the VST and VCK pulse output polarities. The VSTL and VSTR pulse polarities and the VCKL and
VCKR pulse polarities relative to the VSTL and VSTR pulses change as follows according to the combination
of linked/not linked with control signal DWN.
∗∗∗FIX
∗∗∗POL
DWN
Output polarity
0
0
0
Positive
0
0
1
Negative
0
1
0
Negative
0
1
1
Positive
1
0
0
Negative
1
0
1
Negative
1
1
0
Positive
1
1
1
Positive
∗∗∗: VST or VCK
(4) V1OE (sub address: 02Dh)
This sets the output limit of VSTL, VCKL and ENBL pulses.
Setting value: 1 = VSTL, VCKL and ENBL pulses are output, 0 = Output is fixed to "0"
(5) V2OE (sub address: 02Dh)
This sets the output limit of VSTR, VCKR and ENBR pulses.
Setting value: 1 = VSTR, VCKR and ENBR pulses are output, 0 = Output is fixed to "0"
– 60 –
CXD3511AQ
(m) FRP and XFRP pulse settings
(1) FRPM[1:0] (sub address: 002h)
This sets the period for switching the LCD AC conversion signal FRP pulse. 1F/1H, 2F/1H, 1F and 2F inversion
can be set as shown in the figure below. Normally use FRP1, 0: 11.
1H
FRP1, 0: 11
(1F/1H inversion)
FRP1, 0: 01
(2F/1H inversion)
FRP1, 0: 10
(1F inversion)
FRP1, 0: 00
(2F inversion)
1F
(2) FRPP[10:1] (sub address: 00Fh)
This sets the FRP and XFRP inversion positions within 1H in 10 bits. The positions can be set in 2-dot units
using the internal HP counter "0" position as the reference. Set the "(FRP inversion position – HP counter
"0" position – 2)/2" value.
XFRP is output as the polarity inverted FRP pulse.
(3) FRPOE and XFRPOE (sub address: 02Ch)
These set the output limit of FRP and XFRP pulses, respectively.
Setting value: 1 = Pulse is output, 0 = Output is fixed to "0"
– 61 –
CXD3511AQ
(n) VCK and FRP transition point shared setting and V block pulse right/left inversion link setting
FRVC1LNK and RGVLNK (sub address: 003h)
These set the VCKL and VCKR transition points
Setting value: 1 = FRP and VCK transition points are shared,
0 = FRP and VCK transition points are independent
When FRVC1LNK = 1, the VCK inversion timing is forcibly synchronized with the FRP inversion timing. At this
time, which of VCKL or VCKR is linked with the FRP transition point is as follows.
When FRVC1LNK = 0, the VCKL and VCKR transition points are determined by VCK1P[10:1] or VCK2P[10:1]
according to the RGT setting. When RGVLNK = 1, the V block pulses, VSTL, VCKL and ENBL are switched
with VSTR, VCKR and ENBR, respectively, linked with right/left inversion control signal RGT. When RGVLNK =
0, the V block pulses are fixed regardless of the RGT setting. See the following page for a detailed description.
FRVC1LNK
RGVLNK
RGT
Output waveform
0
0
0
A
0
0
1
A
0
1
0
B
0
1
1
A
1
0
0
C
1
0
1
C
1
1
0
D
1
1
1
C
VCKL
VCK1P
A
VCKR
FRP
VCK2P
FRPP
VCKL
VCK2P
B
VCKR
VCK1P
FRP
FRPP
VCKL
C
VCKR
FRP
VCK2P
FRPP
VCKL
VCK2P
D
VCKR
FRP
FRPP
– 62 –
CXD3511AQ
(o) V scanner pulse scan direction link setting
RGVLNK (sub address: 003h)
This sets whether to link the V block pulses, VSTL, VSTR, VCKL, VCKR, ENBL and ENBR with the right/left
inversion control signal RGT.
Setting value: 1 = Linked with RGT, 0 = Independent of RGT
When RGVLNK = 1, rise and fall positions of VSTL and VSTR, ENBL and ENBR pulses and inversion position
of VCKL and VCKR pulses are switched respectively by linking with RGT. When RGVLNK = 0, VSTL, VCKL
and ENBL are set by VST1P, VCK1P, ENB1U and ENB1D, respectively, and VSTR, VCKR and ENBR are set
by VST2P, VCK2P, ENB2U and ENB2D, respectively, independent of the RGT setting.
RGVLNK
RGT
Output waveform
0
0
A
0
1
A
1
0
B
1
1
A
VSTL
VST1P
VSTR
VST2P
VCKL
VCK1P
A
VCKR
VCK2P
ENBL
ENB1D
ENBR
ENB1U
ENB2D
ENB2U
VSTL
VST2P
VSTR
VST1P
VCKL
B
VCK2P
VCKR
VCK1P
ENBL
ENBR
ENB2D
ENB1D
ENB2U
ENB1U
– 63 –
CXD3511AQ
(p) BLK pulse settings
(1) BLKON (sub address: 001h)
This sets the black frame write pulse BLK ON/OFF.
Setting value: 1 = Pulse is output, 0 = DC is output
When BLKON = 1, BLK is output as a single pulse in 1V.
(2) BLKPOL (sub address: 001h)
This sets the black frame write pulse BLK polarity.
Setting value: 1 = Positive polarity, 0 = Negative polarity
Set BLKPOL = 1 for a Sony SVGA panel, and BLKPOL = 0 for an XGA panel.
VST
BLKON: 1, BLKPOL: 1
BLK
BLKON: 0, BLKPOL: 1
BLK
BLKON: 1, BLKPOL: 0
BLK
BLKON: 0, BLKPOL: 0
BLK
(3) SLXBLK (sub address: 003h)
This sets the precharge waveform top/bottom black frame display mode.
Setting value: 1 = XGA type, 0 = Other than XGA type
Set SLXBLK = 1 only when using top/bottom black frame display mode on a Sony XGA type LCD panel. Set
SLXBLK = 0 in all other cases.
VST
VCK
SLXBLK: 0
BLK
PRG
PCG
VST
VCK
SLXBLK: 1
BLK
PRG
PCG
– 64 –
CXD3511AQ
(4) BLKU[10:1] and BLKD[10:1] (sub addresses: 02Ah to 02Bh)
These set the BLK pulse rise and fall positions within 1H in 10 bits. The positions can be set in 2-dot units
using the internal HP counter "0" position as the reference. Set the "(BLK rise/fall position – HP counter "0"
position – 2)/2" value.
(5) BLKOE (sub address: 02Dh)
This is the output limit of BLK pulse.
Setting value: 1 = Pulse is output, 0 = Output is fixed to "0"
– 65 –
– 66 –
—
—
—
—
—
—
—
—
—
—
—
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
PDAT3
USER_GAIN[7:0]
B2_PRE_GAIN[7:0]
B1_PRE_GAIN[7:0]
G2_PRE_GAIN[7:0]
G1_PRE_GAIN[7:0]
R2_PRE_GAIN[7:0]
R1_PRE_GAIN[7:0]
PDAT4
000h
000h
000h
000h
B_MUTE1[9:0]
R_OSD_DAT1[9:0]
R_OSD_DAT2[9:0]
016h
017h
018h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
Initial value
G_MUTE1[9:0]
PDAT0
015h
PDAT1
000h
B2_PRE_BRT[4:0]
B1_PRE_BRT[4:0]
G2_PRE_BRT[4:0]
G1_PRE_BRT[4:0]
R2_PRE_BRT[4:0]
R1_PRE_BRT[4:0]
PDAT2
R_MUTE1[9:0]
B_SUB_GAIN[7:0]
G_SUB_BRT[9:0]
G_SUB_GAIN[7:0]
R_SUB_BRT[9:0]
R_SUB_GAIN[7:0]
USER_BRT[9:0]
GAM_ON
—
—
—
—
—
PDAT5
014h
GAM_SEL
—
—
—
—
—
PDAT6
000h
B_SUB_BRT[10]
G_SUB_BRT[10]
MUTE1_ON
—
—
—
—
—
PDAT7
B_SUB_BRT[9:0]
—
—
R_SUB_BRT[10]
USER_BRT[10]
—
—
—
B_DAT_SW
—
—
—
G_DAT_SW
—
—
—
R_DAT_SW
PDAT8
Data
013h
012h
011h
010h
00Fh
00Eh
—
—
001h
00Dh
—
PDAT9
000h
Sub address
The DSD1 block data format is as follows.
5-2. DSD1 Block (Main Address: 001h)
CXD3511AQ
000h
000h
000h
000h
000h
000h
B_OSD_DAT1[9:0]
B_OSD_DAT2[9:0]
B_OSD_DAT3[9:0]
B_OSD_DAT4[9:0]
R_MUTE2[9:0]
G_MUTE2[9:0]
01Fh
020h
021h
022h
023h
024h
– 67 –
—
—
—
—
—
—
—
—
—
—
—
029h
02Ah
02Bh
02Ch
02Dh
02Eh
02Fh
030h
031h
032h
033h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B2_POST_BRT[6:0]
B2_POST_GAIN[7:0]
B1_POST_BRT[6:0]
B1_POST_GAIN[7:0]
G2_POST_BRT[6:0]
G2_POST_GAIN[7:0]
G1_POST_BRT[6:0]
G1_POST_GAIN[7:0]
R2_POST_BRT[6:0]
R2_POST_GAIN[7:0]
R1_POST_BRT[6:0]
R1_POST_GAIN[7:0]
—: Don't care
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
H_LIM_DAT[9:0]
027h
—
000h
L_LIM_DAT[9:0]
026h
028h
000h
B_MUTE2[9:0]
025h
—
000h
G_OSD_DAT4[9:0]
01Eh
MUTE2_ON
000h
G_OSD_DAT3[9:0]
01Dh
Initial value
000h
PDAT0
G_OSD_DAT2[9:0]
PDAT1
01Ch
PDAT2
000h
PDAT3
G_OSD_DAT1[9:0]
PDAT4
01Bh
Data
000h
PDAT5
R_OSD_DAT4[9:0]
PDAT6
01Ah
PDAT7
000h
PDAT8
R_OSD_DAT3[9:0]
PDAT9
019h
Sub address
CXD3511AQ
CXD3511AQ
The detailed setting contents are described below.
(a) R_DAT_SW, G_DAT_SW and B_DAT_SW (sub addresses: 000h, 004h and 008h)
These select the data path switch block data path.
Setting value: 1 = Data path is switched, 0 = Data path is not switched
(b) R1_PRE_GAIN[7:0], R2_PRE_GAIN[7:0], G1_PRE_GAIN[7:0], G2_PRE_GAIN[7:0],
B1_PRE_GAIN[7:0] and B2_PRE_GAIN[7:0] (sub addresses: 000h, 002h, 004h, 006h, 008h and
00Ah)
These set the pre gain block arithmetic coefficients in 8 bits.
(c) R1_PRE_BRT[4:0], R2_PRE_BRT[4:0], G1_PRE_BRT[4:0], G2_PRE_BRT[4:0], B1_PRE_BRT[4:0]
and B2_PRE_BRT[4:0] (sub addresses: 001h, 003h, 005h, 007h, 009h and 00Bh)
These set the pre bright block arithmetic coefficients in 5 bits with code.
(d) USER_GAIN[7:0] (sub address: 00Ch)
This sets the user gain block arithmetic coefficients in 8 bits.
(e) USER_BRT[10:0] (sub addresses: 00Ch and 00Dh)
This sets the user bright block arithmetic coefficients in 11 bits with code.
(f) R_SUB_GAIN[7:0], G_SUB_GAIN[7:0] and B_SUB_GAIN[7:0] (sub addresses: 00Eh, 010h and
012h)
These set the R, G and B sub gain block arithmetic coefficients in 8 bits.
(g) R_SUB_BRT[10:0], G_SUB_BRT[10:0] and B_SUB_BRT[10:0] (sub addresses: 00Eh to 013h)
These set the R, G and B sub bright block arithmetic coefficients in 11 bits with code.
(h) MUTE1_ON (sub address: 00Bh)
This selects mute 1 block processing ON/OFF.
Setting value: 1 = Mute processing ON, 0 = OFF
(i)
R_MUTE1[9:0], G_MUTE1[9:0] and B_MUTE1[9:0] (sub addresses: 014h to 016h)
These set the mute 1 block data in 10 bits.
– 68 –
CXD3511AQ
(j)
R_OSD_DAT1 to 4[9:0], G_OSD_DAT1 to 4[9:0] and B_OSD_DAT1 to 4[9:0] (sub addresses: 014h
to 022h)
These set the OSD block decode data in 10 bits.
(k) GAM_SEL (sub address: 00Bh)
This selects the gamma block data path.
Setting value: 1 = Path passing through the RAM, 0 = Path not passing through the RAM
(l)
GAM_ON (sub address: 00Bh)
This sets the gamma block RAM operating mode.
Setting value: 1 = Normal operation, 0 = Standby mode
Note that in standby mode, data cannot be written to or read from the RAM. Also, previously set data is held
even when the RAM is set to standby mode.
(m) L_LIM_DAT[9:0] and H_LIM_DAT[9:0] (sub addresses: 026h and 027h)
These set the limiter block limit value data in 10 bits.
Be sure to maintain the relationship L_LIM_DAT < H_LIM_DAT. Note that when both coefficients are set to
000h, limiter processing is not performed.
(n) MUTE2_ON (sub address: 028h)
This selects the mute 2 block processing ON/OFF.
Setting value: 1 = Mute processing ON, 0 = OFF
(o) R_MUTE2[9:0], G_MUTE2[9:0] and B_MUTE2[9:0] (sub addresses: 023h to 025h)
These set the mute 2 block data in 10 bits.
(p) R1_POST_GAIN[7:0], R2_POST_GAIN[7:0], G1_POST_GAIN[7:0], G2_POST_GAIN[7:0],
B1_POST_GAIN[7:0] and B2_POST_GAIN[7:0] (sub addresses: 028h, 02Ah, 02Ch, 02Eh, 030h and
032h)
These set the post gain block arithmetic coefficients in 8 bits.
(q) R1_POST_BRT[6:0], R2_POST_BRT[6:0], G1_POST_BRT[6:0], G2_POST_BRT[6:0],
B1_POST_BRT[6:0] and B2_POST_BRT[6:0] (sub addresses: 029h, 02Bh, 02Dh, 02Fh, 031h and
033h)
These set the post bright block arithmetic coefficients in 7 bits with code.
– 69 –
CSC_XH
—
—
—
006h
007h
008h
– 70 –
000h
000h
000h
000h
000h
000h
000h
000h
CSC_RGP2[9:1]
CSC_RGP3[9:1]
CSC_RGP4[9:1]
CSC_RGP5[9:1]
CSC_RGP6[9:1]
CSC_RGP7[9:1]
CSC_RGP8[9:1]
CSC_GGP1[9:1]
CSC_RGD2
CSC_RGD3
CSC_RGD4
CSC_RGD5
CSC_RGD6
CSC_RGD7
CSC_RGD8
CSC_GGD1
010h
011h
012h
013h
014h
015h
016h
017h
—
—
—
—
000h
CSC_RGP1[9:1]
CSC_RGD1
000h
CSC_VOS[7:2]
00Fh
—
—
—
00Eh
000h
CSC_HOS[7:2]
—
—
—
00Dh
000h
CSC_VINT[7:2]
—
—
—
00Ch
000h
CSC_HINT[7:2]
—
—
—
00Bh
—
—
—
—
000h
000h
000h
000h
CSC_VNUM[5:0]
CSC_R_RGT
000h
000h
CSC_G_RGT
FRM_H2[11:10]
CSC_HNUM[5:0]
CSC_B_RGT
FRM_H1[11:10]
CSC_DWN
CSC_VP[7:0]
CSC_HP[9:1]
FRM_V2[10]
00Ah
CSC_GNUM[2:0]
FRM_V1[10]
—
—
FRM_ON
—
—
CSC_ON
—
009h
—
—
—
000h
FRM_V2[9:0]
004h
005h
000h
Initial value
FRM_V1[9:0]
DATA0
003h
DATA1
000h
DATA2
FRM_H2[9:0]
DATA3
002h
DATA4
000h
DATA5
FRM_H1[9:0]
DATA6
001h
DATA7
000h
DATA8
FRM_DAT[9:0]
DATA9
Data
000h
Sub address
The DSD2 block data format is as follows.
5-3. DSD2 Block (Main Address: 002h)
CXD3511AQ
– 71 –
CCS_GGP7[9:1]
CCS_GGP8[9:1]
CSC_BGP1[9:1]
CSC_BGP2[9:1]
CSC_BGP3[9:1]
CSC_BGP4[9:1]
CSC_BGP5[9:1]
CSC_BGP6[9:1]
CSC_BGP7[9:1]
CSC_GGD7
CSC_GGD8
CSC_BGD1
CSC_BGD2
CSC_BGD3
CSC_BGD4
CSC_BGD5
CSC_BGD6
CSC_BGD7
CSC_BGD8
—
01Dh
01Eh
01Fh
020h
021h
022h
023h
024h
025h
026h
027h
DATA3
R_OFFSET2[4:0]
R_OFFSET4[4:0]
R_OFFSET6[4:0]
02Fh
030h
031h
RGT_SEL_ON
DLY_ON
DLY_DWN
DLY_G_RGT
DLY_R_RGT
000h
000h
R_OFFSET5[4:0]
000h
R_OFFSET3[4:0]
R_OFFSET1[4:0]
000h
—
02Eh
OFFSET_ON
000h
B_GC_ATT[7:0]
—
—
02Dh
02Ch
000h
GC_ON
02Bh
G_GC_ATT[7:0]
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
Initial value
—
DLY_B_RGT
DATA0
—
B_GC_LIM_DAT[9:0]
02Ah
DATA1
R_GC_ATT[7:0]
G_GC_LIM_DAT[9:0]
029h
DATA2
GC_MODE
R_GC_LIM_DAT[9:0]
CSC_XH_DAT[9:2]
028h
OFFSET_MODE[1:0]
CCS_GGP6[9:1]
CSC_GGD6
01Ch
—
CCS_GGP5[9:1]
CSC_GGD5
01Bh
CSC_BGP8[9:1]
CCS_GGP4[9:1]
CSC_GGD4
01Ah
DATA4
CCS_GGP3[9:1]
DATA5
CSC_GGD3
DATA6
019h
DATA7
CCS_GGP2[9:1]
DATA8
CSC_GGD2
DATA9
Data
018h
Sub address
CXD3511AQ
R_OFFSET10[4:0]
R_OFFSET12[4:0]
R_OFFSET14[4:0]
R_OFFSET16[4:0]
R_OFFSET18[4:0]
R_OFFSET20[4:0]
R_OFFSET22[4:0]
R_OFFSET24[4:0]
G_OFFSET2[4:0]
G_OFFSET4[4:0]
G_OFFSET6[4:0]
G_OFFSET8[4:0]
G_OFFSET10[4:0]
G_OFFSET12[4:0]
G_OFFSET14[4:0]
G_OFFSET16[4:0]
G_OFFSET18[4:0]
G_OFFSET20[4:0]
G_OFFSET22[4:0]
G_OFFSET24[4:0]
B_OFFSET2[4:0]
B_OFFSET4[4:0]
B_OFFSET6[4:0]
B_OFFSET8[4:0]
B_OFFSET10[4:0]
B_OFFSET12[4:0]
034h
035h
036h
037h
038h
039h
03Ah
03Bh
03Ch
03Dh
03Eh
03Fh
040h
041h
042h
043h
044h
045h
046h
047h
048h
049h
04Ah
04Bh
04Ch
DATA7
033h
DATA8
R_OFFSET8[4:0]
DATA9
032h
Sub address
DATA6
DATA5
Data
DATA4
DATA3
– 72 –
B_OFFSET11[4:0]
B_OFFSET9[4:0]
B_OFFSET7[4:0]
B_OFFSET5[4:0]
B_OFFSET3[4:0]
B_OFFSET1[4:0]
G_OFFSET23[4:0]
G_OFFSET21[4:0]
G_OFFSET19[4:0]
G_OFFSET17[4:0]
G_OFFSET15[4:0]
G_OFFSET13[4:0]
G_OFFSET11[4:0]
G_OFFSET9[4:0]
G_OFFSET7[4:0]
G_OFFSET5[4:0]
G_OFFSET3[4:0]
G_OFFSET1[4:0]
R_OFFSET23[4:0]
R_OFFSET21[4:0]
R_OFFSET19[4:0]
R_OFFSET17[4:0]
R_OFFSET15[4:0]
R_OFFSET13[4:0]
R_OFFSET11[4:0]
R_OFFSET9[4:0]
R_OFFSET7[4:0]
DATA2
DATA1
DATA0
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
Initial value
CXD3511AQ
B_OFFSET16[4:0]
B_OFFSET18[4:0]
B_OFFSET20[4:0]
B_OFFSET22[4:0]
B_OFFSET24[4:0]
04Fh
050h
051h
052h
DATA7
04Eh
DATA8
B_OFFSET14[4:0]
DATA9
04Dh
Sub address
DATA6
DATA5
Data
DATA4
DATA3
B_OFFSET23[4:0]
B_OFFSET21[4:0]
B_OFFSET19[4:0]
B_OFFSET17[4:0]
B_OFFSET15[4:0]
B_OFFSET13[4:0]
DATA2
DATA1
DATA0
—: Don't care
000h
000h
000h
000h
000h
000h
Initial value
CXD3511AQ
– 73 –
CXD3511AQ
The detailed setting contents are described below.
(a) FRM_ON (sub address: 005h)
This sets the processing ON/OFF for the black frame block.
Setting value: 1 = Black frame processing ON, 0 = Black frame processing OFF
(b) FRM_DAT[9:0] (sub address: 000h)
This sets the data for the black frame processing block in 10 bits.
(c) FRM_H1[11:0] and FRM_H2[11:0] (sub addresses: 001h, 002h and 005h)
These set the horizontal black frame display range for the black frame block in 12 bits. The range can be set in
1-dot units. Set the "display range" value.
HDIN
FRM_H1
FRM_H2
Black frame display range
Black frame display range
(d) FRM_V1[10:0] and FRM_V2[10:0] (sub addresses: 003h to 005h)
These set the vertical black frame display range for the black frame block in 11 bits. The range can be set in
1-line units. Set the "display range – 2" value.
VDIN
FRM_V1
FRM_V2
Black frame display range
Black frame display range
(e) CSC_ON (sub address: 006h)
This sets the processing ON/OFF for the color shading correction block.
Setting value: 1 = ON, 0 = OFF
(f) CSC_R_RGT, CSC_G_RGT and CSC_B_RGT (sub address: 006h)
These set the right/left inversion for the color shading correction block.
Setting value: 1 = Reflects the TG block RGT setting, 0 = Reflects the inverse of TG block RGT setting
(g) CSC_DWN (sub address: 006h)
This sets the up/down inversion for the color shading correction block.
Setting value: 1 = Reflects the TG block DWN setting, 0 = Reflects the inverse of TG block DWN setting
– 74 –
CXD3511AQ
(h) CSC_HP[9:1] (sub address: 007h)
This sets the horizontal correction start position for the color shading correction block in 9 bits. The position
can be set in 2-dot units. The setting range is 020h to 1FEh. Set the "correction start position + 1" value.
(i) CSC_VP[7:0] (sub address: 008h)
This sets the vertical correction start position for the color shading correction block in 8 bits. The position can
be set in 1-line units. The setting range is 00h to FEh. Set the "correction start position – 4" value.
(j) CSC_HNUM[5:0] and CSC_VNUM[5:0] (sub addresses: 009h and 00Ah)
These set the number of horizontal and vertical correction points for the color shading correction block in 6 bits
in the range of 2 to 64 points. Set the "number of correction points – 1" value. The size of the RAM for setting the
correction data is 4096 words, so set the number of correction points as follows.
Number of horizontal correction points × Number of vertical correction points
× Number of gradual correction points ≤ 4096
(k) CSC_HINT[7:2] and CSC_VINT[7:2] (sub addresses: 00Bh and 00Ch)
These set the correction interval for the horizontal and vertical directions of the color shading correction block
in 6 bits. This setting has a setting range from 32 to 256 dots (lines) and can be set in 4-dot (-line) units.
Set the "correction interval/4 – 1" value.
HDIN
Number of
correction points
CSC_HNUM
VDIN
Correction start position
CSC_HP
1
2
3
4
5
6
7
8
9
2
3
4
Color shading correction range
Number of
correction points
CSC_VNUM
5
6
Correction interval
CSC_HINT
Correction start position
CSC_VP
1
7
Correction interval
CSC_VINT
– 75 –
CXD3511AQ
(l) CSC_HOS[7:2] and CSC_VOS[7:2] (sub addresses: 00Dh and 00Eh)
These set the range for which virtual corrections are to be made. The same data as at the edge of the
correction area for color shading correction is assumed for outside the correction area. It is possible to
independently set values from 0 to 256 dots (lines) for the horizontal and vertical directions in 4-dot (-line)
units.
HDIN
VDIN
Correction start position
CSC_VP
Color shading correction range
Virtual correction range
CSC_VOS
Virtual correction range
CSC_HOS
Correction start position
CSC_HP
: Area actually corrected
: Area virtually corrected
(m) CSC_GNUM [2:0] (sub address: 006h)
This sets the number of correction points in the gradual direction for color shading correction. It is possible to set
1 to 8 points. Set the "number of correction points – 1" value.
(n) CSC_RGP1 to 8[9:1], CSC_GGP1 to 8[9:1] and CSC_BGP1 to 8[9:1] (sub addresses: 00Fh to 026h)
These set the correction points for color shading correction in the gradual direction in 2-gradual units
independently for each R, G and B signal. Registers are set in order of lowest number beginning from 3FFh.
Always keep this order in mind when setting data.
3FFh
Same data as Correction Point 1
CSC_R (G, B) GP1
CSC_R (G, B) GP2
300h
CSC_R (G, B) GP3
CSC_R (G, B) GP4
200h
CSC_R (G, B) GP5
CSC_R (G, B) GP6
100h
CSC_R (G, B) GP7
CSC_R (G, B) GP8
000h
Same data as Correction Point 8
– 76 –
CXD3511AQ
(o) CSC_RGD1 to 8, CSC_GGD1 to 8 and CSC_BGD1 to 8 (sub addresses: 00Fh to 026h)
These set to expand data set in RAM for color shading correction by ± 8bits by shifting data 1 bit in the MSB
direction. This setting can be made independently for correction points in the gradual direction for each R, G
and B signal.
Setting value: 1 = Expand by ±8 bits; 0 = Not expanded
(p) CSC_XH (sub address: 006h)
This sets the cross hatch display ON/OFF used during color shading correction.
Setting value: 1 = Display; 0 = Not displayed
(q) CSC_XH_DAT (sub address: 027h)
This sets the display level (gradual level) of the cross hatch pattern used for color shading correction in 2-gradual
units, 9 bits.
(r) GC_ON (sub address: 02Bh)
This sets the ghost cancel block processing ON/OFF.
Setting value: 1 = Ghost cancel ON, 0 = Ghost cancel OFF
(s) GC_MODE (sub address: 02Bh)
This sets the signal processing period of ghost cancel block.
Setting value: 1 = 24-dot period, 0 = 12-dot period
(t) R_GC_LMT_DAT[9:0], G_GC_LMT_DAT[9:0] and B_GC_LIM_DAT[9:0] (sub addresses: 028h to 02Ah)
These set the limiter data of the R, G and B ghost cancel block in 10 bits.
(u) R_GC_ATT[7:0], G_GC_ATT[7:0] and B_GC_ATT[7:0] (sub addresses: 02Bh to 02Dh)
These set the multiplier arithmetic coefficient of the R, G and B ghost cancel block in 8 bits.
(v) RGT_SEL_ON, DLY_ON, DLY_DWN, DLY_R_RGT, DLY_G_RGT and DLY_B_RGT (sub address: 02Eh)
These are the selectable delay line block settings.
RGT_SEL_ON: This sets ON/OFF for port switching linked with right/left inversion.
Setting value: 1 = ON, 0 = OFF
DLY_ON: This sets the dot/line inverted drive support ON/OFF.
Setting value: 1 = ON, 0 = OFF
DLY_DWN: This sets the up/down inversion for the selectable delay line block.
Setting value: 1 = Reflects the TG block DWN setting,
0 = Reflects the inverse of the TG block DWN setting
DLY_R_RGT, DLY_G_RGT and DLY_B_RGT: These set the right/left inversion for the selectable delay line block.
Setting value: 1 = Reflects the TG block RGT setting,
0 = Reflects the inverse of the TG block RGT setting
– 77 –
CXD3511AQ
(w) OFFSET_ON (sub address: 02Eh)
This sets the processing ON/OFF for the cycle offset block.
Setting value: 1 = offset processing ON, 0 = offset processing OFF
(x) OFFSET_MODE[1:0] (sub address: 02Eh)
This sets the counter period for the cycle offset block.
Setting value: 0h = 6-dot period, 1h = 12-dot period, 2h = 24-dot period
(y) R_OFFSET1 to 12[4:0], G_OFFSET1 to 12[4:0] and B_OFFSET1 to 12[4:0] (sub addresses: 02Fh to 052h)
These set the offset data for the cycle offset block in 5 bits with code.
– 78 –
PG_G_ON
PG_R_ON
PG_ON
PG_G_SEL
PDAT4
PG_HWSTP[10:1]
PG_VST[9:0]
PG_VSTP[9:0]
PG_VWST[9:0]
005h
006h
007h
008h
– 79 –
PG_WIDTH[9:0]
PG_SIG1R[9:0]
PG_SIG2R[9:0]
PG_SIG1G[9:0]
PG_SIG2G[9:0]
PG_SIG1B[9:0]
PG_SIG2B[9:0]
00Ch
00Dh
00Eh
00Fh
010h
011h
PG_STEP[9:1]
00Bh
00Ah
PG_VWSTP[9:0]
PG_HWST[10:1]
004h
009h
PG_HSTP[10:1]
003h
—
PG_R_SEL
PDAT5
PG_B_SEL
PDAT3
PG_HSTP[11] PG_HWST[11] PG_HWSTP[11] PG_VST[10]
PG_B_ON
PDAT6
PG_HST[10:1]
PG_STRP_SW PG_STAIR_SW PG_HST[11]
PDAT7
PDAT8
PDAT9
Data
002h
001h
000h
Sub address
The pattern generator block data format is as follows.
5-6. Pattern Generator Block (Main Address: 012h)
PG_PAT[2:0]
PDAT1
PDAT0
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
000h
Initial value
—: Don't care
PG_VSTP[10] PG_VWST[11] PG_VWSTP[11]
PDAT2
CXD3511AQ
CXD3511AQ
The detailed setting contents are described below.
(a) PG_ON (sub address: 000h)
This sets the test signal output ON/OFF.
Setting value: 1 = Test pattern output mode enabled, 0 = Normal signal output
(b) PG_R (G, B)_ON (sub address: 000h)
These set the test signal level setting ON/OFF.
Setting value: 1 = Various settings enabled, 0 = Output fixed to "0"
(c) PG_R (G, B)_SEL (sub address: 000h)
These switch the pattern and non-pattern signal levels within the effective area.
Setting value: 1 = Pattern signal level is PG_SIG1R (G, B), 0 = Pattern signal level is PG_SIG2R (G, B)
(d) PG_PAT[2:0] (sub address: 000h)
This switches the display pattern within the window area.
Setting value: See the table below.
0
Raster
1
Window
2
Vertical stripe/diagonal stripe
3
Horizontal stripe
4
Cross hatch
5
Dot
6
Horizontal ramp/horizontal stair
7
Vertical ramp/vertical stair
(e) PG_STRP_SW (sub address: 001h)
(Valid only when PG_PAT[2:0] = 2h)
This switches between vertical stripe and diagonal stripe.
Setting value: 1 = Diagonal stripe, 0 = Vertical stripe
(f) PG_STAIR_SW (sub address: 001h)
(Valid only when PG_PAT[2:0] = 6h or 7h)
This switches between ramp and stair.
Setting value: 1 = Stair, 0 = Ramp
(g) PG_HST[11:1] (sub addresses: 001h and 002h)
PG_HSTP[11:1] (sub addresses: 001h and 003h)
These set the horizontal effective area in 11 bits. The area can be set in 2-dot units using the front edge of the
HDIN input as the reference. Set the "(set point – 66)/2" value.
– 80 –
CXD3511AQ
(h) PG_HWST[11:1] (sub addresses: 001h and 004h)
PG_HWSTP[11:1] (sub addresses: 001h and 005h)
These set the horizontal window area in 11 bits. The area can be set in 2-dot units using the front edge of the
HDIN input as the reference. Set the "(set point – 68)/2" value.
(i) PG_VST[10:0] (sub addresses: 001h and 006h)
PG_VSTP[10:0] (sub addresses: 001h and 007h)
These set the vertical effective area in 11 bits. The area can be set in 1-line units using the front edge of the
VDIN input as the reference. Set the "set point – 3" value.
(j) PG_VWST[10:0] (sub addresses: 001h and 008h)
PG_VWSTP[10:0] (sub addresses: 001h and 009h)
These set the vertical window area in 11 bits. The area can be set in 1-line units using the front edge of the
VDIN input as the reference. Set the "set point – 4" value.
VDIN
HDIN
PG_HST
PG_HWST
PG_HWSTP
PG_HSTP
PG_VST
Effective area
PG_VWST
Window area
PG_VWSTP
PG_VSTP
(k) PG_STEP[9:1] (sub address: 00Ah)
(Valid for PG_PAT[2:0] = 2h, 3h, 4h, and 5h)
This sets the vertical stripe, diagonal stripe, horizontal stripe, cross hatch and dot period in 9 bits. The period
can be set in 2-dot units. Set the "(period – 2)/2" value.
(l) PG_WIDTH[9:0] (sub address: 00Bh)
(Valid for PG_PAT[2:0] = 2h, 3h, 4h, and 5h)
This sets the vertical stripe, diagonal stripe, horizontal stripe, cross hatch and dot line width in 10 bits. The
width can be set in 1-dot units. Set the "width" value.
(m) PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] (sub addresses: 00Ch to 011h)
These set the output signal level inside and outside the pattern area within the effective area in 10 bits. The
level can be set with an accuracy of 1 bit.
– 81 –
CXD3511AQ
Notes on Handling
• The power supply and GND patterns have a large effect on undesired radiation on the substrate and
interference to analog circuits, etc. General precautions are as follows.
• Make the GND pattern as wide as possible. Using a multi-layer substrate and a solid ground is
recommended.
• Connect each power supply pin to GND via a ceramic chip capacitor of 0.1µF or more located as close
to each pin as possible.
• Do not use this IC under conditions other than the recommended operating conditions.
• Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage
the device, leading to eventual breakdown.
• This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.
• Since this IC utilizes a MOS structure, it may latch up due to excessive noise or power surge greater than the
maximum rating of the I/O pins, interface with two power supplies of another circuit, or the order in which
power is supplied to circuits. Make a thorough study of measures against the possibility of latch up before
use.
• When the initialization of this IC is performed at power-on, system clear cancellation is performed after the
supply voltage is set in the range of the recommended operating conditions and stabilized. Keep in mind that
the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply
voltage is set in the range of the recommended operating conditions.
• When designing the substrate, take sufficient care for the surrounding temperature and heat radiation, and
make sure the IC junction temperature does not exceed the maximum value.
• Be sure to make the number of dot clocks input to the CXD3511AQ in 1H an even number. Note that if there is
an odd number of dot clocks, the internal phase compensation PLL will not operate properly.
• Be sure to make a thorough evaluation of any items not listed in this data sheet.
– 82 –
CXD3511AQ
Application Circuit
CTRL
From A/D converter
Auxiliary pulse
To S/H driver
To LCD panel
To LCD panel
To D/A converter
+2.5V
+3.3V
10µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
10µ
VSTR
VCKR
181 R1IN2
182 R1IN1
R1OUT7 120
R1OUT6 119
183 R1IN0
R1OUT5 118
184 R2IN7
R1OUT4 117
185 R2IN6
R1OUT3 116
VSS 115
186 VDD2
From A/D converter
0.1µ
0.1µ
188 R2IN5
R1OUT2 113
189 R2IN4
R1OUT1 112
190 R2IN3
R1OUT0 111
191 R2IN2
R2OUT9 110
192 R2IN1
R2OUT8 109
193 R2IN0
R2OUT7 108
194 G1IN7
R2OUT6 107
195 G1IN6
R2OUT5 106
196 G1IN5
R2OUT4 105
197 VDD1
R2OUT3 104
198 VSS
R2OUT2 103
199 G1IN4
VSS 102
200 G1IN3
VDD1 101
201 G1IN2
VDD2 100
202 G1IN1
R2OUT1 99
203 G1IN0
R2OUT0 98
204 G2IN7
G1OUT9 97
205 G2IN6
G1OUT8 96
206 G2IN5
G1OUT7 95
207 G2IN4
G1OUT6 94
208 G2IN3
G1OUT5 93
209 VDD1
G1OUT4 92
210 VSS
G1OUT3 91
212 G2IN1
VDD1 89
213 G2IN0
G1OUT2 88
214 B1IN7
G1OUT1 87
215 B1IN6
G1OUT0 86
216 B1IN5
G2OUT9 85
217 B1IN4
VDD2 84
218 B1IN3
G2OUT8 83
219 B1IN2
G2OUT7 82
220 B1IN1
G2OUT6 81
221 VDD1
G2OUT5 80
222 VSS
G2OUT4 79
224 B2IN7
VDD1 77
225 B2IN6
G2OUT3 76
226 B2IN5
G2OUT2 75
227 B2IN4
G2OUT1 74
228 B2IN3
G2OUT0 73
229 B2IN2
B1OUT9 72
230 B2IN1
B1OUT8 71
231 B2IN0
B1OUT7 70
232 R1OSD1
B1OUT6 69
233 R1OSD0
B1OUT5 68
0.1µ
0.1µ
VSS 67
234 VDD2
VDD2 66
235 VSS
237 G1OSD0
B1OUT3 64
238 B1OSD1
B1OUT2 63
239 B1OSD0
B1OUT1 62
B1OUT0 61
10µ
0.1µ
B2OUT9
B2OUT8
B2OUT7
B2OUT6
B2OUT5
VSS
VDD2
B2OUT4
B2OUT3
B2OUT2
B2OUT1
B2OUT0
VSS
CLKOUT
VSS
PLLDIV
VSS
VDD1
VDD2
CLKN
CLKP
VDD1
VDD1
CLKC
VSS
VSS
VDIN
HDIN
VSS
XCLR3
XCLR2
XCLR1
PDAT0
VDD1
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS
B2OSD0
8
VDD2
B2OSD1
7
PDAT6
VSS
6
PDAT7
VDD2
5
PDAT8
G2OSD0
4
PDAT9
G2OSD1
3
PCLK
R2OSD0
2
PCTL
R2OSD1
1
YS2
YS1
240 YM1
CLKSEL2
B1OUT4 65
CLKSEL1
236 G1OSD1
YM2
OSD input
0.1µ
VSS 78
223 B1IN0
0.1µ
0.1µ
VSS 90
211 G2IN2
0.1µ
0.1µ
VDD2 114
187 VSS
10µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
GND
OSD input
Parallel data input
To D/A converter
CLKOUT
+3.3V
CLKN
CLKP
10k
CLKC
+3.3V
VDIN1
1µ
1µ
GND
GND
PLLDIV
1µ
CLKSEL2
10k
CLKSEL1
10k
HDIN1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 83 –
To D/A converter
0.1µ
0.1µ
R2OUT9
R1OUT8
VSS
VDD2
ENBR
VSS
DCK2
DCK2X
VSS
DCK1
DCK1X
RGT
HCK1
HCK2
VSS
VDD2
XRGT
BLK
HST
VDD2
ENBL
VDD1
VCKL
DWN
VSTL
VSS
CTRL
PST
PCG
PO3
PO2
PO1
FRP
HD2
VDD1
XFRP
SHST
DENB
VSS
PRG
VDD1
CLP
PO4
HD1
PO5
TEST1
TEST2
TEST3
TEST4
TEST5
VSS
VDD2
TEST6
R1IN7
R1IN6
R1IN5
R1IN4
R1IN3
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
CXD3511AQ
Package Outline
Unit: mm
240PIN QFP (PLASTIC)
34.6 ± 0.2
4.1 MAX
+ 0.10
0.40 – 0.15
32.0 ± 0.1
180
121
0.10
181
120
A
240
61
1
+ 0.05
0.22 – 0.03
0.25
0˚ to 8˚
60
+ 0.05
0.145 – 0.03
0.08 M
0.45 MIN – 0.75 MAX
0.5
PACKAGE STRUCTURE
DETAIL A
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-240P-L022
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP240-P-3232
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
7.6g
LEAD SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
LEAD TREATMENT
Sn-Bi
– 84 –
Sony Corporation
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