Hanbit HMN12816D-70I Non-volatile sram module 2mbit (128k x 16-bit), 40pin-dip, 5v Datasheet

HANBit
HMN12816D
Non-Volatile SRAM MODULE 2Mbit (128K x 16-Bit), 40pin-Dip, 5V
Part No. HMN12816D
GENERAL DESCRIPTION
The HMN12816D 128K x 16 nonvolatile SRAM’s are 2,097,152-bit fully static, nonvolatile SRAM’s, organized as
131,072 words by 16 bits. Each NVSRAM has a self contained lithium energy source and control circuitry which
constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is
automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package
HMN12816D devices can be used in place of solutions which build nonvolatile 128Kx16 memory by utilizing a
variety of discrete components. There is no limit on the number of write cycles that can be executed and no additional
support circuitry is required for microprocessor interfacing.
The HMN12816D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
PIN ASSIGNMENT
w Access time : 70, 85, 120, 150ns
w High-density design : 256KByte Design
/CEU
/CEL
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Vss
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
/OE
w Battery internally isolated until power is applied
w Industry-standard 40-pin 128K x 16 pinout
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
w Conventional SRAM operation; unlimited write cycles
OPTIONS
MARKING
w Timing
70 ns
85 ns
- 85
-120
150 ns
-150
Rev. 0.0 (April, 2002)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
/WE
A16
A15
A14
A13
A12
A11
A10
A9
Vss
A8
A7
A6
A5
A4
A3
A2
A1
A0
- 70
120 ns
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20
40-pin Encapsulated Package
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HANBit Electronics Co.,Ltd
HANBit
HMN12816D
FUNCTIONAL DESCRIPTION
The HMN12816D devices execute a read cycle whenever /WE (Write Enable) is inactive (high) and either/both of /CEU or
/CEL (Chip Enables) are active (low) and /OE (Output Enable) is active (low). The unique address specified by the 17
address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of /CEU and /CEL
determines whether all or part of the addressed word is accessed. If /CEU is active with /CEL inactive, then only the upper
byte of the addressed word is accessed. If /CEU is inactive with /CEL active, then only the lower byte of the addressed
word is accessed. If both the /CEU and /CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will
be available to the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that /CEU, /CEL and /OE access times are also satisfied. If /CEU, /CEL, and /OE access times are not satisfied, then data
access must be measured from the later occurring signal, and the limiting parameter is either t CO for /CEU, /CEL, or tOE for
/OE rather than address access.
The HMN12816D devices execute a write cycle whenever /WE and either/both of /CEU or /CEL are active (low) after
address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072
words of data is accessed. The status of /CEU and /CEL determines whether all or part of the addressed word is
accessed. If /CEU is active with /CEL inactive, then only the upper byte of the addressed word is accessed. If /CEU is
inactive with /CEL active, then only the lower byte of the addressed word is accessed. If both the /CEU and /CEL inputs
are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of /CEU
and/or /CEL, or WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for
a minimum recovery time (tWR ) before another cycle can be initiated. The /OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (/CEU and/or /CEL, and /OE active)
then /WE will disable the outputs in tODW from its falling edge.
PIN DESCRIPTION
BLOCK DIAGRAM
A0-A16 : Address Inputs
/CEU : Chip enable upper byte
/OE
/CEL : Chip enable lower byte
/WE
2 x 128K x 8
SRAM
DQ0-DQ15
Block
DQ0-DQ15 : Data input / Data output
/WE : Write enable
A0-A16
Power
/CEL
/CEU
/OE : Output enable
VCC : +5V power supply
/CEL
Vss : Ground
/CEU
VCC
Power – Fail
Control
Lithium
Cell
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HANBit Electronics Co.,Ltd
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HMN12816D
READ/WRITE FUNCTION
/OE
/WE
/CEL
/CEU
VCC CURRENT
DQ0-DQ7
DQ8-DQ15
H
H
X
X
ICCO
High-Z
High-Z
L
H
L
L
Output
Output
L
H
L
H
Output
High-Z
L
H
H
L
High-Z
Output
X
L
L
L
Input
Input
X
L
L
H
Input
High-Z
X
L
H
L
High-Z
Input
X
X
H
H
High-Z
High-Z
ICCO
ICCO
ICCS
CYCLE
PERFORMED
Output Disabled
Read Cycle
Write Cycle
Output Disabled
DATA RETENTION MODE
The HMN12816D provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25volts. Data is
maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor
VCC. Should the supply volt-age decay, the NV SRAM’s automatically write protect themselves, all inputs become "don't
care," and all out-puts become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit
connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VCC
-0.3V to 7.0V
VT
-0.3V to 7.0V
Operating temperature
TOPR
0 to 70°C
Storage temperature
TSTG
-40°C to 70°C
Temperature under bias
TBIAS
-10°C to 70°C
TSOLDER
260°C
DC voltage applied on VCC relative to VSS
DC Voltage applied on any pin excluding VCC
relative to VSS
Soldering temperature
CONDITIONS
VT≤ VCC+0.3
For 10 second
NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation
should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
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HMN12816D
RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR )
PARAMETER
SYMBOL
MIN
TYPICAL
MAX
Supply Voltage
VCC
4.5V
5.0V
5.5V
Ground
VSS
0
0
0
Input high voltage
VIH
2.2
-
Vcc+0.3V
Input low voltage
VIL
-0.3
-
0.8V
NOTE: Typical values indicate operation at TA = 25℃
DC ELECTRICAL CHARACTERISTICS (TA= 0OC to 70 OC )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
IIL
-2.0
-
+2.0
mA
IIO
-1.0
-
+1.0
mA
Output Current @ 2.4V
IOH
-1.0
-
-
mA
Output Current @0.4V
IOL
2.0
-
-
mA
-
10
20
mA
ICCS2
-
6
10
mA
ICCO1
-
170
mA
Input Leakage Current
I/O Leakage Current
CE ³VIH£VCC
Standby Current
ICCS1
/CEU,/CEL=2.2V
Standby Current
/CEU,/CEL=Vcc-0.5V
Operating Current
CAPACITANCE (TA=25℃ , f=1MHz, VCC=5.0V)
TYP
MAX
UNITS
Input Capacitance
DESCRIPTION
CIN
20
25
pF
Input/Output Capacitance
CI/O
5
10
pF
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SYMBOL
MIN
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HMN12816D
READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
SYMBOL
Read Cycle Time
tRC
Address Access Time
tACC
Chip enable access time
Output enable to Output valid
CONDITIONS
-70
-85
-120
-150
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
70
-
85
-
120
-
150
-
ns
Output load A
-
70
-
85
-
120
-
150
ns
tACE
Output load A
-
70
-
85
-
120
-
150
ns
tOE
Output load A
-
35
-
45
-
60
-
70
ns
Chip enable to output in low Z
tCLZ
Output load B
5
-
5
-
5
-
10
-
ns
Output enable to output in low Z
tOLZ
Output load B
5
-
0
-
0
-
5
-
ns
Chip disable to output in high Z
tCHZ
Output load B
0
25
0
35
0
45
0
60
ns
Output disable to output high Z
tOHZ
Output load B
0
25
0
25
0
35
0
50
ns
Output hold from address change
tOH
Output load A
10
-
10
-
10
-
10
-
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
SYMBOL
Write Cycle Time
tWC
Chip enable to end of write
tCW
Address setup time
CONDITIONS
-70
-85
-120
-150
UNI
MIN
MAX
MIN
MAX
MIN
MAX
Min
Max
T
70
-
85
-
120
-
150
-
ns
Note 1
65
-
75
-
100
-
100
-
ns
tAS
Note 2
0
-
0
-
0
-
0
-
ns
Address valid to end of write
tAW
Note 1
65
-
75
-
100
-
90
-
ns
Write pulse width
tWP
Note 1
55
-
65
-
85
-
90
-
ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
-
5
-
5
-
ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
15
-
15
-
ns
Data valid to end of write
tDW
30
-
35
-
45
-
50
-
ns
Data hold time (write cycle 1)
tDH1
Note 4
0
-
0
-
0
-
0
-
ns
Data hold time (write cycle 2)
tDH2
Note 4
10
-
10
-
10
-
0
-
ns
Write enabled to output in high Z
tWZ
Note 5
0
25
0
30
0
40
0
50
ns
Output active from end of write
tOW
Note 5
5
-
0
-
0
-
5
-
ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state.
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HMN12816D
TIMING WAVEFORM
READ CYCLE
tRC
Address
tOH
tACC
tCO
/CEU, /CEL
tOD
/OE
tOE
tOD
tCOE
DOUT
Data Valid
WRITE CYCLE NO.1
tWC
Address
tWR1
tWP
/CEU,/CEL
tAW
tWP
/WE
tDS
DIN
Data-in Valid
tODW
DOUT
Data Undefined (1)
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tDH1
6
tOEW
High-Z
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HMN12816D
WRITE CYCLE NO.2
tWC
Address
tWR2
tWP
/WE
tAW
tWP
/CEU,/CEL
tDS
tDH2
Data-in Valid
DIN
tCOE
tODW
DOUT
High-Z
POWER-DOWN/POWER-UP CONDITION
VCC
VTP
3.2V
tF
tR
tPD
tREC
/CEU,/CEL
Data Retention Time
T DR
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HMN12816D
POWER-DOWN/POWER-UP TIMING(tA= 0OC to 70OC)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNITS
NOTES
tPD
0
-
-
us
11
VCC Slew from VTP to 0V
tF
300
-
-
us
-
VCC Slew from 0V to VTP
tR
300
-
-
us
-
tREC
2
-
125
us
-
/CEU,/CEL at VIH before
Power-Down
/CEU,/CEL at VIH after
Power-Up
O
(tA= 25 C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
-
-
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. /WE is high for a read cycle.
2. /OE = VIH or VIL . If /OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical and of /CEU or /CEL and /WE. tWP is measured from the latter of /CEU, /CEL or /WE
going low to the earlier of /CEU, /CEL or /WE going high.
4. tDS is measured from the earlier of /CEU or /CEL or /WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the /CEU or /CEL low transition occurs simultaneously with or later than the /WE low transition in the output buffers
remain in a high impedance state during this period.
7. If the /CEU or /CEL high transition occurs prior to or simultaneously with the /WE high transition, the output buffers
remain in high impedance state during this period.
8. If /WE is low or the /WE low transition occurs prior to or simultaneously with the /CEU or /CEL low transition, the
output buffers remain in a high impedance state during this period.
9. Each HMN12816D has a built-in switch that disconnects the lithium source until VCC is first applied by the user.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied
by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range 0_C to 70_C.
11. In a power down condition the voltage on any pin may not exceed the voltage on Vcc .
12. tWR1, tDH1 are measured from /WE going high.
13. tWR2, tDH2 are measured from /CEU or /CEL going high.
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Rev. 0.0 (April, 2002)
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HMN12816D
PACKAGE DIMENSION
Dimension
Min
Max
A
2.070
2.100
B
0.710
0.740
C
0.365
0.375
D
0.015
-
E
0.008
0.013
F
0.590
0.630
G
0.017
0.023
H
0.090
0.110
I
0.080
0.110
J
0.120
0.150
J
A
H
I
G
C
D
E
B
F
All dimensions are in inches.
ODERING INFORMATION
H M N 128 16 D - 70 I
Operating Temp. : Blank = Commercial (0 to 70 °C )
I = Industrial (-40 to 85°C)
Speed options : 70 = 70 ns
85 = 85 ns
Dip type package
120 = 120 ns
150 = 150 ns
Device : 128K x 16 bit
Nonvolatile SRAM
HANBit Memory Module
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Rev. 0.0 (April, 2002)
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