NSC LMH6629SD Ultra-low noise, high speed operational amplifier Datasheet

LMH6629
Ultra-Low Noise, High Speed Operational Amplifier
General Description
Features
The LMH6629 is a high speed, ultra low-noise amplifier designed for applications requiring wide bandwidth with high
gain and low noise such as in communication, test and measurement, optical and ultrasound systems.
The LMH6629 operates on 2.7 to 5.5V supply with an input
common mode range that extends below ground and outputs
that swing to within 0.8V of the rails for ease of use in single
supply applications. The LMH6629 has user-selectable internal compensation for minimum gains of 4 or 10 controlled by
pulling the COMP pin low or high, thereby avoiding the need
for external compensation capacitors required in competitive
devices.
The low-input noise (0.69nV/√Hz and 2.6 pA/√Hz), low distortion (HD2/ HD3 = −90 dBc/ −94 dBc) and ultra-low DC
errors (780 µV VOS Max @ 25°C, ±0.45 µV/°C drift) allow precision operation in both AC- and DC-coupled applications.
The LMH6629 is fabricated in National Semiconductor’s proprietary SiGe process and is available in a 3mm x 3mm, 8 pin
LLP package.
Specified for VS = 5V, RL = 100Ω, AV = 10V/V
900MHz
■ –3dB bandwidth
0.69 nV/√Hz
■ Input voltage noise
±780 µV
■ Input offset voltage max. @ 25°C
1600 V/ μs
■ Slew rate
−90 dBc
■ HD2 @ f = 1MHz, 2VPP
−94 dBc
■ HD3 @ f = 1MHz, 2VPP
2.7V to 5.5V
■ Supply voltage range
15.5 mA
■ Typical supply current
≥4 or ≥10
■ Selectable min. gain
LLP-8
■ Package
Applications
■
■
■
■
■
■
■
Instrumentation Amplifiers
Ultrasound Pre-amps
Wide-band Active Filters
Opto-electronics
Medical imaging systems
Base-station Amplifiers
Trans-impedance amplifier
Typical Application Circuit
30068011
FIGURE 1. Transimpedance Amplifier
© 2010 National Semiconductor Corporation
300680
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LMH6629 Ultra-Low Noise, High Speed Operational Amplifier
June 3, 2010
LMH6629
Ordering Information
Package
Part Number
Package Marking
LMH6629SD
LLP-8
LMH6629SDE
Transport Media
L6629
250 Units Tape and Reel
LMH6629SDX
4.5k Units Tape and Reel
Connection Diagram
30068052
8-Pin LLP SDA088AD (Top View)
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NSC Drawing
1k Units Tape and Reel
2
SDA08A
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 4)
Human Body Model
Machine Model
Charge-Device Model
Positive Supply Voltage
Differential Input Voltage
Analog Input Voltage Range
Digital Input Voltage
2kV
200V
750V
−0.5 to 6.0V
3V
−0.5 to VS
−0.5 to VS
Operating Ratings
(Note 1)
Supply Voltage (V+ - V−
Operating Temperature Range
Package
2.7V to 5.5V
−40°C to +125°C
(θJA)
71°C/W
LLP-8
5V Electrical Characteristics
The following specifications apply for single supply with VS = 5V, RL = 100Ω terminated to 2.5V, gain = 10V/V, VO = 2VPP, VCM =
VS/2, COMP Pin = HI, unless otherwise noted. Boldface limits apply at the temperature extremes. (Note 2).
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Units
DYNAMIC PERFORMANCE
SSBW
Small signal −3dB
bandwidth
LSBW
Large signal −3dB
bandwidth
0.1 dB bandwidth
SR
tr/tf
Ts
VO = 200 mVPP
900
COMP Pin = LO, AV= 4, VO = 200
mVPP
800
VO = 2VPP
380
COMP Pin = LO, AV= 4, VO = 2VPP
190
AV= 10, VO = 200 mVPP
330
COMP Pin = LO, AV= 4, VO = 200
mVPP
95
AV= 10, 2V step
1600
AV= 4, 2V step,
COMP Pin = LO
530
AV= 10, 2V step, 10% to 90%
0.9
Rise/fall time
AV= 4, 2V step, 10% to 90%,
COMP Pin = LO, (Slew Rate Limited)
2.8
Settling time
AV= 10, 1V step, ±0.1%
42
Overload Recovery
VIN = 1VPP
2
Slew rate
MHz
MHz
MHz
V/μs
ns
NOISE AND DISTORTION
HD2
HD3
2nd order distortion
3rd order distortion
fc = 1MHz, VO = 2VPP
−90
COMP Pin = LO, AV= 4, fc = 1 MHz,
VO = 2VPP
−88
fc = 10 MHz, VO = 2VPP
−70
COMP Pin = LO, fc = 10 MHz, AV=
4V, VO = 2VPP
−65
fc = 1MHz, VO = 2VPP
−94
COMP Pin = LO, AV= 4, fc = 1MHz,
VO = 2VPP
−87
fc = 10 MHz, VO = 2VPP
−82
COMP Pin = LO, fc = 10 MHz, VO =
2VPP
−75
OIP3
Two-tone 3rd order intercept fc = 25 MHz, VO = 2 VPP composite
point
fc = 75 MHz, VO = 2VPP composite
en
Noise Voltage
in
Noise current
Input referred f > 1MHz
3
31
27
dBc
dBc
dBm
0.69
nV/√Hz
2.6
pA/√Hz
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LMH6629
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Soldering Information
See Product Folder at www.national.com and http://
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1)
LMH6629
Symbol
NF
Parameter
Conditions
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Noise Figure
RS = RT = 50Ω
Input voltage range
CMRR > 70 dB
−0.30
RL = 100Ω to VS/2
0.89
0.95
0.82 to
4.19
4.0
3.9
No Load
0.76
0.85
0.72 to
4.28
4.1
4.0
8.0
Units
dB
ANALOG I/O
CMVR
3.8
V
VO
Output voltage range
IOUT
Linear output current
VOS
Input offset voltage
TcVOS
Input offset voltage
temperature drift
IBI
Input bias current
IOS
Input offset current
TCIOS
Input offset voltage
temperature drift
(Note 7)
CCM
Input capacitance
Common Mode
1.7
pF
RCM
Input resistance
Common Mode
450
kΩ
VO = 2.5V (Note 3)
250
±150
(Note 7)
mA
±780
±800
µV
μV/°C
±0.45
(Note 6)
V
−15
−23
−37
μA
±0.1
±1.8
±3.0
μA
±2.8
nA/°C
MISCELLANEOUS PARAMETERS
CMRR
Common mode rejection
ratio
PSRR
AVOL
VCM from 0V to 3.7V
82
70
87
Power supply rejection ratio
81
78
83
Open loop gain
74
72
78
dB
DIGITAL INPUTS/TIMING
VIL
Logic low-voltage threshold PD and COMP pins
VIH
Logic high-voltage
threshold
IIL
Logic low-bias current
IIH
Logic high-bias current
Ten
Enable time
75
Tdis
Disable time
80
0.8
PD and COMP pins
V
2.5
PD and COMP pins = 0.8V (Note 6)
−23
−19
−28
−34
−38
PD and COMP pins = 2.5V (Note 6)
−16
−14
−22
−27
−29
µA
ns
POWER REQUIREMENTS
IS
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Supply Current
No Load, Normal Operation (PD Pin
= HI or open)
15.5
16.7
18.2
No Load, Shutdown (PD Pin =LO)
1.1
1.85
2.0
4
mA
LMH6629
3.3V Electrical Characteristics
The following specifications apply for single supply with VS = 3.3V, RL = 100Ω terminated to 1.65V, gain = 10V/V, VO = 1VPP,
VCM = VS/2, COMP Pin = HI, unless otherwise noted. Boldface limits apply at the temperature extremes. (Note 2)
Symbol
Parameter
Conditions
Min
(Note 5)
Typ
(Note 5)
Max
(Note 5)
Units
DYNAMIC PERFORMANCE
VO = 200 mVPP
820
SSBW
Small signal −3dB bandwidth COMP Pin = LO, AV= 4, VO = 200
mVPP
LSBW
Large signal −3dB bandwidth
0.1 dB bandwidth
SR
Slew rate
MHz
730
VO = 1VPP
540
COMP Pin = LO, AV= 4, VO = 1VPP
320
AV= 10, VO = 200 mVPP
330
COMP Pin = LO, AV= 4, VO = 200
mVPP
85
AV= 10, 1.3V step
1100
COMP Pin = LO, AV= 4, 1.3V step
500
AV= 10, 1V step, 10% to 90%
0.7
tr/tf
Rise/fall time
COMP Pin = LO, AV= 4, 1V step, 10%
to 90% (Slew Rate Limited)
1.3
Ts
Settling time
AV= 10, 1V step, ±0.1%
70
Overload Recovery
VIN = 1VPP
2
MHz
MHz
V/µs
ns
NOISE AND DISTORTION
HD2
HD3
2nd order distortion
3rd order distortion
OIP3
Two-tone 3rd Order Intercept
Point
en
Noise voltage
fc = 1MHz, VO = 1VPP
–82
COMP Pin = LO, AV= 4, fc = 1MHz,
VO = 1VPP
-88
fc = 10 MHz, VO = 1VPP
-67
COMP Pin = LO, fc = 10 MHz, AV= 4V,
VO = 1VPP
-74
fc = 1MHz, VO = 1VPP
-94
COMP Pin = LO, AV= 4, fc = 1MHz,
VO = 1VPP
-112
fc = 10 MHz, VO = 1VPP
-79
COMP pin = LO, fc = 10 MHz, VO =
1VPP
–96
fc = 25 MHz, VO = 1VPP composite
30
fc = 75 MHz, VO = 1VPP composite
26
Input referred, f > 1MHz
dBc
dBc
dBm
0.69
nV/√HZ
2.6
pA/√HZ
8.0
dB
in
Noise current
NF
Noise figure
RS = RT = 50Ω
Input voltage range
CMRR > 70 dB
−0.30
RL = 100Ω to VS/2
0.90
0.95
0.79 to
2.50
2.4
2.3
No load
0.76
0.80
0.70 to
2.60
2.5
2.4
ANALOG I/O
CMVR
VO
IOUT
Output voltage range
Linear output current
VOS
Input Offset Voltage
TcVOS
Input offset voltage
temperature drift
VO = 1.65V (Note 3)
2.1
230
±150
(Note 7)
±1
5
V
V
mA
±680
±700
µV
μV/°C
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LMH6629
Symbol
Parameter
Conditions
Min
(Note 5)
(Note 6)
Typ
(Note 5)
Max
(Note 5)
Units
−15
−23
−35
μA
±0.13
±1.8
±3.0
μA
IBI
Input Bias Current
IOS
Input Offset Current
TCIOS
Input offset voltage
temperature drift
(Note 7)
±3.2
nA/°C
CCM
Input Capacitance
Common Mode
1.7
pF
RCM
Input Resistance
Common Mode
1
MΩ
MISCELLANEOUS PARAMETERS
CMRR
Common Mode Rejection
Ratio
84
81
87
PSRR
Power supply rejection ratio
82
79
84
AVOL
Open Loop Gain
78
73
79
VCM from 0V to 2.0V
dB
DIGITAL INPUTS/TIMING
VIL
Logic low-voltage threshold
VIH
Logic high-voltage threshold
IIL
Logic low-bias current
PD and COMP pins = 0.8V (Note 6)
-17
−14
−23
−28
−32
IIH
Logic high-bias current
PD and COMP pins = 2.0V (Note 6)
−16
−13
−22
−27
−31
Ten
Enable time
75
Tdis
Disable time
80
PD and COMP pins
0.8
2.0
V
µA
ns
POWER REQUIREMENTS
IS
Supply Current
No Load, Normal Operation (PD Pin =
HI or open)
13.7
14.9
16.0
No Load, Shutdown (PD Pin = LO)
0.89
1.4
1.5
mA
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA.
Note 3: The maximum continuous output current (IOUT) is determined by device power dissipation limitations. Continuous short circuit operation at elevated
ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C
Note 4: Human Body Model, applicable std. JESD22-A114C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable
std. JESD22-C101-C.
Note 5: Typical numbers are the most likely parametric norm. Bold numbers refer to over-temperature limits.
Note 6: Negative input current implies current flowing out of the device.
Note 7: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
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6
LMH6629
Typical Performance Characteristics
Unless otherwise specified, VS = ±2.5V, Rf = 240Ω, RL = 100Ω, VOUT = 2VPP, COMP pin = HI, AV = +10 V/V.
Inverting Frequency Response
Inverting Frequency Response
30068003
30068004
Non-Inverting Frequency Response
Non-Inverting Frequency Response
30068005
30068006
Non-Inverting Frequency Response
with Varying VO
Non-Inverting Frequency Response
with Varying VO
30068007
30068008
7
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LMH6629
Non-Inverting Frequency Response
with Varying VO
Non-Inverting Frequency Response
with Varying VO
30068013
30068014
Frequency Response with Cap. Loading
Frequency Response Cap. Loading
30068015
30068016
Frequency Response vs. Rf
Frequency Response vs. Rf
30068017
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30068038
8
LMH6629
Distortion vs. Swing
Distortion vs. Swing
30068043
30068077
Distortion vs. Gain
Distortion vs. Frequency
30068044
30068078
3rd Order Intermodulation Distortion vs. Output Voltage
Input Noise Voltage vs. Frequency
30068062
30068096
9
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LMH6629
Input Noise Current vs. Frequency
Open Loop Gain/Phase Response
30068060
30068063
Output Source Current
Output Sink Current
30068057
30068058
Large Signal Step Response
Large Signal Step Response
30068073
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30068074
10
LMH6629
Large Signal Step Response
Large Signal Step Response
30068064
30068046
Small Signal Step Response
Small Signal Step Response
30068075
30068076
Turn-On Waveform
Turn-Off Waveform
30068025
30068024
11
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LMH6629
Supply Current vs. Supply Voltage
Offset Voltage vs. Supply Voltage (Typical Unit)
30068067
30068090
Input Bias Current vs. Supply Voltage (Typical Unit)
Input Offset Current vs. Supply Voltage (Typical Unit)
30068053
30068091
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12
CONTROL PINS
The LMH6629 has two digital control pins; PD and COMP
pins. The PD pin, used for powerdown, floats high (on) when
not driven. When the PD pin is pulled low, the amplifier is disabled and the amplifier output stage goes into a high
impedance state so the feedback and gain set resistors determine the output impedance of the circuit. The other control
pin, the COMP pin, allows control of the internal compensation and defaults to the lower gain mode or logic 0.
INTRODUCTION
The LMH6629 is a very wide gain bandwidth, ultra low-noise
voltage feedback operational amplifier. The excellent noise
and bandwidth enables applications such as medical diagnostic ultrasound, magnetic tape & disk storage and fiberoptics to achieve maximum high frequency signal-to-noise
ratios. The following discussion will enable the proper selection of external components to achieve optimum system performance.
The LMH6629 has some additional features to allow maximum performance. As shown in Figure 2 there are provisions
for low power shut down and two internal compensation settings, which are further discussed below. Also provided is a
feedback (FB) pin which allows the placement of the feedback
resistor directly adjacent to the inverting input (IN-) pin. This
pin simplifies board layout and minimizes the possibility of
unwanted interaction between the feedback path and other
circuit elements.
COMPENSATION
Nearly all high-speed operational amplifiers are now internally
compensated. To use external compensation capacitors
would compromise stability and performance due to bond
wire and board parasitic reactances. The LMH6629 gives a
degree of flexibility that was lost with on chip compensation.
There are two compensation settings that can be controlled
by the COMP pin. The default setting is set through an internal
pull down resistor and places the COMP pin at the logic 0
state. In this configuration the on chip compensation is set to
the maximum and bandwidth is reduced to enable stability at
gains as low as 4V/V.
When this pin is driven to the logic 1 state the internal compensation is decreased to allow higher bandwidth at higher
gains. In this state the minimum stable gain is 10V/V. Due to
the reduced compensation slew rate and large signal bandwidth are significantly enhanced for the higher gains.
BIAS CURRENT CANCELLATION
The LMH6629 offers exceptional offset voltage accuracy. In
order to preserve the low offset voltage errors, care must be
taken to avoid voltage errors due to input bias currents. This
is important in both inverting and non inverting applications.
The non-inverting circuit is used here as an example. To cancel the bias current errors of the non-inverting configuration,
the parallel combination of the gain setting (Rg) and feedback
(Rf) resistors should equal the equivalent source resistance
(Rseq) as defined in Figure 4. Combining this constraint with
the non-inverting gain equation also seen in Figure 4 allows
both Rf and Rg to be determined explicitly from the following
equations:
30068061
FIGURE 2. 8-Pin LLP Pinout Diagram
The LLP-8 package requires the bottom-side Die Attach Paddle (DAP) to be soldered to the circuit board for proper thermal
dissipation and to get the thermal resistance number specified. The DAP is tied to the V- potential within the LMH6629
package. Thus, the circuit board copper area devoted to DAP
heatsinking connection should be at the V- potential as well.
Please refer to the package drawing for the recommended
land pattern and recommended DAP connection dimensions.
Rf = AVRseq and Rg = Rf/(AV-1)
30068052
FIGURE 3. 8-Pin LLP SDA088AD (Top View)
13
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LMH6629
Application Section
LMH6629
30068018
FIGURE 4. Non-Inverting Amplifier Configuration
When driven from a 0Ω source, such as the output of an op
amp, the non-inverting input of the LMH6629 should be isolated with at least a 25Ω series resistor.
As seen in Figure 5, bias current cancellation is accomplished
for the inverting configuration by placing a resistor (Rb) on the
non-inverting input equal in value to the resistance seen by
the inverting input (Rf || (Rg+Rs)). Rb should to be no less than
25Ω for optimum LMH6629 performance. A shunt capacitor
(not shown) can minimize the additional noise of Rb.
30068019
FIGURE 5. Inverting Amplifier Configuration
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14
30068020
FIGURE 6. Non-Inverting Amplifier Noise Model
Equation 1 provides the general form for total equivalent input
voltage noise density (eni).
Figure 8 illustrates the equivalent noise model using this assumption. Figure 9 is a plot of eni against equivalent source
resistance (Rseq) with all of the contributing voltage noise
source of Equation 2. This plot gives the expected eni for a
given (Rseq) which assumes Rf||Rg = Rseq for bias current
cancellation. The total equivalent output voltage noise (eno) is
eni*AV.
(1)
Equation 1: General Noise Equation
Equation 2 is a simplification of Equation 1 that assumes Rf ||
Rg = Rseq for bias current cancellation:
Equation 2: Noise Equation with
Rf || Rg = Rseq
(2)
Figure 7 schematically shows eni alongside VIN (the portion of
VS source which reaches the non-inverting input of Figure 4)
and external components affecting gain (Av= 1 + Rf / Rg), all
connected to an ideal noiseless amplifier.
30068021
FIGURE 8. Noise Model with Rf||Rg = Rseq
As seen in Figure 9, eni is dominated by the intrinsic voltage
noise (en) of the amplifier for equivalent source resistances
below 15Ω. Between 15Ω and 2.5 kΩ, eni is dominated by the
thermal noise (et = √(4kT(2Rseq)) of the equivalent source resistance Rseq; incidentally, this is the range of Rseq values
where the LMH6629 has the best (lowest) Noise Figure (NF)
for the case where Rseq = Rf || Rg.
Above 2.5 kΩ, eni is dominated by the amplifier’s current noise
(in = √(2) i nRseq). When Rseq = 190Ω (i.e., R seq = en/√(2) i n),
the contribution from voltage noise and current noise of
LMH6629 is equal. For example, configured with a gain of
+10V/V giving a −3dB of 825 MHz and driven from Rseq =
Rf||RG = 20Ω (eni = 1.07 nV√Hz from Figure 9), the LMH6629
produces a total equivalent output noise voltage (eni * 10 V/V
* √(1.57 * 825 MHz)) of 385 μVrms.
30068023
FIGURE 7. Non-Inverting Amplifier Equivalent Noise
Source Schematic
15
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LMH6629
noise model for the non-inverting amplifier configuration
showing all noise sources. In addition to the intrinsic input
voltage noise (en) and current noise (in = in+ = in−) source,
there is also thermal voltage noise (et = √(4KTR)) associated
with each of the external resistors.
TOTAL INPUT NOISE vs. SOURCE RESISTANCE
To determine maximum signal-to-noise ratios from the
LMH6629, an understanding of the interaction between the
amplifier’s intrinsic noise sources and the noise arising from
its external resistors is necessary. Figure 6 describes the
LMH6629
• Choose the Optimum RS (ROPT)
ROPT is the point at which the NF curve reaches a minimum
and is approximated by:
ROPT ≈ en/in
Figure 10 is a plot of NF vs RS with the circuit of Figure 4 (Rf
= 240Ω, AV = +10V/V). The NF curves for both Unterminated
(RT = open) and Terminated systems (RT = RS) are shown.
Table 1 indicates NF for various source resistances including
RS = ROPT.
30068022
FIGURE 9. Voltage Noise Density vs. Source Resistance
If bias current cancellation is not a requirement, then Rf || Rg
need not equal Rseq. In this case, according to Equation 1,
Rf||Rg should be as low as possible to minimize noise. Results
similar to Equation 1 are obtained for the inverting configuration of Figure 5 if Rseq is replaced by Rb and Rg is replaced by
Rg + Rs. With these substitutions, Equation 1 will yield an eni
referred to the non-inverting input. Referring eni to the inverting input is easily accomplished by multiplying eni by the ratio
of non-inverting to inverting gains (1+Rg/Rf).
30068079
FIGURE 10. Noise Figure vs. Source Resistance
NOISE FIGURE
Noise Figure (NF) is a measure of the noise degradation
caused by an amplifier.
Equation 3: General Noise Figure Equation
TABLE 1. Noise Figure for Various Rs
(3)
Looking at the two parts of the NF expression (inside the log
function) yields:
Si/So→ Inverse of the power gain provided by the amplifier
No/Ni→ Total output noise power, including the contribution of
RS, divided by the noise power at the input due to RS
To simplify this, consider Na as the noise power added by the
amplifier (reflected to its input port):
Si/So→ 1/G
No/Ni→ G * (Ni+Na) /Ni (where G*(Ni +Na ) = No)
Substituting these two expressions into the NF expression:
Equation 4: Simplified Noise Figure Equation
NF (Terminated)
(dB)
NF (Unterminated)
(dB)
50
7.96
3.18
ROPT
4.13
(ROPT = 750Ω)
1.12
(ROPT = 350Ω)
SINGLE SUPPLY OPERATION
The LMH6629 can be operated with single power supply as
shown in Figure 11. Both the input and output are capacitively
coupled to set the DC operating point.
(4)
The noise figure expression has simplified to depend only on
the ratio of the noise power added by the amplifier at its input
(considering the source resistor to be in place but noiseless
in getting Na) to the noise power delivered by the source resistor (considering all amplifier elements to be in place but
noiseless in getting Ni).
For a given amplifier with a desired closed loop gain, to minimize noise figure:
• Minimize Rf||Rg
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RS (Ω)
30068026
FIGURE 11. Single Supply Operation
16
Equation 5: Optimum CF Value
(5)
Equation 6: Resulting -3dB Bandwidth
(6)
Equation 7 provides the total input current noise density (ini)
equation for the basic Transimpedance configuration and is
plotted against feedback resistance (RF) showing all contributing noise sources in Figure 14. The plot indicates the
expected total equivalent input current noise density (ini) for a
given feedback resistance (RF). This is depicted in the
schematic of Figure 15 where total equivalent current noise
density (ini) is shown at the input of a noiseless amplifier and
noiseless feedback resistor (RF). The total equivalent output
voltage noise density (eno) is ini*RF.
30068011
FIGURE 12. 200MHz Transimpedance Amplifier
Configuration
Figure 13 shows the Noise Gain (NG) and transfer function
(I-V Gain). As with most Transimpedance amplifiers, it is required to compensate for the additional phase lag (Noise Gain
zero at fZ) created by the total input capacitance ( CD (diode
capacitance) + CCM (LMH6629 input capacitance) ) looking
into RF; this is accomplished by placing CF across RF to create
enough phase lead (Noise Gain pole at fP) to stabilize the
loop.
30068028
FIGURE 14. Current Noise Density vs. Feedback
Resistance
Equation 7: Noise Equation for Transimpedance
Amplifier
(7)
30068002
FIGURE 13. Transimpedance Amplifier Noise Gain &
Transfer Function
17
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LMH6629
The optimum value of CF is given by Equation 5 resulting in
the I-V -3dB bandwidth shown in Equation 6, or around
200MHz in this case (assuming GBWP= 4GHz with COMP
pin = HI). This CF value is a “starting point” and CF needs to
be tuned for the particular application as it is often less than
1pF and thus is easily affected by board parasitics, etc. For
maximum speed, the LMH6629 COMP pin should be HI.
LOW-NOISE TRANSIMPEDANCE AMPLIFIER
Figure 12 implements a high speed, single supply, low-noise
Transimpedance amplifier commonly used with photodiodes. The transimpedance gain is set by RF.
LMH6629
pass filter topology. Using component predistortion methods
discussed in OA-21 enables the proper selection of components for these high-frequency filters.
30068012
FIGURE 15. Transimpedance Amplifier Equivalent Input
Source Model
30068036
From Figure 14, it is clear that with LMH6629’s extremely low
noise characteristics, for RF < 2.5kΩ, the noise performance
is entirely dominated by RF thermal noise. Only above this
RF threshold, LMH6629’s input noise current (in) starts being
a factor and at no RF setting does the LMH6629 input noise
voltage play a significant role. This noise analysis has ignored
the possible noise gain increase, due to photo-diode capacitance, at higher frequencies.
FIGURE 17. Low Pass Sallen-Key Active Filter Topology
LOW-NOISE MAGNETIC MEDIA EQUALIZER
The LMH6629 implement a high-performance low-noise
equalizer for such application as magnetic tape channels as
shown in Figure 18. The circuit combines an integrator (used
to limit noise) with a bandpass filter (used to boost the response centered at a frequency or over a band of interest) to
produce the low noise equalization. The circuit’s simulated
frequency response is illustrated in Figure 19.
In this circuit, the bandpass filter center frequency is set by
LOW-NOISE INTEGRATOR
The LMH6629 implement a deBoo integrator shown in Figure
16. Positive feedback maintains integration linearity. The
LMH6629’s low input offset voltage and matched inputs allow
bias current cancellation and provide for very precise integration. Keeping RG and RS low helps maintain dynamic
stability.
For higher selectivity, use high C values; for wider bandwidth,
use high L values, while keeping the product of L and C values
the same to keep fc intact. The integrator’s -3dB roll-off is set
by
If
the integrator and the bandpass filter frequency interaction is
minimized so that the operating frequencies of each can be
set independently. Lowering the value of R2 increases the
bandpass gain (boost) without affecting the integrator frequencies. With the LMH6629’s wide Gain Bandwidth (4GHz),
the center frequency could be adjusted higher without worries
about loop gain limitation. This increases flexibility in tuning
the circuit.
30068029
FIGURE 16. Noise Integrator
HIGH-GAIN SALLEN-KEY ACTIVE FILTERS
The LMH6629 is well suited for high-gain Sallen-Key type of
active filters. Figure 17 shows the 2nd order Sallen-Key low-
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18
LMH6629
30068031
FIGURE 18. Low-Noise Magnetic Media Equalizer
circuit oscillations (see Application Note OA-15 for more information). Use high-quality chip capacitors with values in the
range of 1000 pF to 0.1F for power supply bypassing. One
terminal of each chip capacitor is connected to the ground
plane and the other terminal is connected to a point that is as
close as possible to each supply pin as allowed by the
manufacturer’s design rules. In addition, connect a tantalum
capacitor with a value between 4.7 μF and 10 μF in parallel
with the chip capacitor.
Signal lines connecting the feedback and gain resistors
should be as short as possible to minimize inductance and
microstrip line effect. Place input and output termination resistors as close as possible to the input/output pins. Traces
greater than 1 inch in length should be impedance matched
to the corresponding load termination.
Symmetry between the positive and negative paths in the
layout of differential circuitry should be maintained to minimize the imbalance of amplitude and phase of the differential
signal.
Component value selection is another important parameter in
working with high-speed/high-performance amplifiers.
Choosing external resistors that are large in value compared
to the value of other critical components will affect the closed
loop behavior of the stage because of the interaction of these
resistors with parasitic capacitances. These parasitic capacitors could either be inherent to the device or be a by-product
of the board layout and component placement. Moreover, a
large resistor will also add more thermal noise to the signal
path. Either way, keeping the resistor values low will diminish
this interaction. On the other hand, choosing very low value
resistors could load down nodes and will contribute to higher
overall power dissipation and high distortion.
30068032
FIGURE 19. Equalizer Frequency Response
LAYOUT CONSIDERATIONS
National Semiconductor suggests the copper patterns on the
evaluation board(s) for this product. These board(s) are also
useful as an aid in device testing and characterization. As is
the case with all high-speed amplifiers, accepted-practice RF
design technique on the PCB layout is mandatory. Generally,
a good high frequency layout exhibits a separation of power
supply and ground traces from the inverting input and output
pins. Parasitic capacitances between these nodes and
ground may cause frequency response peaking and possible
19
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LMH6629
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin LLP
NS Package Number SDA08A
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20
LMH6629
Notes
21
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LMH6629 Ultra-Low Noise, High Speed Operational Amplifier
Notes
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