TI AMC1203BPSA 1-bit, 10mhz, 2nd-order, isolated delta-sigma modulator Datasheet

AMC1203
www.ti.com
SBAS427 – FEBRUARY 2008
1-Bit, 10MHz, 2nd-Order, Isolated Delta-Sigma Modulator
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
The AMC1203 is a 1-bit, 10MHz, isolated delta-sigma
(ΔΣ) modulator with an output buffer separated from
the input interface circuitry by a silicon dioxide (SiO2)
isolation barrier. This barrier provides galvanic
isolation of up to 4000VPEAK. Used in conjunction with
isolated power supplies, these devices prevent noise
currents on a data bus or other circuits from entering
the local ground and interfering with or damaging
sensitive circuitry.
1
2
•
•
16-Bit Resolution
SNR: 80.5dB min
THD: –88dB max (AMC1203B)
±280mV Input Range with +5V Supply
Internal 2.5V Reference Voltage: 1% Accuracy
Gain Error: ±1% (AMC1203B)
UL1577, IEC60747-5-2 (VDE0884, Rev. 2), and
IEC61010-1 Approved
– Isolation: 4000VPEAK,
Working Voltage: 560V
– Transient Immunity: 15kV/µs
Typical 25-Year Life at Rated Working Voltage
(see Application Report SLLA197)
Operating Temperature Range:
–40°C to +105°C
The AMC1203 modulator operates from a +5V supply
with a dynamic range of 95dB. The differential inputs
are ideal for direct connection to shunt resistors or
other low-level signal sources. With the appropriate
digital filter and modulator rate, the device can be
used to achieve 16-bit analog-to-digital (A/D)
conversion with no missing codes. An effective
resolution of 14 bits and an SNR of 85dB (typical)
can be maintained with a sinc3 filter with a decimation
ratio of 256.
APPLICATIONS
•
The modulator output is translated to a balanced
signal and then transferred by the capacitive isolation
barrier. Across the isolation barrier, a differential
comparator receives the logic transition information,
and then sets or resets a flip-flop and the output
circuit accordingly.
Shunt Based Current Sensing in:
– Motor Control
– Uninterruptible Power Supplies
– Power Inverters
– Industrial Process Control
The AMC1203 is available in an SO-8 gull-wing
package. SO-8 and SO-16 packages are planned for
release in 2008. The AMC1203 is characterized for
operation over the ambient temperature range of
–40°C to +105°C.
Isolation Barrier
+
VIN+
2nd-Order
DS Modulator
Output
Buffer
VREF
MDAT
+
VIN-
Interface Circuit
-
POR
BIAS
POR
+
Buffer
20MHz
RC
Oscillator
2.5V
VREF
Output
Buffer
VREF
MCLK
+
-
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
AMC1203
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SBAS427 – FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
AMC1203
AMC1203B
(1)
(2)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
SO-8 Gull-Wing
DUB
–40°C to +105°C
AMC1203
SO-8 (2)
PSA
–40°C to +105°C
TBD
SO-16 (2)
DW
–40°C to +105°C
TBD
SO-8 Gull-Wing
DUB
–40°C to +105°C
AMC1203
SO-8 (2)
PSA
–40°C to +105°C
TBD
SO-16 (2)
DW
–40°C to +105°C
TBD
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
AMC1203DUB
Tube, 50
AMC1203DUBR
Tape and Reel, 700
AMC1203PSA
Tube, 80
AMC1203PSAR
Tape and Reel, 2000
AMC1203DW
Tube, 40
AMC1203DWR
Tape and Reel, 2000
AMC1203BDUB
Tube, 50
AMC1203BDUBR
Tape and Reel, 700
AMC1203BPSA
Tube, 80
AMC1203BPSAR
Tape and Reel, 2000
AMC1203BDW
Tube, 40
AMC1203BDWR
Tape and Reel, 2000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
SO-8 and SO-16 packages available in 2008.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
Supply voltage, VDD1 to GND1 or VDD2 to GND2
Analog input voltage at VIN+, VIN–
Input current to any pin except supply pins
Continuous total power dissipation
(1)
2
UNIT
–0.3 to +6
V
GND1 – 0.3 to VDD1 + 0.3
V
±10
mA
See Dissipation Ratings Table
+150
°C
Human body model (HBM)
JEDEC standard 22, test method A114-C.01
±3000
V
Charged device Model (CDM)
JEDEC standard 22, test method C101
±1500
V
Machine Model (MM)
JEDEC standard 22, test method A115A
±200
V
Maximum junction temperature, TJ
Electrostatic discharge (ESD), all pins
AMC1203
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
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THERMAL CHARACTERISTICS (1)
Over recommended operating conditions, unless otherwise noted.
PARAMETER
SO-8 GULL-WING
SO-8
SO-16
UNIT
Low-K
127
246
104
°C/W
High-K
78
164
58
°C/W
θJA
Junction-to-air thermal resistance
θJC
Junction-to-case thermal resistance
61
32
25
°C/W
PD
Device power dissipation (max)
110
110
110
mW
(1)
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
Supply voltage, VDD1 to GND1 or VDD2 to GND2
4.5
5.0
5.5
Common-mode operating range, VCM
Differential input voltage, (VIN+) – (VIN–)
Operating junction temperature range, TJ (see the Thermal Characteristics table)
UNIT
V
0
VDD1
V
–280
280
mV
–40
+125
°C
DISSIPATION RATINGS (1)
PACKAGE
DERATING FACTOR
ABOVE TA = +25°C
TA ≤ +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +125°C
POWER RATING
SO-8 Gull-Wing
7.9mW/°C
984mW
629mW
511mW
354mW
SO-8
4.1mW/°C
508mW
325mW
264mW
182mW
SO-16
9.6mW/°C
1201mW
769mW
625mW
432mW
(1)
Based on Low-K thermal resisitance.
REGULATORY INFORMATION
VDE
UL
Certified according to IEC 60747-5-2
Recognized under 1577 Component Recognition Program
File Number: 40014131
File Number: E181974
IEC 60747-5-2 ISOLATION CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted.
PARAMETER
VIORM
VPD
TEST CONDITIONS
Maximum working insulation voltage
Input to output test voltage
VALUE
UNIT
560
V
Method A, after input or safety test (subgroup 2 or 3),
VPD = VIORM × 1.2, t = 10s, partial discharge < 5pC
672
V
Method A, after environmental test (subgroup 1),
VPD = VIORM × 1.6, t = 10s, partial discharge < 5pC
896
V
Method B1, routine and initial test, VPD = VIORM × 1.875,
100% production test with t = 1s, partial discharge < 5pC
1050
V
VIOTM
Transient overvoltage
t = 60s
4000
V
RS
Isolation resistance
VIO = 500V at TS
> 109
Ω
PD
Pollution degree
2
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PACKAGE CHARACTERISTICS (1)
Over recommended operating conditions, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal to terminal distance
through air
L(I02)
Minimum external tracking (creepage)
Shortest terminal to terminal distance
across the package surface
CTI
Tracking resistance (comparative
tracking index)
DIN IEC 60112 / VDE 0303 Part 1
≥ 175
V
Minimum internal gap (internal
clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
7.0
mm
7.0
mm
Input to output, VIO = 500V, all pins on
each side of the barrier tied together
creating a two-terminal device, TA < +85°C
> 1012
Ω
Input to output, VIO = 500V,
+100°C ≤ TA < TA max
> 1011
Ω
CIO
Barrier capacitance input to output
VI = 0.8VPP at 1MHz
1.2
pF
CI
Input capacitance to ground
VI = 0.8VPP at 1MHz
3
pF
(1)
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting pads of the isolator
on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to
the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit
board are used to help increase these specifications.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is
that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction
temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER
IS
Safety input, output, or supply current
TC
Maximum case temperature
TEST CONDITIONS
MIN
TYP
MAX
θJA = 246°C/W, VI = 5.5V, TJ = +150°C, TA = +25°C
UNIT
90
mA
+150
°C
IEC 61000-4-5 RATINGS
PARAMETER
Surge immunity
TEST CONDITIONS
1.2/50µs voltage surge and 8/20µs current surge
VALUE
UNIT
±6000
V
IEC 60664-1 RATINGS
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
IIIa
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage < 300 VRMS
I-III
Installation classification
4
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 4.5V to 5.5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with
OSR = 256, unless otherwise noted.
AMC1203
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP (1)
MAX
UNIT
16
Bits
DC ACCURACY
AMC1203
±3
±9
LSB
AMC1203B
±2
±6
LSB
+1
LSB
INL
Integral linearity error (2)
DNL
Differential nonlinearity (3)
–1
VOS
Offset error
(4)
–1
TCVOS
Offset error thermal drift
GERR
Gain error
TCGERR
Gain error thermal drift
PSRR
Power-supply rejection ratio
±0.1
1
mV
±1.5
±5
µV/°C
%
AMC1203
–2
±0.2
2
AMC1203B
–1
±0.2
1
%
±20
ppm/°C
80
dB
ANALOG INPUTS
FSR
Full-scale differential voltage input range
VCM
Operating common-mode signal (3)
CI
Input capacitance to GND1
CID
Differential input capacitance
RID
Differential input resistance
IIL
Input leakage current
CMTI
Common-mode transient immunity
CMRR
Common-mode rejection ratio
(VIN+) – (VIN–)
–320
320
–0.1
5
VIN+ or VIN–
3
6
pF
kΩ
5
15
VIN from 0V to 5V at 50kHz
V
pF
28
–5
VIN from 0V to 5V at 0Hz
mV
nA
kV/µs
92
dB
105
dB
INTERNAL CLOCK
tCLK
Clock period
See Figure 2
83.33
100
125
ns
fCLK
Clock frequency
See Figure 2
8
10
12
MHz
tH
Clock high-time
See Figure 2
(tCLK/2) – 8
50
(tCLK/2) + 8
ns
tD1
Data valid time after falling edge of clock
See Figure 2
–2
0
2
ns
85
AC ACCURACY
SINAD
Signal-to-noise + distortion
fIN = 1kHz
80
SNR
Signal-to-noise ratio
fIN = 1kHz
80.5
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
(1)
(2)
(3)
(4)
dB
85
dB
AMC1203, fIN = 1kHz
–92
–84.5
AMC1203B, fIN = 1kHz
–95
–88
AMC1203, fIN = 1kHz
86
92
AMC1203B, fIN = 1kHz
89
95
dB
dB
All typical values are at TA = +25°C
Integral nonlinearity is defined as the maximum deviation of the line through the inputs of the specified input range of the transfer curve
of the specified VIN expressed either as number of LSBs, or as a percent of the specified 560mV input range.
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 4.5V to 5.5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with
OSR = 256, unless otherwise noted.
AMC1203
MIN
TYP (1)
IOH = –8mA
VDD2 – 0.8
4.6
V
IOH = –4mA
VDD2 – 0.4
4.8
V
PARAMETER
TEST CONDITIONS
MAX
UNIT
DIGITAL OUTPUTS
VOH
High-level output voltage
VOL
Low-level output voltage
IOL = 8mA
0.3
0.8
V
IOL = 4mA
0.2
0.4
V
5.0
5.5
V
POWER SUPPLY
VDD
Supply voltage
VDD1 and VDD2
4.5
IDD1
Analog supply current
6
8
IDD2
Digital supply current
10
12
mA
PD
Power dissipation
80
110
mW
mA
EQUIVALENT INPUT CIRCUIT
RSW
350W (typ)
AIN+
CINT
7pF (typ)
1.5pF
Switching
Frequency = CLK
High
Impedance
>1GW
VCM
1.5pF R
SW
350W (typ)
CINT
7pF (typ)
AIN-
High
Impedance
>1GW
Figure 1. Equivalent Analog Input Circuit
6
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PIN ASSIGNMENTS
DUB or PSA(1) PACKAGE
SO-8 Gull-Wing or SO-8
(TOP VIEW)
VDD1
1
VIN+
2
DW PACKAGE(1)
SO-16
(TOP VIEW)
8
VDD2
VDD1
1
16 GND2
7
MCLK
VIN+
2
15 NC
14 VDD2
AMC1203
VIN-
3
6
MDAT
VIN-
3
GND1
4
5
GND2
GND1
4
13 MCLK
AMC1203
(1)
PSA package available in late 2008.
Table 1. SO-8 PIN CONFIGURATION
PIN
NO.
VDD1
Analog power supply
2
VIN+
Noninverting analog input
3
VIN–
Inverting analog input
4
GND1 Analog ground
5
GND2 Digital ground
7
8
5
12 NC
NC
6
11 MDAT
NC
7
10 NC
GND1
8
9
GND2
NAME DESCRIPTION
1
6
NC
(1)
DW package available in 2008.
Table 2. SO-16 PIN CONFIGURATION
PIN
NO.
NAME DESCRIPTION
MDAT Modulator data output
1
VDD1
Analog power supply
MCLK Modulator clock output
2
VIN+
Noninverting analog input
VIN–
Inverting analog input
VDD2
3
Digital power supply
4, 8 (1)
5, 6, 7,
10, 12,
15
9,
16 (1)
(1)
GND1 Analog ground
NC
No internal connection—can be tied to any
potential or left unconnected
GND2 Digital ground
11
MDAT Modulator data output
13
MCLK Modulator clock output
14
VDD2
Digital power supply
Both pins are connected internally via a low-impedance path;
thus only one of the pins must be tied to the ground plane.
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TIMING INFORMATION
tCLK
tHIGH
MCLK
tD
tS
tH
MDAT
Figure 2. Modulator Output Mode Timing
TIMING CHARACTERISTICS FOR MODULATOR OUTPUT MODE
Over recommended operating free-air temperature range at –40°C to +105°C, VDD1 = +5V, and VDD2 = +5V, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
83.33
100
125
ns
(tCLK/2) – 8
tP/2
(tCLK/2) + 8
ns
–2
0
2
ns
tCLK
MCLK clock period
tHIGH
MCLK clock high time
tD
Data delay after falling edge of MCLK
tS
Data setup time prior to rising edge of MCLK
31.5
ns
tH
Data hold time after rising edge of MCLK
31.5
ns
8
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TYPICAL CHARACTERISTICS
At VDD1 = VDD2 = 5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with OSR = 256, unless otherwise noted.
INTEGRAL NONLINEARITY
vs INPUT SIGNAL AMPLITUDE
INTEGRAL NONLINEARITY
vs TEMPERATURE
6
3
5
4
2
3
1
INL (LSB)
INL (LSB)
2
1
0
-1
0
-1
-2
-3
-2
-4
-5
-6
-300
-3
-200
-100
0
VIN (mV)
100
200
300
20 35 50 65
Temperature (°C)
80
Figure 3.
Figure 4.
OFFSET ERROR
vs SUPPLY VOLTAGE
OFFSET ERROR
vs TEMPERATURE
0.20
0.5
0.15
0.4
95
110 125
0.3
0.10
0.2
0.05
VOS (mV)
VOS (mV)
5
-40 -25 -10
0
-0.05
0.1
0
-0.1
-0.2
-0.10
-0.3
-0.15
-0.4
-0.5
4.75
5.00
VDD1 (V)
5.25
5.50
5
-40 -25 -10
20 35 50 65
Temperature (°C)
80
95
Figure 5.
Figure 6.
GAIN ERROR
vs TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs OVERSAMPLING RATIO
0
18
-0.1
16
-0.2
14
-0.3
12
ENOB (Bits)
Gain (%)
-0.20
4.50
-0.4
-0.5
110 125
Sinc3 Filter
Sinc2 Filter
10
8
-0.6
6
-0.7
4
-0.8
2
Sinc Filter
0
-0.9
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
1
Figure 7.
10
100
OSR
1000
10000
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with OSR = 256, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL AMPLITUDE
SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
100
90
fIN = 500Hz
89
90
87
70
86
SNR (dB)
SNR (dB)
88
80
60
85
84
83
50
82
40
81
30
80
1
10
100
1000
-40 -25 -10
5
VIN (mVPP)
Figure 10.
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
110
90
105
89
110 125
fIN = 1kHz
87
95
SNR (dB)
SNR (dB)
95
88
90
85
86
85
84
83
80
82
75
81
70
80
100
1k
fIN (Hz)
10k
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
-80
-80
-85
-85
-90
-90
THD (dB)
THD (dB)
80
Figure 9.
100
-95
110 125
-95
-100
-100
-105
-105
-110
-110
100
1k
fIN (Hz)
10k
-40 -25 -10
Figure 13.
10
20 35 50 65
Temperature (°C)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with OSR = 256, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 0.56VPP)
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 500Hz, 0.56VPP)
-60
-80
-80
-100
-100
-120
-120
-140
-140
0
2
4
6
8
10
12
Frequency (kHz)
14
16
18
20
0
2
4
6
8
10
12
Frequency (kHz)
14
16
Figure 15.
Figure 16.
COMMON-MODE REJECTION RATIO
vs INPUT SIGNAL FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
120
18
20
110
With
Sinc3 Filter
100
110
90
PSRR (dB)
CMRR (dB)
-60
100
Without
Filter
80
70
60
90
50
80
40
100
1k
10k
fIN (Hz)
100k
1M
100
1k
10k
100k
Frequency (Hz)
Figure 17.
Figure 18.
INTERNAL CLOCK FREQUENCY
vs SUPPLY VOLTAGE
INTERNAL CLOCK FREQUENCY
vs TEMPERATURE
10.40
10.5
10.35
10.4
10.25
fCLK (MHz)
fCLK (MHz)
10.30
10.20
10.15
10.10
10.3
10.2
10.1
10.05
10.00
4.50
10.0
4.75
5.00
VDD1 (V)
5.25
5.50
-40 -25 -10
Figure 19.
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At VDD1 = VDD2 = 5V, VIN+ = –280mV to +280mV, VIN– = 0V, and sinc3 filter with OSR = 256, unless otherwise noted.
ANALOG SUPPLY CURRENT
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs TEMPERATURE
6.5
10.0
9.5
6.0
IDD2 (mA)
IDD1 (mA)
9.0
5.5
5.0
8.5
8.0
4.5
7.5
4.0
7.0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
-40 -25 -10
Figure 21.
12
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 22.
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GENERAL DESCRIPTION
The AMC1203 is a single-channel, 2nd-order, CMOS,
delta-sigma modulator, designed for medium- to
high-resolution A/D conversions from dc to 39kHz
with an oversampling ratio (OSR) of 256. The isolated
output of the converter (MDAT) provides a stream of
digital ones and zeros. The time average of this serial
output is proportional to the analog input voltage.
The modulator shifts the quantization noise to high
frequencies; therefore, a low-pass digital filter should
be used at the output of the device to increase the
overall performance. This filter is also used to convert
from the 1-bit data stream at a high sampling rate into
a higher-bit data word at a lower rate (decimation). A
digital signal processor (DSP), microcontroller (µC) or
field programmable gate array (FPGA) can be used
to implement the filter. Another option is using a
suitable application-specific device, such as the
AMC1210, a four-channel digital sinc-filter. Figure 23
shows two AMC1203s and one ADS1205
(dual-channel, non-isolated modulator) connected to
an AMC1210, building the entire analog front-end of a
resolver-based motor-control application. For detailed
information on the ADS1205 and AMC1210, please
visit our home page at www.ti.com.
The overall performance (speed and accuracy)
depends on the selection of an appropriate OSR and
filter type. A higher OSR results in higher accuracy
while operating at lower refresh rate. Alternatively, a
lower OSR results in lower accuracy, but provides
data at a higher refresh rate. This system allows
flexibility with the digital filter design and is capable of
A/D conversion results that have a dynamic range
exceeding 95dB with OSR = 256.
Resolver
Control Module
AMC1210
PWM1
Signal
Generator
PWM2
Filter Module 1
Comparator
Filter
IN1
ADS1205
CLK1
IN2
Sinc Filter/
Integrator
Input
Control
Filter
Module 2
CLK2
Current
Shunt
Resistor
IN3
AMC1203 CLK3
IN4
AMC1203
RST
INT
ACK
Time
Measurement
ADS1205
Current
Shunt
Resistor
CLK
Interrupt
Unit
CLK4
Register
Map
Interface
Module
Filter
Module 3
CS
ALE
RD
WR
M0
M1
AD0
AD7
Filter
Module 4
Figure 23. Example of a Resolver-Based Motor-Control Application
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THEORY OF OPERATION
The differential analog input of the AMC1203 is
implemented with a switched-capacitor circuit. This
switched-capacitor circuit implements a 2nd-order
modulator stage that digitizes the input signal into a
1-bit output stream. The internally-generated clock
signal (sourcing the capacitor circuit and the
modulator) is available as an output signal on the
MCLK pin. The analog input signal is continuously
sampled by the modulator and compared to an
internal voltage reference. A digital stream, accurately
representing the analog input voltage over time,
appears at the output of the converter.
ANALOG INPUT
The input design topology of the AMC1203 is based
on a fully-differential, switched-capacitor architecture
with a dynamic input impedance of 28kΩ at 10MHz,
as Figure 1 shows. This input stage provides the
mechanism to achieve low system noise, high
common-mode rejection (92dB), and excellent
power-supply rejection.
The input impedance becomes a consideration in
designs with high input-signal source impedance.
This high-impedance may cause degradation in gain,
linearity, and THD. The importance of this effect,
however, depends on the desired system
performance.
There are two restrictions on the analog input signals,
VIN+ and VIN–. If the input voltage exceeds the range
GND – 0.3V to VDD + 0.3V, the input current must be
limited to 10mA, because the input protection diodes
on the front end of the converter begin to turn on. In
addition, the linearity and the noise performance of
the device is ensured only when the differential
analog voltage resides within ±280mV.
MODULATOR
The modulator topology of the AMC1203 is
fundamentally a 2nd-order, switched-capacitor,
delta-sigma
modulator,
such
as
the
one
conceptualized in Figure 24. The analog input voltage
(X(t)) and the output of the 1-bit digital-to-analog
converter (DAC) are differentiated, providing an
analog voltage (X2) at the input of the first integrator
or modulator stage. The output of the first integrator
is further differentiated with the DAC output, and the
resulting voltage (X3) feeds the input of the second
integrator stage. When the value of the integrated
signal (X4) at the output of the second stage equals
the comparator reference voltage, the output of the
comparator switches from high to low, or vice versa,
depending on its previous state. In this case, the 1-bit
DAC responds on the next clock pulse by changing
its analog output voltage (X6), causing the integrators
to progress in the opposite direction, while forcing the
value of the integrator output to track the average of
the input.
fCLK
X(t)
X2
Integrator 1
X3
Integrator 2
X4
DATA
fS
VREF
Comparator
X6
DAC
Figure 24. Block Diagram of the 2nd-Order Modulator
14
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DIGITAL OUTPUT
0
The system clock of the AMC1203 is 20 MHz by
default, and is generated internally using an RC
circuit. The system clock is divided by two for the
modulator clock; thus, the default clock frequency of
the modulator is 10MHz. This clock is also available
on the output terminal MCLK, whereas the data are
provided at the MDAT output pin. The data are
changing at the falling edge of MCLK, so data can
safely be latched with the rising edge; see the Timing
Characteristics.
fDATA = 10MHz/32 = 312.5kHz
-3dB: 81.9kHz
OSR = 32
-10
-20
Gain (dB)
A differential input signal of 0V ideally produces a
stream of ones and zeros that are high 50% of the
time and low 50% of the time. A differential input of
+280mV produces a stream of ones and zeros that
are high 87.5% of the time. A differential input of
–280mV produces a stream of ones and zeros that
are high 12.5% of the time. The input voltage versus
the output modulator signal is shown in Figure 27.
-30
-40
-50
-60
-70
-80
0
400
600
800 1000
Frequency (kHz)
1200
1400
1600
Figure 25. Frequency Response of the Sinc3 Filter
30k
fMOD = 10MHz
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
Settling Time =
3 ´ 1/fDATA = 9.6ms
25k
Output Code
FILTER USAGE
The modulator generates a bit stream that is
processed by a digital filter to get a digital word
similar to the conversion result of a conventional
analog-to-digital converter (ADC). A very simple filter,
built with minimal effort and hardware, is a sinc3 filter:
200
20k
15k
10k
3
H(z) =
5k
1 - z-OSR
1 - z-1
(1)
This filter provides the best output performance at the
lowest hardware size (count of digital gates). For an
OSR in the range of 16 to 256, this filter is a good
choice. All the characterizations in this document are
also done with a sinc3 filter with OSR=256 and an
output word width of 16 bits.
3
In a sinc filter response (shown in Figure 25 and
Figure 26), the location of the first notch occurs at the
frequency of output data rate fDATA = fCLK/OSR. The
–3dB point is located at half the Nyquist frequency or
fDATA/4.
0
0
5
10
15
20
25
30
Number of Output Clocks
35
40
Figure 26. Pole Response of the Sinc3 Filter
Performance can be improved, for example, by using
a cascaded filter structure. The first decimation stage
could be built using a sinc3 filter with a low OSR and
the second stage using a high-order filter.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 27. Analog Input vs Modulator Output
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In motor-control applications, a very fast response
time for the over-current detection is required. The
time for full settling of the filter depends on its order
(that is, a sinc3 filter requires three data clocks for full
settling (with fDATA = fMOD/OSR). Therefore, for
over-current protection, filter types other than sinc3
might be a better choice; an alternative is the sinc2
filter. Figure 29 compares the settling times of
different filter orders (sincfast is a modified sinc2
filter):
16
sinc3
14
sincfast
12
ENOB (Bits)
The effective number of bits (ENOB) is often used to
compare the performance of ADCs and delta-sigma
modulators. Figure 28 shows the ENOB of the
AMC1203 with different oversampling ratios. In this
data sheet, this number is calculated from the SNR
using following formula:
SNR = 1.76dB + 6.02dB ´ ENOB
(2)
sinc2
10
8
6
sinc
4
2
0
1
10
100
1000
OSR
Figure 28. Measured Effective Number of Bits vs
Oversampling Ratio
2
1 - z-OSR
(1 + z-2OSR)
1 - z-1
10
(3)
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter
for Current Measurement in Motor Control
Applications, available for download at www.ti.com.
sinc3
9
8
sincfast
7
ENOB (Bits)
H(z) =
sinc2
6
5
4
sinc
3
2
1
0
0
1
2
3
4
5
6
Settling Time (ms)
7
8
9
10
Figure 29. Measured Effective Number of Bits vs
Settling Time
16
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APPLICATION INFORMATION
A typical operation of the AMC1203 in a motor-control
application is shown in Figure 30. Measurement of
the motor phase current is done via the shunt resistor
(RSHUNT; in this case, a 2-terminal shunt). For better
performance, the differential signal is filtered using
RC filters (components R2, R3 and C2). Optionally, C3
and C4 can be used to reduce charge dumping from
the inputs. In this case, care should be taken when
choosing the quality of these capacitors—mismatch in
values of these capacitors will lead to a
common-mode error at the input of the modulator.
The high-side power supply for the AMC1203 (VDD1)
is derived from the power supply of the upper gate
driver. For lowest cost, a Zener diode can be used to
limit the voltage to 5V ±10%. A decoupling capacitor
HV+
of 0.1µF is recommended for filtering this
power-supply path. This capacitor (C1 in Figure 30)
should be placed as close as possible to the VDD1 pin
for best performance. If better filtering is required, an
additional 1µF to 10µF capacitor can be used. The
floating ground reference (GND1) is derived from the
end of the shunt resistor, which is connected to the
negative input of the AMC1203 (VIN–). If a 4-terminal
shunt is used, the inputs of the AMC1203 are
connected to the inner leads, while GND1 is
connected to one of the outer leads of the shunt.
Both digital outputs, MCLK and MDAT, can be
directly connected to a digital filter (that is, the
AMC1210); see Figure 23.
Floating
Power Supply
Gated
Drive
Circuit
Isolation
Barrier
R1
AMC1203
D1
5.1V
R3
12W
RSHUNT
To Load
Power
Supply
Gated
Drive
Circuit
VDD1
VDD2
VIN+
MDAT
VIN-
MCLK
GND1
GND2
C1(1)
0.1mF
R2
12W
C2
330pF
C3
10pF
(optional)
C4
10pF
(optional)
NOTE: (1) Place C1 close to AMC1203.
HV-
Figure 30. Typical Application Diagram
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SBAS427 – FEBRUARY 2008
ISOLATION GLOSSARY
Creepage Distance: The shortest path between two
conductive input to output leads measured along the
surface of the insulation. The shortest distance path
is found around the end of the package body.
the leakage current produces an overvoltage at the
site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization
on insulation material and lead to a carbon track
between points of different potential. This process is
known as tracking.
Insulation:
Operational insulation—Insulation needed for the
correct operation of the equipment.
Clearance: The shortest distance between two
conductive input to output leads measured through air
(line of sight).
Basic insulation—Insulation to
protection against electric shock.
provide
basic
Supplementary insulation—Independent insulation
applied in addition to basic insulation in order to
ensure protection against electric shock in the event
of a failure of the basic insulation.
Double insulation—Insulation comprising both basic
and supplementary insulation.
Reinforced insulation—A single insulation system that
provides a degree of protection against electric shock
equivalent to double insulation.
Input-to Output Barrier Capacitance: The total
capacitance between all input terminals connected
together, and all output terminals connected together.
Input-to Output Barrier Resistance: The total
resistance between all input terminals connected
together, and all output terminals connected together.
Primary Circuit: An internal circuit directly connected
to an external supply mains or other equivalent
source that supplies the primary circuit electric power.
Secondary Circuit: A circuit with no direct
connection to primary power that derives its power
from a separate isolated source.
Comparative Tracking Index (CTI): CTI is an index
used for electrical insulating materials. It is defined as
the numerical value of the voltage that causes failure
by tracking during standard testing. Tracking is the
process that produces a partially conducting path of
localized deterioration on or through the surface of an
insulating material as a result of the action of electric
discharges on or close to an insulation surface. The
higher CTI value of the insulating material, the
smaller the minimum creepage distance.
Generally, insulation breakdown occurs either
through the material, over its surface, or both.
Surface failure may arise from flashover or from the
progressive degradation of the insulation surface by
small localized sparks. Such sparks are the result of
the breaking of a surface film of conducting
contaminant on the insulation. The resulting break in
18
Pollution Degree:
Pollution Degree 1—No pollution, or only dry,
nonconductive pollution occurs. The pollution has no
influence on device performance.
Pollution Degree 2—Normally, only nonconductive
pollution occurs. However, a temporary conductivity
caused by condensation is to be expected.
Pollution Degree 3—Conductive pollution, or dry
nonconductive pollution that becomes conductive
because of condensation, occurs. Condensation is to
be expected.
Pollution Degree 4 – Continuous conductivity occurs
as a result of conductive dust, rain, or other wet
conditions.
Installation Category:
Overvoltage Category—This section is directed at
insulation coordination by identifying the transient
overvoltages that may occur, and by assigning four
different levels as indicated in IEC 60664.
I: Signal Level: Special equipment or parts of
equipment.
II: Local Level: Portable equipment, etc.
III: Distribution Level: Fixed installation.
IV: Primary Supply Level: Overhead lines, cable
systems.
Each category should be subject to smaller transients
than the previous category.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
AMC1203BDUB
ACTIVE
SOP
DUB
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203BDUBG4
ACTIVE
SOP
DUB
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203BDUBR
ACTIVE
SOP
DUB
8
700
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203BDUBRG4
ACTIVE
SOP
DUB
8
700
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203DUB
ACTIVE
SOP
DUB
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203DUBG4
ACTIVE
SOP
DUB
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203DUBR
ACTIVE
SOP
DUB
8
700
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
AMC1203DUBRG4
ACTIVE
SOP
DUB
8
700
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AMC1203BDUBR
SOP
DUB
8
700
330.0
24.4
10.9
10.01
5.85
16.0
24.0
Q1
AMC1203DUBR
SOP
DUB
8
700
330.0
24.4
10.9
10.01
5.85
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1203BDUBR
SOP
DUB
8
700
358.0
335.0
35.0
AMC1203DUBR
SOP
DUB
8
700
358.0
335.0
35.0
Pack Materials-Page 2
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