Sony CXD2931R-9 1 chip gps lsi Datasheet

CXD2931R-9/GA-9
1 chip GPS LSI
Description
The CXD2931R-9/GA-9 is a dedicated LSI for the
GPS (Global Positioning System) satellite-based
position measurement system.
This LSI contains a 32-bit RISC CPU, 2M-bit MASK
ROM, RAM, UART, timer, and others.
This LSI, used together with the RF LSI (CXA1951AQ),
enables the configuration of a 2-chip system capable
of measuring its position anywhere on the globe.
Features
• 16-channel GPS receiver capable of
simultaneously receiving 16 satellites
• Supports differential GPS
— Comforms to RTCM SC-104 Ver. 2.1
— Supports DARC
• All-in-view measurement
• 2-satellite measurement
• Timer supporting GPS time
• High performance 32-bit RISC CPU
• 256K-byte program ROM
• 36K-byte RAM
• 3-channel UART
— Baud rate generator
— Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and
38.4K baud
— Supports 1/2/4-byte buffer mode
• 23-bit general-purpose I/O port capable of defining
input/output independently for each bit
• 8-bit successive approximation system A/D
converter
CXD2931R-9
144 pin LQFP (Plastic)
CXD2931GA-9
144 pin LFLGA (Plastic)
Absolute Maximum Ratings
• Supply voltage
VDD
VSS – 0.5 to 4.6
• Input voltage
VI
VSS – 0.5 to VDD + 0.5
• Output voltage
VO VSS – 0.5 to VDD + 0.5
• Operating temperature
Topr
–40 to +85
• Storage temperature
Tstg
–50 to +150
V
V
V
°C
°C
Recommended Operating Conditions
3.0 to 3.6
• Supply voltage
VDD
• Operating temperature
Topr
–40 to +85
°C
Input/Output Pin Capacitance
• Input capacitance
CIN
9 (Max.)
• Output capacitance COUT
11 (Max.)
• I/O capacitance
CI/O
11 (Max.)
pF
pF
pF
V
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01Z12A22-PS
CXD2931R-9/GA-9
Performance
• 16-channel GPS receiver
• High performance 32-bit RISC CPU
• Receiver frequency: 1575.42MHz (L1 band, CA code)
• Reception sensitivity
Tracking sensitivity: –145dBm (typ.) when using the antenna of 25dBi, NF = 2dB and the RF amplifier
with the 25dB gain
∗ Reference data using the Sony's reference board.
This value is not guaranteed, depending on the conditions.
• Time to First Fix (time until initial measurement after power-on)
Cold Start (without both ephemeris and almanac): 27 to 58s
Warm Start (without ephemeris with almanac):
23 to 45s
Hot Start (with both ephemeris and almanac):
6 to 17s
∗ Reference data with elevation angle of 5° or more and no interception environment on Nov., 2001.
Positioning time with 90% possibility.
These values are not guaranteed, depending on the conditions.
• Positioning accuracy
2DRMS: approx. 12m
∗ Reference data with elevation angle of 5° or more and no interception environment.
This value is not guaranteed, depending on the conditions.
• Measurement data update time
1s
• Interfece format
NMEA0183 (4800bps)
• Communication method
Start-stop synchronization
• All-in-view
1575.42MHz
LNA
CXA1951AQ
RF Converter
18.414MHz
IF
1.023MHz
TCXO
TXD
CXD2931R-9
16ch GPS Processor
RXD
GPS receiver system block diagram using the CXD2931R-9
–2–
CXD2931R-9/GA-9
PORT (0:15)
DWR
DRD
DB (0:7)
DADR (0:15)
DCS0 to DCS5/PORT (16:21)
XCS0
IWR
IRD
IB (0:15)
IADR (1:18)
ICS0, 1
Block Diagram
TEST0, 1
ICST0, 1
BIU
RUN
XROMW
HOLD
CLKS
NMI
CLKI
PMI
32-bit RISC
IODBK
CLKO
CLKOUT
HOLDA
TCXOS
SINT/PORT (22)
EXRS
256K-byte ROM
PWRST
36K-byte SRAM
VDD × 10
VSS × 10
TXD0 to TXD2
UART (Baud Rate Generator) × 3
RXD0 to RXD2
TIMER × 3
AVD
8-bit
ADC
16ch GPS DSP
AVS
VRT
–3–
AVIN
IF0
IF0O
CCKI
CCKO
OTCXO
TCXO
XTCXO
VRB
CXD2931R-9/GA-9
IB9
IB10
VDD
IB11
IB12
IB13
IB14
IB15
DRD
DWR
XCS0
DADR0
DADR1
VSS
DADR2
DADR3
DADR4
DADR5
DADR6
DADR7
DADR8
DADR9
VDD
DADR10
DADR11
DADR12
DADR13
DADR14
DADR15
DB0
DB1
VSS
DB2
DB3
DB4
DB5
Pin Configuration (CXD2931R-9)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
DB6 109
72 IB8
DB7 110
71 IB7
SINT/PORT22 111
70 VSS
DCS0/PORT21 112
69 IB6
VDD 113
68 IB5
DCS1/PORT20 114
67 IB4
DCS2/PORT19 115
66 IB3
DCS3/PORT18 116
65 IB2
DCS4/PORT17 117
64 IB1
DCS5/PORT16 118
63 VDD
PORT15 119
62 IB0
PORT14 120
61 IADR18
VSS 121
60 IADR17
PORT13 122
59 IADR16
PORT12 123
58 IADR15
PORT11 124
57 IADR14
PORT10 125
56 IADR13
PORT9 126
55 VSS
PORT8 127
54 IADR12
PORT7 128
53 IADR11
52 IADR10
VDD 129
PORT6 130
51 IADR9
PORT5 131
50 IADR8
PORT4 132
49 IADR7
PORT3 133
48 IADR6
PORT2 134
47 VDD
PORT1 135
46 IADR5
PORT0 136
45 IADR4
VSS 137
44 IADR3
TXD2 138
43 IADR2
RXD2 139
42 IADR1
TXD1 140
41 XROMW
RXD1 141
40 ICS1
TXD0 142
39 VSS
RXD0 143
38 ICS0
37 IRD
IWR
RUN
VDD
CLKOUT
CLKS
CLKO
CLKI
VSS
PWRST
EXRS
IODBK
VDD
HOLDA
XTCXO
PMI
TCXO
NMI
VSS
HOLD
AVS
VDD
VRB
TCXOS
VRT
–4–
IF0O
AVD
IF0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ICST1
8
ICST0
7
VSS
6
CCKO
5
CCKI
4
TEST1
3
TEST0
2
OTCXO
1
AVIN
VDD 144
CXD2931R-9/GA-9
Pin Configuration (CXD2931GA-9)
70
67
64
62
VSS
IB4
IB1
IB0
59
58
IADR16 IADR15
75
71
68
66
63
VDD
IB7
IB5
IB3
VDD
60
55
VSS
56
54
51
IADR12 IADR9
53
49
IADR17 IADR13 IADR11 IADR7
50
47
45
42
39
34
IADR8
VDD
IADR4
IADR1
VSS
VDD
43
41
46
IADR5
IADR2 XROMW
38
35
31
ICS0
RUN
CLKO
32
28
78
74
72
69
65
IB13
IB10
IB8
IB6
IB2
81
77
73
33
30
26
DRD
IB12
IB9
CLKOUT
CLKI
IODBK
61
57
52
48
IADR18 IADR14 IADR10 IADR6
44
40
37
36
IADR3
ICS1
IRD
IWR
83
79
76
29
27
23
IB14
IB11
VSS
EXRS
NMI
86
82
80
25
24
22
VSS
DWR
IB15
HOLDA
PMI
HOLD
87
85
84
90
89
88
DADR5 DADR4 DADR3
91
92
93
DADR6 DADR7 DADR8
94
96
97
DADR9 DADR10 DADR11
95
VDD
99
21
20
19
VDD
TCXOS
IF0O
16
17
18
ICST0
ICST1
IF0
12
13
15
TEST1
CCKI
VSS
8
10
14
101
DADR13 DADR15
4
7
11
VRB
TCXO
TEST0
98
102
105
1
5
9
DB0
DB2
AVD
AVS
VDD
100
104
108
109
DADR14
VSS
DB5
DB6
103
107
110
113
106
DB3
15
DB4
DB7
VDD
111
114
117
112
116
120
124
DCS0/
DCS3/ PORT14 PORT11
PORT21 PORT18
115
118
DCS2/
DCS5/
PORT19 PORT16
119
122
121
VSS
123
125
129
133
137
141
144
2
6
VDD
PORT3
VSS
RXD1
VDD
AVIN
VSS
128
132
135
138
140
143
3
TXD2
TXD1
RXD0
VRT
134
136
PORT10 PORT7 PORT4 PORT1
126
127
130
131
SINT/
DCS1/
DCS4/
PORT15 PORT13 PORT12 PORT9 PORT8 PORT6 PORT5 PORT2 PORT0
PORT22 PORT20 PORT17
14
13
N
M
L
K
J
H
G
F
XTCXO OTCXO CCKO
DADR12
DB1
P
CLKS PWRST
XCS0
DADR2 DADR1 DADR0
R
12
11
10
9
8
–5–
7
6
5
4
3
139
142
RXD2
TXD0
2
1
E
D
C
B
A
CXD2931R-9/GA-9
Pin Configuration
Pin
No.
Symbol
I/O
Description
1
AVD
—
2
AVIN
I
3
VRT
I
4
VRB
I
5
AVS
—
A/D converter GND.
6
Vss
—
GND
7
TCXO
I
8
XTCXO
O
9
VDD
—
Power supply.
10
OTCXO
O
TCXO clock output.
11
TEST0
I
12
TEST1
I
13
CCKI
I
14
CCKO
O
15
Vss
—
16
ICST0
I
17
ICST1
I
18
IF0
I
19
IF0O
O
20
TCXOS
I
21
VDD
22
HOLD
I
Hold input signal. (High: Hold)
23
NMI
I
Non maskable interrupt.
24
PMI
I
Program maskable interrupt.
25
HOLDA
O
Hold acknowledge signal.
26
IODBK
O
Break signal for debugging.
27
EXRS
I
Reset input signal.
28
PWRST
I
Connect to main power supply. Leave open during backup.
29
Vss
—
30
CLKI
I
31
CLKO
O
32
CLKS
I
CPU clock select signal. (Low: TCXO, High: CLKI)
33
CLKOUT
O
CPU clock output.
34
VDD
—
Power supply.
35
RUN
O
Signal indicating CPU operating status.
36
IWR
O
Write signal for external expansion memory.
37
IRD
O
Read signal for external expansion memory.
—
A/D converter power supply.
Analog input.
Reference input.
TCXO binary conversion circuit/crystal oscillator.
Test. (Low level fixed)
Timer oscillation. (32.768kHz ± 100ppm)
GND
Test. (Low level fixed)
IF signal binary conversion circuit.
TCXO select. (Low: TCXO/2, High: TCXO through)
Power supply.
GND
CPU clock oscillation circuit.
–6–
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
38
ICS0
O
Chip select 0 for external expansion memory.
39
Vss
—
GND
40
ICS1
O
Chip select 1 for external expansion memory.
41
XROMW
I
Wait signal for external expansion memory. (High: Wait)
42
IADR1
I/O
43
IADR2
I/O
44
IADR3
I/O
45
IADR4
I/O
46
IADR5
I/O
47
VDD
—
48
IADR6
I/O
49
IADR7
I/O
50
IADR8
I/O
51
IADR9
I/O
52
IADR10
I/O
53
IADR11
I/O
54
IADR12
I/O
55
Vss
—
56
IADR13
I/O
57
IADR14
I/O
58
IADR15
I/O
59
IADR16
I/O
60
IADR17
I/O
61
IADR18
I/O
(MSB)
62
IB0
I/O
(LSB) Data bus I/O for external expansion memory.
63
VDD
—
Power supply.
64
IB1
I/O
65
IB2
I/O
66
IB3
I/O
67
IB4
I/O
68
IB5
I/O
69
IB6
I/O
70
Vss
—
71
IB7
I/O
72
IB8
I/O
73
IB9
I/O
74
IB10
I/O
(LSB)
Address signal for external expansion memory.
Power supply.
Address signal for external expansion memory.
GND
Address signal for external expansion memory.
Data bus I/O for external expansion memory.
GND
Data bus I/O for external expansion memory.
–7–
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
75
VDD
—
76
IB11
I/O
77
IB12
I/O
78
IB13
I/O
79
IB14
I/O
80
IB15
I/O
(MSB)
81
DRD
O
Read signal for external expansion data memory.
82
DWR
O
Write signal for external expansion data memory.
83
XCS0
O
Chip select signal for external expansion data memory.
84
DADR0
I/O
85
DADR1
I/O
(LSB)
Address signal for external expansion data memory.
86
Vss
—
GND
87
DADR2
I/O
88
DADR3
I/O
89
DADR4
I/O
90
DADR5
I/O
91
DADR6
I/O
92
DADR7
I/O
93
DADR8
I/O
94
DADR9
I/O
95
VDD
—
96
DADR10
I/O
97
DADR11
I/O
98
DADR12
I/O
99
DADR13
I/O
100
DADR14
I/O
101
DADR15
I/O
(MSB)
102
DB0
I/O
103
DB1
I/O
(LSB)
Data bus I/O for external expansion data memory.
104
Vss
—
GND
105
DB2
I/O
106
DB3
I/O
107
DB4
I/O
108
DB5
I/O
109
DB6
I/O
110
DB7
I/O
Power supply.
Data bus I/O for external expansion memory.
Address signal for external expansion data memory.
Power supply.
Address signal for external expansion data memory.
Data bus I/O for external expansion data memory.
(MSB)
–8–
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
111
SINT/PORT22
I/O
External interrupt input signal/general-purpose I/O port.
This pin can be used as a general-purpose I/O port according to the internal
registers.
112
DCS0/PORT21
I/O
Chip select for external expansion data memory/general-purpose I/O port.
This pin can be used as a general-purpose I/O port according to the internal
registers.
113
VDD
—
Power supply.
114
DCS1/PORT20
I/O
115
DCS2/PORT19
I/O
116
DCS3/PORT18
I/O
117
DCS4/PORT17
I/O
118
DCS5/PORT16
I/O
119
PORT15
I/O
120
PORT14
I/O
121
Vss
—
122
PORT13
I/O
123
PORT12
I/O
124
PORT11
I/O
125
PORT10
I/O
126
PORT9
I/O
127
PORT8
I/O
128
PORT7
I/O
129
VDD
—
130
PORT6
I/O
131
PORT5
I/O
132
PORT4
I/O
133
PORT3
I/O
134
PORT2
I/O
135
PORT1
I/O
136
PORT0
I/O
137
Vss
—
GND
138
TXD2
O
UART transmission data output. (channel 2)
139
RXD2
I
UART reception data input. (channel 2)
140
TXD1
O
UART transmission data output. (channel 1)
141
RXD1
I
UART reception data input. (channel 1)
142
TXD0
O
UART transmission data output. (channel 0)
143
RXD0
I
UART reception data input. (channel 0)
144
VDD
—
Chip select for external expansion data memory/general-purpose I/O port.
These pins can be used as a general-purpose I/O port according to the
internal registers.
General-purpose I/O port.
GND
General-purpose I/O port.
Power supply.
General-purpose I/O port.
Power supply.
–9–
CXD2931R-9/GA-9
A/D Converter Characteristics
Item
(0 < VRB < VIN < VRT < AVD = 3.0 to 3.6V, Topr = –40 to +85°C)
Pin
Condition
Min.
Typ.
Max.
Unit
8
Bit
–0.5
+0.5
LSB
–2.5
+2.5
LSB
Resolution
Differential linearity error (DLE)
Integral linearity error (ILE)
Sampling time
AVD = 3.0V
f = 18.414MHz
Conversion time
Current consumption
648
ns
864
ns
2.0
AVD = 3.0V
mA
Electrical Characteristics
DC Characteristics
(VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
Item
Symbol
Condition
High level
VIH (1)
Low level
VIL (1)
Input voltage (2)
(5V interface)
High level
VIH (2)
Low level
VIL (2)
High level
VOH (1)
IOH = –4.0mA
Low level
VOL (1)
IOL = 4.0mA
High level
VOH (2)
IOH = –2.0mA
Low level
VOL (2)
IOL = 4.0mA
High level
VOH (3)
IOH = –2.0mA
Low level
VOL (3)
IOL = 8.0mA
Output voltage (2)
Output voltage (3)
Current consumption in standby mode
ISTB
(Using external timer, +85°C)
Supply current
IDD
Typ.
0.7 × VDD
Input voltage (1)
(CMOS level)
Output voltage (1)
Min.
0.7 × VDD
Max.
Unit Applicable
Pins
VDD
V
0.2 × VDD
V
5.5
V
0.2 × VDD
V
VDD – 0.4
V
0.4
VDD – 0.8
VDD – 0.8
VDD = 3.0V
20
70
VDD = 1.8V
4
50
f = 18.414MHz
55
∗3
∗4
V
V
0.4
∗2
V
V
0.4
∗1
∗5
V
µA
—
mA
—
Applicable pins
∗1 Pins 11, 12, 16, 17, 20, 28, 32, 41
∗2 Pins 22 to 24, 27, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120,
122, 128, 130 to 136, 139, 141, 143
∗3 Pins 10, 25, 26, 33, 35
∗4 Pins 38, 40, 82, 83, 138, 140, 142
∗5 Pins 36, 37, 42 to 46, 48 to 54, 56 to 62, 64 to 69, 71 to 74, 76 to 81, 84, 85, 87 to 94, 96 to 103,
105 to 112, 114 to 120, 122 to 128, 130 to 136
– 10 –
CXD2931R-9/GA-9
Battery Backup Mode
The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset
goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock
are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and
the registers are initialized.
Battery backup mode is canceled by setting power-on reset to high.
10 clocks
Power-on reset
EXRS
PWRST
100ms or more
Timer clocks
CCKI, CCKO
Other clocks
TCXO, XTCXO, CLKI, CLKO
Normal outputs
TXD0 to 2, OTCXO, HOLDA
Fixed low
Tri-state outputs
IODBK, RUN, CLKOUT
Fixed low
Tri-state outputs
ICS0, ICS1, IADR[18:1],
IRD, IWR, DRD, DWR, XCS0
Hi-Z
Fixed low
Bidirectional
(Input)
SINT, IB[15:0], DCS0 to DCS5,
DADR[15:0], DB[7:0], PORT[22:0] (Outut)
Hi-Z
Inputs
RXD0 to RXD2, IF0,
HOLD, NMI, PMI
Fixed low
– 11 –
CXD2931R-9/GA-9
CXD2931R-9/GA-9 Initialization
CXD2931R-9/GA-9 initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The
timing should satisfy the conditions noted below.
1. During power-on (power-on reset) (VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
VDD
VDD [V]
Power supply,
PWRST
(Pin 28)
EXRS (Pin 27)
100ms or more
VDD/2
GND
The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal
should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST
signal should be left open during battery backup.
2. Initialization during operation (VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
Power supply,
PWRST
(Pin 28)
VDD
EXRS (Pin 27)
VDD [V]
100µs or more
VDD/2
GND
The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for
100µs or more. Keep the PWRST (Pin 28) signal at high level at this time.
– 12 –
CXD2931R-9/GA-9
• External Command Fetch Timing (XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
ICS0, ICS1
(e)
(f)
IRD
(g)
(16)
IB
No.
(h)
Item
Min.
Typ.
Max.
Unit
(a)
Read cycle time (Fex: @20MHz)
—
100
—
ns
(b)
Address delay time
—
—
12
ns
(c)
Chip select fall delay time
2
—
10
ns
(d)
Chip select rise delay time
2
—
10
ns
(e)
Read signal fall delay time
0
—
3
ns
(f)
Read signal rise delay time
0
—
5
ns
(g)
Read data setup time
11
—
—
ns
(h)
Read data hold time
0
—
—
ns
∗ The load capacitance = 30pF.
• External Command Fetch Timing (XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
(16)
IB
– 13 –
CXD2931R-9/GA-9
• External Data Access Timing (ICS0, ICS1/XROMW = 0)
(1) Read (half-word access/XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
(e)
(f)
ICS0, ICS1
IRD
(g)
(h)
(16)
IB
(2) Write (half-word access/XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
(i)
(j)
ICS0, ICS1
IWR
(k)
(16)
IB
No.
(l)
Item
Min.
Typ.
Max.
Unit
(a)
Read/write cycle time (Fex: @20MHz)
—
100
—
ns
(b)
Address delay time
—
—
12
ns
(c)
Chip select fall delay time
2
—
10
ns
(d)
Chip select rise delay time
2
—
10
ns
(e)
Read signal fall delay time
0
—
3
ns
(f)
Read signal rise delay time
0
—
5
ns
(g)
Read data setup time
11
—
—
ns
(h)
Read data hold time
0
—
—
ns
(i)
Write signal fall delay time
0
—
1
ns
(j)
Write signal rise delay time
0
—
2
ns
(k)
Write data established time
—
—
5
ns
(l)
Write data hold time
5
—
—
ns
– 14 –
∗ The load capacitance = 30pF.
CXD2931R-9/GA-9
(3) Read (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
H (16)
L (16)
(4) Write (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IWR
IB
L (16)
– 15 –
H (16)
CXD2931R-9/GA-9
• External Data Access Timing (ICS0, ICS1/XROMW = 1)
(1) Read (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
(16)
IB
(2) Write (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR
(16)
IB
(3) Read (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
H (16)
L (16)
(4) Write (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR
IB
L (16)
– 16 –
H (16)
CXD2931R-9/GA-9
• External Data Access Timing (XCS0, DCS0 to DCS5/no data wait)
(1) Read (byte access/no data wait)
CLKOUT
(a)
(b)
DADR
(c)
(d)
XCS0, DCS0 to DCS5
(e)
(f)
DRD
(h)
(g)
DB
(8)
(2) Write (byte access/no data wait)
CLKOUT
(a)
(b)
DADR
(c)
(d)
XCS0, DCS0 to DCS5
(i)
(j)
DWR
(l)
(k)
(8)
DB
No.
Item
Min.
Typ.
Max.
Unit
(a)
Read/write cycle time (Fex: @20MHz)
—
100
—
ns
(b)
Address delay time
—
—
12
ns
(c)
Chip select fall delay time
3
—
13
ns
(d)
Chip select rise delay time
3
—
13
ns
(e)
Read signal fall delay time
2
—
8
ns
(f)
Read signal rise delay time
2
—
10
ns
(g)
Read data setup time
16
—
—
ns
(h)
Read data hold time
0
—
—
ns
(i)
Write signal fall delay time
0
—
2
ns
(j)
Write signal rise delay time
0
—
3
ns
(k)
Write data established time
—
—
12
ns
(l)
Write data hold time
5
—
—
ns
– 17 –
∗ The load capacitance = 30pF.
CXD2931R-9/GA-9
(3) Read (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
H (8)
L (8)
H (8)
(4) Write (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
(5) Read (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
HH (8)
HL (8)
LH (8)
LL (8)
LL (8)
LH (8)
HL (8)
HH (8)
(6) Write (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
– 18 –
CXD2931R-9/GA-9
• External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 1)
(1) Read (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
(8)
DB
(2) Write (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
(8)
DB
(3) Read (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
L (8)
L (8)
H (8)
(4) Write (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
– 19 –
CXD2931R-9/GA-9
(5) Read (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
HH (8)
HL (8)
LH (8)
LL (8)
LL (8)
LH (8)
HL (8)
HH (8)
(6) Write (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
• External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 2)
(1) Read (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
(8)
DB
(2) Write (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
(8)
DB
– 20 –
CXD2931R-9/GA-9
(3) Read (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
L (8)
L (8)
H (8)
(4) Write (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
(5) Read (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
HH (16)
HL (16)
LH (16)
LL (16)
LL (16)
LH (16)
HL (16)
HH (16)
(6) Write (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
– 21 –
CXD2931R-9/GA-9
Application Notes
The constants shown in the circuits below are the examples, and do not quarantee the circuit operation.
1. TCXO input
(1) When inputting the binary-converted signal
The TCXO (Pin 7) input signal should be 18.414MHz ± 3ppm.
7
Input
Open 8
(2) When performing the self-oscillation with the TCXO and XTCXO pins (Pins 7 and 8)
The TCXO (Pin 7) input signal should be 18.414MHz ± 3ppm.
0.01µF
7
TCXO
1MΩ
8
2. CPU clock generation
Pin 32 is used to select that TCXO is used or that the self-oscillation is performed with the MCKI and
MCKO pins (Pins 30 and 31).
(1) TCXO solution (TCXO is used for CPU clock)
Set Pin 32 to low.
Pin 30: Low
Pin 31: Open
(2) When performing the self-oscillation with the MCKI and MCKO pins (Pins 30 and 31)
Set Pin 32 to high.
The crystal frequency should be less than 20MHz.
The following circuit is just a reference, and is not guaranteed.
20pF
30
20MHz max.
10MΩ
31
20pF
– 22 –
CXD2931R-9/GA-9
(3) Using internal clock
Set PORT5 (Pin 131) to high.
Connect the external parts as follows when performing the self-oscillation with the CCKI and CCKO pins
(Pins 13 and 14).
220pF
13
32.768kHz
±100ppm
10MΩ
14
220pF
(4) Input IF signal
0.01µF
18
1MΩ
19
– 23 –
CXD2931R-9/GA-9
Description of Application Circuit
See the Application Circuit when using the CXD2931R-9/GA-9 to configure a GPS receiver.
Points for caution are as follows.
1. Unused pins
Software processing is performed to prevent undesired current from flowing to unused pins in the circuit
diagram, so leave these pins open.
2. TCXO input
The TCXO frequency is 18.414MHz ± 3ppm. Signals that have not been binary-converted should be input
via a DC filter capacitor (C19 in the circuit diagram). Input binary-converted signals directly to Pin 7 (TCXO)
without passing through C19 or R1 in the circuit diagram.
Make sure the input level at this time satisfies the Electrical Characteristics.
3. IF input
The CXD2931R-9/GA-9 interface is 1.023MHz, and does not accept other frequencies. Signals that have
not been binary-converted should be input via a DC filter capacitor (C20). Input binary-converted signals
directly to Pin 18 (IF0) without passing through C20 or R3 in the circuit diagram.
Make sure the input level at this time satisfies the Electrical Characteristics.
4. TXD (SIO output)
The TXD amplitude low level is 0.4V or less, and the high level is VDD – 0.4V (VDD = 3.0 to 3.6V) or more.
When the LSI, etc., connected to TXD operates at 5V and has a CMOS input level, perform 3 to 5V
conversion before inputting the signal.
5. Real-time clock
The current software version uses an external real-time clock. Consult your Sony representative
beforehand when using the internal real-time clock. When using an external real-time clock, connect Pin 13
(CCKI) to GND.
– 24 –
2
3
4
5
6
7
TXD
RXD
TCXO (18.414MHz)
IF (1.023MHz)
RESET
GND
IF
RESET
TCXO
VSS
VDD
C11
3.3
D2
RB400D-T146
∗ Input 3.6V in consideration of voltage step-down by diode (D2).
1
CN1
3.6V∗
RXD0
TXD0
VDD
1
BT1
3.0V
2
D1
RB400D-T146
3
4
5
NC
VOUT
NC
VIN
C13
0.1
X1
5
32.768k
C6
6
10p
7
C9
8
10p
VSS 4
CE 1
C10
0.1
C2
0.1
IB13
IB14
IB15
DRD
DWR
EXRS
XCS0
IODBK
DADR0
HOLDA
DADR1
PMI
VSS
NMI
DADR2
HOLD
DADR7
DADR9
VSS
DADR8
VDD
CCKO
DADR14
DB0
TCXO
DADR15
DB1
VSS
VSS
AVS
DB2
VRB
IB7 71
125 PORT10
2
1
143 RXD0
144 VDD
142 TXD0
141 RXD1
140 TXD1
139 RXD2
138 TXD2
137 VSS
136 PORT0
135 PORT1
134 PORT2
133 PORT3
132 PORT4
131 PORT5
130 PORT6
129 VDD
128 PORT7
127 PORT8
VRT
3
C19
0.01
C14
0.1
ICS0 38
IRD 37
VSS 39
ICS1 40
XROMW 41
IADR1 42
IADR2 43
IADR3 44
IADR4 45
IADR5 46
VDD 47
IADR6 48
IADR7 49
IADR8 50
IADR9 51
IADR10 52
IADR11 53
IADR12 54
When using the internal timer
C15 C16
220p 220p
R2
10M
X2
32.768k
C20
0.01
R3 1M
C17
0.1
C18
0.1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
R1
1M
8
IADR14 57
IADR13 56
124 PORT11
7
IADR15 58
123 PORT12
6
IADR16 59
122 PORT13
5
IADR17 60
121 VSS
4
IADR18 61
120 PORT14
VSS 55
IB0 62
119 PORT15
126 PORT9
IB1 64
ICST0
VDD 63
ICST1
118 DCS5/PORT16
IF0
117 DCS4/PORT17
IB2 65
IB3 66
116 DCS3/PORT18
IB4 67
115 DCS2/PORT19
XTCXO
114 DCS1/PORT20
VDD
DB3
IB5 68
PWRST
IB6 69
VSS
113 VDD
CLKI
112 DCS0/PORT21
CLKO
IB8 72
VDD
VSS
VDD
VSS
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
VDD
OSCI SCL 2
OSCO SIO 3
INT
IC2
RS5C313
When using an external timer
C5
0.1
DADR6
IC1
CXD2931R-9/GA-9
IB12
CLKS
VSS 70
CLKOUT
111 SINT/PORT22
DADR13
OTCXO
109 DB6
110 DB7
IB11
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
C1
0.1
DADR5
IF0O
C3
0.1
VDD
DADR12
TEST0
DB5
AVD
GND
VSS
47k 47k
VDD
VDD
47k
47k
VSS
47k 47k 47k 47k
DADR11
TEST1
IB9
VSS
DADR10
CCKI
DB4
AVIN
IC3
5812185G
VSS
DADR4
TCXOS
Note) Set PORT5 to low when using an external timer, and
set PORT5 to high when using an internal timer.
VDD
DADR3
VDD
Recommended components
IC1:
CXD2931R-9/GA-9
IC2:
Real-time clock
Made by RICOH (RS5C313)
IC3:
Voltage regulator (for step-down transformation)
Made by SEIKO INSTRUMENTS (S81218SG,
steps down 3V to 1.8V)
TCXO: Made by Tokyo Denpa
Oscillator frequency: 18.414MHz ± 3ppm
VDD
IB10
RUN
– 25 –
IWR
Application Circuit
C7
0.1
C4
0.1
CXD2931R-9/GA-9
CXD2931R-9/GA-9
Package Outline
Unit: mm
CXD2931R-9
144PIN LQFP (PLASTIC)
22.0 ± 0.2
1.7 MAX
1.4 ± 0.1
20.0 ± 0.1
73
108
109
72
B
A
37
144
1
36
0.5
b
0.08 M
0.1
S
S
S
DETAIL A
0.5 ± 0.15
0˚ to 10˚
b = 0.20 ± 0.03
0.125 ± 0.04
(21.0)
0.1 ± 0.05
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-144P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
LQFP144-P-2020
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
1.3 g
JEDEC CODE
– 26 –
CXD2931R-9/GA-9
Package Outline
Unit: mm
CXD2931GA-9
144PIN LFLGA
0.2
S A
0.10 S
13.0
1.4MAX
X
PIN 1 INDEX
0.2
S B
0.20 S
13.0
0.01
x4
0.15
S
A
0.55
DETAIL X
144 – φ0.40 ± 0.05
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
φ0.08 M S A B
0.8
B
1 2 3 4 5 6 7 8 9 101112131415
0.5
0.55
0.8
0.9
0.9
0.55
0.5
0.55
3 – φ0.50
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
EIAJ CODE
LFLGA-144P-01
P-LFLGA144-13x13-0.8
TERMINAL TREATMENT
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 27 –
ORGANIC SUBSTRATE
NICKEL & GOLD PLATING
COPPER
0.5g
Sony Corporation
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