LINER LT3694-1EFEPBF 36v, 2.6a monolithic buck regulator with dual ldo Datasheet

LT3694/LT3694-1
36V, 2.6A Monolithic Buck
Regulator With Dual LDO
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
Wide Input Range: 4V to 36V
Overvoltage Shutdown Protects Circuit Through
70V Transients
2.6A Output Switching Regulator with Internal
Power Switch
Dual, Low Dropout, Linear Regulator Controllers
with Programmable Current Limit
Tracking/Soft-Start Inputs and Power Good Output
Simplify Soft-Start and Supply Sequencing
Uses Small Inductors and Ceramic Capacitors
VOUT(MIN) = 0.75V (Buck and LDOs)
Adjustable 250kHz to 2.5MHz Switching Frequency
Accurate Enable Threshold Allows User
Programmable Undervoltage Lockout
Options for Clock Synchronization (LT3694) or Clock
Output to Enable Synchronization to Other Switching
Regulators (LT3694-1)
Thermally Enhanced 28-Lead 4mm × 5mm QFN and
20-Lead TSSOP Packages
The LT®3694/LT3694-1 are monolithic, current mode
DC/DC converters with dual, low dropout regulator controllers. The switching converter is a step-down converter
capable of generating up to 2.6A at its output. Each regulator has independent track/soft-start circuits simplifying
power supply sequencing and interfacing with microcontrollers and DSPs.
The switching frequency is set with a single resistor with a
range of 250kHz to 2.5MHz. The high switching frequency
permits the use of small inductors and ceramic capacitors
leading to very small triple output solutions. The constantswitching frequency, combined with low impedance ceramic capacitors, results in low, predictable output ripple.
Protection circuitry senses the current in the power switch
and external Schottky catch diode to protect the LT3694
against short-circuit conditions. Frequency foldback and
thermal shutdown provide additional protection.
With its wide input voltage range of 4V to 36V, the LT3694
regulates a broad array of power sources from 4-cell batteries
and 5V logic rails to unregulated wall transformers, lead acid
batteries and distributed power supplies. The LT3694 can be
synchronized to an external clock with the SYNC pin while
the LT3694-1 offers a CLKOUT pin allowing other DC/DC
converters to synchronize to the LT3694-1 clock.
APPLICATIONS
n
n
n
n
n
Automotive
Industrial
DSL and Cable Modems
Distributed Power Regulation
Wall Transformer Regulation
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Efficiency at VOUT = 3.3V
VIN
4.5V TO 36V
EN/UVLO
VIN BIAS
BST
0.22μF
1nF
TRK/SS1
TRK/SS2
TRK/SS3
0.1Ω
LIM2
OUT1
B340A
LT3694
DA
FB1
VC1
DRV2
OUT2
2.5V
450mA
100
4.7μH
SW
41.2k
2.2μF
24.9k
FB2
SYNC
10.7k
51.1k
10k
OUT1
RT
fSW = 800kHz
90
VIN = 12V
VIN = 36V
80
70
2.2μF
OUT3
1.8V
450mA
60
50
FB3
GND
fSW = 800kHz
VIN = 4.5V
0.1Ω
15.4k
PGOOD
47μF
330pF
LIM3
DRV3
34k
OUT1
3.3V
1.7A
EFFICIENCY (%)
4.7μF
11k
0
1
2
IOUT (A)
3
36941 TA01b
36941 TA01a
36941fa
1
LT3694/LT3694-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN/UVLO (Note 6) ............................... –0.3V to 70V
BST ...........................................................................55V
BST Above SW ..........................................................25V
PGOOD......................................................................16V
TRK/SS, VC, FB, RT, SYNC Pins ...................................6V
BIAS, LIM2, LIM3 Pins ...............................................7V
Operating Junction Temperature Range (Notes 2 and 5)
LT3694E ............................................. –40°C to 125°C
LT3694I .............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
(TSSOP Only) ................................................... 300°C
PIN CONFIGURATION
TOP VIEW
SW
SW
GND
GND
VIN
VIN
TOP VIEW
VIN
1
20 SW
EN/UVLO
2
19 DA
SYNC(CLKOUT)
3
18 BST
PGOOD
4
17 BIAS
19 VC1
RT
5
18 FB1
TRK/SS1
6
17 TRK/SS3
TRK/SS2
7
14 TRK/SS3
FB2
8
13 FB3
DRV2
9
12 DRV3
LIM2 10
11 LIM3
28 27 26 25 24 23
22 DA
EN/UVLO 1
SYNC (CLKOUT) 2
21 BST
PGOOD 3
20 BIAS
29
GND
RT 4
TRK/SS1 5
TRK/SS2 6
FB2 7
16 FB3
DRV2 8
15 DRV3
LIM3
GND
GND
GND
GND
LIM2
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
θJA = 34°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
LT3694-1 PINOUT IS SHOWN IN PARENTHESIS
21
GND
16 VC1
15 FB1
FE PACKAGE
20-LEAD PLASTIC TSSOP
θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
LT3694-1 PINOUT IS SHOWN IN PARENTHESIS
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3694EUFD#PBF
LT3694EUFD#TRPBF
3694
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3694IUFD#PBF
LT3694IUFD#TRPBF
3694
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3694EFE#PBF
LT3694EFE#TRPBF
LT3694FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3694IFE#PBF
LT3694IFE#TRPBF
LT3694FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3694-1EUFD#PBF
LT3694-1EUFD#TRPBF
36941
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3694-1IUFD#PBF
LT3694-1IUFD#TRPBF
36941
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3694-1EFE#PBF
LT3694-1EFE#TRPBF
LT3694FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
LT3694-1IFE#PBF
LT3694-1IFE#TRPBF
LT3694FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
36941fa
2
LT3694/LT3694-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VBIAS = 3V, unless otherwise noted. (Notes 2, 9)
PARAMETER
CONDITIONS
MIN
TYP
VIN Internal Undervoltage Lockout
l
MAX
UNITS
3.5
3.8
4
V
Overvoltage Shutdown Threshold
l
36
38
40
V
Input Quiescent Current
Not Switching
1
2
mA
Bias Quiescent Current
Not Switching
2
3.5
mA
Shutdown Current
VEN/UVLO = 0.1V
0.1
2
μA
EN/UVLO Threshold, Bias On
l
EN/UVLO Threshold, Switching On
Reference Voltage Line Regulation
5V < VIN < 36V
Switching Frequency
RT = 40.2K
350
500
1.16
1.2
mV
1.23
0.01
l
0.9
VIH, SYNC
l
1.5
VIL, SYNC
l
VOH, CLKOUT
ICLKOUT = –50μA
l
VOL, CLKOUT
ICLKOUT = 50μA
l
PGOOD Output Voltage Low
IPGOOD = 250μA
PGOOD Leakage
VPGOOD = 2V
PGOOD Threshold (Relative to VFB)
(Note 8)
1.0
V
%/V
1.1
MHz
V
0.35
V
2.6
V
0.3
V
0.2
0.4
V
10
1000
nA
86
90
94
%
735
750
765
mV
–50
–500
nA
1.6
Switching Regulator
Feedback Pin Voltage
l
Feedback Pin Bias Current
l
Error Amplifier Transconductance
350
Error Amplifier Voltage Gain
μS
600
V/V
TRK/SS Pull-Up Current
–2
–3
–4
μA
TRK/SS Threshold to Start Switching
35
50
70
mV
VC1 Source Current
VC = 0.6V
–20
μA
VC1 Sink Current
VC = 0.6V
28
μA
VC1 Clamp Voltage
2
V
VC1 Switching Threshold
0.75
V
VC1 to Switch Current Gain
3.6
A/V
Switch Leakage Current
VIN = 36V
Minimum Boost Voltage Above Switch
(Note 4)
l
3.5
0.01
10
μA
1.8
2.5
V
4.9
6
A
Switch Current Limit (Note 3)
(Note 3) 10% Duty Cycle
Switch VCESAT
ISW1 = 3A
600
mV
BST Operating Current
ISW1 = 3A
60
mA
VF , BST Diode
IBST = 100mA
0.8
V
IL BST Diode
VBST – VBIAS = 36V
1
μA
DA Current Limit
l
Minimum Switch Off-Time
l
2.6
3.6
4.5
A
140
ns
36941fa
3
LT3694/LT3694-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VBIAS = 3V, unless otherwise noted. (Notes 2, 9)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
735
750
765
mV
–50
–500
nA
–3
–4
μA
50
70
LDO Regulator
Feedback Pin Voltage
l
Feedback Pin Bias Current
l
Error Amplifier Voltage Gain
2800
TRK/SS Pull-Up Current
–2
TRK/SS Threshold to Shut Down LDO
35
Line Regulation
5V < VIN < 36V
0.025
Load Regulation
IDRV From 0.1mA to 10mA
mV
%/V
0.5
mV/mA
Base Drive
l
10
15
20
mA
Current Limit Threshold
l
47
60
70
mV
Short-Circuit Current Limit Threshold
VFB = 0
26
30
mV
Minimum BIAS to DRV Voltage (Note 7)
IDRV = 10mA
l
0.3
0.9
V
Minimum VIN to DRV Voltage
IDRV = 10mA
l
2.0
2.3
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3694E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3694I is guaranteed to meet performance specifications from –40°C to
125°C junction temperature.
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
22
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair
device reliability.
Note 6: Absolute Maximum Voltage at VIN and EN/UVLO pins is 70V for
non-repetitive, 1 second transients and 36V for continuous operation.
Note 7: The LDO will function if the BIAS to DRV differential is not met,
but the base drive current will be drawn from VIN instead of BIAS.
Note 8: The PGOOD pin will pull low when the voltage on any of the three
FB pins is lower than the PGOOD threshold value.
Note 9: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum values refer to absolute values.
36941fa
4
LT3694/LT3694-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency at VOUT = 5V
100
VIN = 12V, TA = 25°C, unless otherwise noted.
BST Pin Current
vs Switch Current
Switch VCESAT vs Switch Current
fSW = 800kHz
VIN = 6.3V
0.8
70
0.7
60
0.6
SWITCH VCESAT (V)
EFFICIENCY (%)
VIN = 12V
BOOST PIN CURRENT (mA)
90
80
VIN = 36V
70
0.5
0.4
0.3
0.2
60
50
40
30
20
10
0.1
50
2
1
0
IOUT (A)
3
0
0
0
36941 G01
2
1
SWITCH CURRENT (A)
3
1
2
SWITCH CURRENT (A)
0
36941 G02
3
36941 G03
Switch Current Limit
vs Duty Cycle
Switch Current Limit
vs Temperature
5.0
5.0
160
–45°C
25°C
3.5
MINIMUM
ON-TIME
120
150°C
TIME (ns)
SWITCH ILIM (A)
4.0
ISW = 1A
140
4.5
4.5
SWITCH ILIM (A)
Switch Minimum On-Time and
Off-Time vs Temperature
4.0
100
MINIMUM
OFF-TIME
80
60
3.5
40
20
3.0
–50
100
50
TEMPERATURE (°C)
150
0
36941 G04
80
20
40
60
SWITCH DUTY CYCLE (%)
100
VFB vs Temperature
5
2.5
756
FREQUENCY (MHz)
VFB (mV)
NORMALIZED FREQUENCY SHIFT (%)
758
752
750
748
746
744
2.0
1.5
1.0
0.5
742
0
0
100
50
TEMPERATURE (°C)
150
36941 G07
100
50
TEMPERATURE (°C)
0
50
100
RT (k)
150
36941 G06
Frequency Shift vs Temperature
Frequency vs RT
3.0
754
0
36941 G05
760
740
–50
0
–50
3.0
0
150
200
36941 G08
RT = 200k
4
RT =
40.2k
3
2
1
RT = 10.7k
0
–1
–2
–3
–4
–5
–50
0
100
50
TEMPERATURE (°C)
150
36941 G09
36941fa
5
LT3694/LT3694-1
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Thresholds
vs Temperature
ITRK/SS vs Temperature
4.0
Minimum Input Voltage
vs Load Current (VIN to Start)
7.0
1.4
UVLO SWITCHING THRESHOLD
3.5
3.0
2.5
TO START
1.0
0.8
BIAS CURRENT
SHUTDOWN THRESHOLD
0.6
0.4
0
0
–50
150
100
50
TEMPERATURE (°C)
5.5
TO RUN
5.0
100
50
TEMPERATURE (°C)
4.0
0.001
150
0.01
0.1
LOAD CURRENT (A)
36941 G11
1
36941 G12
LDO Minimum VIN to DRV Voltage
vs DRV Current
LDO Current Limit
vs VFB (Foldback)
2.5
60
5
+150°C
4
3
2
1
0
–1
–2
–3
50
2.0
–40°C
VIN TO DRV VOLTAGE (V)
CURRENT LIMIT VOLTAGE (mV)
NORMALIZED CURRENT LIMIT (%)
0
36941 G10
LDO Current Limit vs Temperature
40
30
20
10
–4
–5
–50
6.0
4.5
0.2
2.0
–50
VOUT = 5V
fSW = 800kHz
6.5
INPUT VOLTAGE (V)
EN/UVLO THRESHOLD (V)
1.2
TRK/SS CURRENT (μA)
VIN = 12V, TA = 25°C, unless otherwise noted.
0
100
50
TEMPERATURE (°C)
150
0.4
0.6
0.2
FEEDBACK VOLTAGE (V)
0.8
BIAS TO DRV VOLTAGE (V)
0
0
36941 G14
36941 G13
2
4
6
DRV CURRENT (mA)
8
10
36941 G15
LDO Minimum BIAS to DRV
Voltage vs DRV Current
0.5
1.0
0.5
0
0
1.5
10Hz to 100kHz LDO Output Noise
VOUT = 2.5V
IOUT = 0.25A
VIN = 5V
VBIAS = 4.4V
ZXTCM322
PASS XSTR
0.4
0.3
10mV/DIV
0.2
0.1
0
0
2
4
6
DRV CURRENT (mA)
8
10
1ms/DIV
36941 G17
36941 G16
36941fa
6
LT3694/LT3694-1
PIN FUNCTIONS
(FE/UFD)
VIN (Pin 1/Pins 27, 28): The VIN pin supplies power to the
internal switch of the 2.6A regulator and to the LT3694’s
internal reference and start-up circuitry. This pin must be
locally bypassed.
EN/UVLO (Pin 2/Pin 1): The EN/UVLO pin is used to shut
down the LT3694. It can be driven from a logic level or
used as an undervoltage lockout by connecting a resistor
divider from VIN.
CLKOUT (Pin 3/Pin 2): Digital Clock Output. The CLKOUT
pin allows synchronization of other switching regulators
(LT3694-1 only).
SYNC (Pin 3/Pin 2): Frequency Synchronization Input.
Connect a frequency source to this input if synchronization
is desired. Connect SYNC to ground if not used (LT3694
only).
PGOOD (Pin 4/Pin 3): Open Collector Output. PGOOD is
pulled low when any of the three regulators drops out of
regulation (VFB < 90% of nominal value).
RT (Pin 5/Pin 4): The RT pin requires a resistor to ground
to set the operating frequency of the LT3694. If synchronizing the LT3694 to an external clock, the resistor should
be set to program the frequency at least 20% below the
synchronization frequency.
TRK/SS1, TRK/SS2 , TRK/SS3 (Pins 6, 7, 14/Pins 5, 6, 17):
The TRK/SS pins allow a regulator to track the output of
another regulator. When the TRK/SS pin is below 0.75V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB1, FB2, FB3 (Pins 15, 8, 13/Pins 18, 7, 16): Negative
Inputs of the Error Amplifiers. The LT3694 regulates each
feedback pin to the lesser of 0.75V or the corresponding
TRK/SS pin voltage. Connect the feedback resistor divider
taps to these pins.
for the LDO regulators. The DRV pins can provide up to
6V of base drive.
LIM2, LIM3 (Pins 10, 11/Pins 9, 14): The LIM pins provide
current limiting on the LDO pass transistors by sensing
a voltage on an external sense resistor connected to the
BIAS pin. These pins should be connected to BIAS if this
function is not used.
GND (Pins 10, 11, 12, 13, 25, 26) UFD Package Only:
Power and Signal Ground.
VC1 (Pin 16/Pin 19): Output of the Internal Error Amp.
The voltage on this pin controls the peak switch current. This pin is normally used to compensate the
control loop. The switching regulator can be shut
down by pulling the VC1 pin to ground with an NMOS
or NPN transistor.
BIAS (Pin 17/Pin 20): The BIAS pin supplies the current
to the LT3694’s internal regulator and boost circuits. This
must be connected to a voltage source above 3V, usually
to VOUT1. The LDO pass transistor base current will also
come from the BIAS pin if it is at least 1.8V above the
LDO output.
BST (Pin 18/Pin 21): The BST pin is used to provide a
drive voltage, higher than the input voltage, to the internal
bipolar NPN power switch.
DA (Pin 19/Pin 22): The DA pin senses the catch diode
current to prevent excessive inductor current in output
overload or short-circuit conditions.
SW (Pin 20/Pins 23, 24): Output of the Internal Power
Switch. Connect this pin to the inductor and switching
diode.
Exposed Pad (Pin 21/Pin 29): Ground. The underside
exposed pad metal of the package provides both elec-trical
contact to ground and a conductive thermal path to the
printed circuit board. The Exposed Pad must be soldered to
a grounded pad on the circuit board for proper operation.
DRV2, DRV3 (Pins 9, 12/Pins 8, 15): The DRV pins
provide the base drive for the external NPN transistors
36941fa
7
LT3694/LT3694-1
BLOCK DIAGRAM
RT
BIAS
SYNC
(LT3694)
CLKOUT
(LT3694-1)
OUT1
VIN
CLK
EN/UVLO
+
–
0.5V
INT REG
AND REF
–
+
1.2V
PGOOD
OVERVOLTAGE
SHUTDOWN
MASTER
OSC
THERMAL
SHUTDOWN
LDO
OUT1
60mV
LDO
–
RLIM3
PG1
+
LIM3
+
RLIM2
LIM2
OUT1
–
60mV
DRV3
DRV2
3μA
3μA
TRK/SS2
0.75V
FB2
+
+
SD
TRK/SS3
FB3
–
–
–
+
0.68V
0.68V
BUCK
VIN
+
VIN
CIN
BIAS
–
0.9V
3
OUT3
0.75V
SD
+
–
OUT2
+
+
+
BST
R
–
S
SLOPE
COMP
O
C3
L1
SW
OUT1
CLK
DA
+
–
RC
–
+
+
Cf
ERROR
AMP
R1
FB1
–
VC1
C1
D1
R2
0.75V
3μA
+
GND
2V
ILIMIT
CLAMP
PG1
+
–
CC
0.68V
TRK/SS1
36941 F01
Figure 1. LT3694 Block Diagram with Typical External Components
36941fa
8
LT3694/LT3694-1
OPERATION
Unless specifically noted, this data sheet refers to both the
LT3694 and the LT3694-1 generically as the LT3694.
The LT3694 is a constant-frequency, current mode, buck
regulator with an internal power switch plus two low
dropout linear regulator controllers. The three regulators
share common circuitry including input source, voltage
reference, undervoltage lockout, and enable, but are otherwise independent. Operation can be best understood by
referring to the Block Diagram (Figure 1).
the current through the inductor to the output. The internal
error amplifier regulates the output voltage by continually
adjusting the VC1 pin voltage. The threshold for switching
on the VC1 pin is 0.75V and an active clamp of 2V limits
the output current.
Overcurrent protection is provided by the DA comparator.
The DA comparator senses the catch diode current and
will delay the switch-on cycle if the diode current is too
high at the beginning of a cycle.
If the EN/UVLO pin is below 0.35V (min), the LT3694 is
shut down and draws <2μA from the input source tied to
VIN1. If the EN/UVLO pin is driven above 0.5V (typ), the
internal bias circuits turn on, including the internal regulator,
reference and master oscillator. The switching regulator
will only begin to operate when the EN/UVLO pin reaches
>1.20V (typ). The EN/UVLO pin can be driven from a logic
gate or can be used as an undervoltage lockout by using
a resistor divider to VIN.
The switch driver operates either from VIN or from the BST
pin. An external capacitor is used to generate a voltage at
the BST pin that is higher than the input supply. This allows the driver to saturate the internal bipolar NPN power
switch for efficient operation.
The switcher is a current mode regulator. Instead of directly
modulating the duty cycle of the power switch, the feedback
loop controls the peak current in the switch during each
cycle. Compared to voltage mode control, current mode
control improves loop dynamics and provides cycle-bycycle current limit.
The BIAS pin allows the internal circuitry to draw its current from a voltage supply lower than VIN, reducing power
dissipation and increasing efficiency. If the voltage on the
BIAS pin falls below 2.7V, then its quiescent current will
flow from VIN.
A pulse from the oscillator sets the RS flip-flop and turns
on the internal NPN bipolar power switch. Current in the
switch and the external inductor begins to increase. When
this current exceeds a level determined by the voltage
at VC1, the current comparator resets the RS flip-flop,
turning off the switch. The current in the inductor flows
through the external, Schottky, catch diode, and begins to
decrease. The cycle begins again at the next pulse from the
oscillator. In this way, the voltage on the VC1 pin controls
The TRK/SS pins override the 0.75V reference for the FB
pins when the TRK/SS pins are below 0.75V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a minimum load capacitance of 2.2 μF. The
LDO also has a foldback current limiter available to protect
the external transistor under overload conditions
The overvoltage detection shuts down the LT3694 if the
input voltage goes above 38V. This will prevent the switch
from turning on under high voltage conditions and allows
the LT3694 to survive transient input voltages up to 70V.
36941fa
9
LT3694/LT3694-1
APPLICATIONS INFORMATION
STEP DOWN SWITCHING REGULATOR
Feedback Resistor Network
The output voltage is programmed with a resistor divider
(refer to the Block Diagram in Figure 1) between the output
and the FB pin. Choose the resistors according to:
⎛ V
⎞
R1= R2 ⎜ OUT − 1⎟
⎝ 750mV ⎠
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
each clock cycle if there is sufficient voltage across the
boost capacitor (C3 in Figure 1) to fully saturate the output
switch. A forced switch off for a minimum time will only
occur at the end of a clock cycle when the boost capacitor needs to be recharged. This operation has the same
effect as lowering the clock frequency for a fixed off time,
resulting in a higher duty cycle and lower minimum input
voltage. The resultant duty cycle depends on the charging
times of the boost capacitor and can be approximated by
the following equation:
DCMAX =
B
B+1
Input Overvoltage Lockout
An important feature of the LT3694 is the ability to survive
transient surges on the input voltage of up to 70V. This is
accomplished by shutting off the regulators to keep this
high voltage off the critical components. The overvoltage
lockout trips when the input voltage exceeds 38V.
Input Voltage Range
The minimum operating voltage is determined either by the
LT3694’s internal undervoltage lockout or by its maximum
duty cycle. The duty cycle is the fraction of time that the
internal switch is on and is determined by the input and
output voltage:
DC =
VOUT + VF
VIN − VSW + VF
where VF is the forward voltage drop of the catch diode
and VSW is the voltage drop of the internal switch (~0.3V
at maximum load). This leads to a minimum input
voltage of:
VIN(MINCF) =
VOUT + VF
− VF + VSW
DCMAX(CF)
The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. The maximum duty cycle
for constant-frequency operation given by DCMAX(CF) = 1
– tOFF(MIN) • fSW . However, unlike most fixed frequency
regulators, the LT3694 will not switch off at the end of
where B is the output current divided by the typical
boost current from the BST Pin Current vs Switch Current curve in the Typical Performance Characteristics
section.
The maximum voltage, VIN, for constant-frequency operation is determined by the minimum duty cycle DCMIN:
VIN(MAXCF) =
VOUT + VF
− VF + VSW
DCMIN
with DCMIN = tON(MIN) • fSW
Thus, both the maximum and minimum input voltages
for constant-frequency operation are a function of the
switching frequency and output voltage. Therefore, the
maximum switching frequency must be set to a value that
accommodates the input and output voltage parameters
and must meet both of the following criteria:
⎛
⎞
VOUT + VF
1
fMAX1 = ⎜
⎟•
⎝ VIN(MAXCF) − VSW + VF ⎠ tON(MIN)
⎛
⎞
VOUT + VF
1
fMAX2 = ⎜ 1−
⎟•
⎝ VIN(MINCF) − VSW + VF ⎠ tOFF(MIN)
The values of tON(MIN) and tOFF(MIN) are functions of
ISW and temperature (see chart in the Typical Performance Characteristics section). Worst-case values for
switch currents greater than 0.5A are tON(MIN) = 130ns and
36941fa
10
LT3694/LT3694-1
APPLICATIONS INFORMATION
tOFF(MIN) = 140ns. fMAX1 is the frequency at which the minimum duty cycle is exceeded. The regulator will skip ON pulses
in order to reduce the overall duty cycle at frequencies above
fMAX1. It will continue to regulate but with increased
inductor current and greatly increased output ripple. The
increased peak inductor current in pulse-skipping will
also stress the switch transistor at high voltages and high
switching frequency. fMAX2 is the frequency at which the
maximum duty cycle is exceeded. If there is sufficient
charge on the BST capacitor, the regulator will skip OFF
periods to increase the overall duty cycle at frequencies
above fMAX2. It will continue to regulate but will not have
constant-frequency operation.
Note that the restriction on the operating input voltage
refers to steady-state limits to keep the output in regulation
in constant-frequency mode; the circuit will tolerate input
voltage transients up to the absolute maximum rating.
Switching Frequency
Once the upper limit for the switching frequency is found
from the duty cycle requirements, the frequency may be
chosen below the upper limit. Lower frequencies result in
lower switching losses, but require larger inductors and
capacitors. The user must decide the best trade-off. The
switching frequency is set by a resistor connected from
the RT pin to ground, or by forcing a clock signal into the
SYNC pin (LT3694 only). The LT3694 applies a voltage of
0.75V across this resistor and uses the current to set the
oscillator speed. The switching frequency is given by the
following formula:
49.8
fSW =
R T + 8.8
where fSW is in MHz and RT is in kΩ. The formula is
accurate within ±2% over the frequency range. Table 1
shows the typical measured value of RT for several common switching frequencies.
Table 1: RT for Common Frequencies
SWITCHING FREQUENCY (MHz)
RT (k)
0.25
193
0.5
90.2
0.75
56.6
1
40.2
1.25
30.5
1.5
23.8
1.75
19.6
2
16.0
2.25
13.5
2.5
11.4
For external clocks applied to the SYNC pin (LT3694 only),
the circuit will support VH logic levels from 1.8V to 5V
CMOS or TTL. The duty cycle needs a minimum on time of
100ns and a minimum off time of 100ns. When operating
in sync mode, RT should be set to provide a frequency at
least 20% below the minimum sync frequency.
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
L=
VOUT + VF
1.25A • f
where f is the switching frequency in MHz, L is the inductor
value in μH, VOUT is the output voltage and VF is the catch
diode voltage drop.
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-topeak inductor ripple current. The LT3694 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3694 will deliver depends on the switch current
limit, the inductor value and the input and output voltages.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
ΔIL = (1− DC)
VOUT + VF
L•f
36941fa
11
LT3694/LT3694-1
APPLICATIONS INFORMATION
where f is the switching frequency of the LT3694 and L
is the value of the inductor. The peak inductor and switch
current is:
ΔI
ISWPK =ILPK =IOUT + L
2
To maintain output regulation, this peak current must be
less than the LT3694’s switch current limit, ILIM. ILIM is at
least 3.5A at low duty cycles (0.1) and decreases linearly
to 2.8A at DC = 0.8.
The minimum inductance can now be calculated as:
L MIN =
1− DCMIN VOUT + VF
•
2•f
ILIM −IOUT
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
large output capacitors to keep output voltage ripple low.
Select an inductor greater than LMIN that keeps the ripple
current below 30% of ILIM.
For input voltages greater than 30V, use an inductor with
a saturation current of 6A or greater and an inductance
value of 3.3μH or greater.
The inductor’s RMS current rating must be greater than the
maximum load current and its saturation current should
be greater than ILPK. For highest efficiency, the series
resistance (DCR) should be less than 0.1Ω. Table 2 lists
several vendors and types that are suitable.
Table 2. Inductors
SERIES
INDUCTANCE
RANGE (μH)
CURRENT
RANGE (A)
WE-HC
1 to 6.5
6 to 15
Würth Elektronik
www.we-online.com
MSS1048
0.8 to 8
4 to 8
Coilcraft
www.coilcraft.com
CDRH103R
0.8 to 10
2.8 to 8.3
Sumida
www.sumida.com
VLF
2.2 to 10
3.8 to 7.7
TDK
www.component.tdk.
com
1 to 10
2.5 to 9.5
Vishay
www.vishay.com
IHLP-2525CZ-11
MANUFACTURER
This analysis is valid for continuous mode operation
(IOUT > ILIM/2). For details of maximum output current in
discontinuous mode operation, see the Linear Technology Application Note 44. Finally, for duty cycles greater
than 50% (VOUT /VIN > 0.5), a minimum inductance is
required to avoid subharmonic oscillations. This minimum
inductance is:
LMIN =
(VOUT + VF )
2A • fSW
with LMIN in μH and fSW in MHz. A detailed discussion
of subharmonic oscillations can be found in the Linear
Technology Application Note 19.
Input Capacitor Selection
Bypass the input of the LT3694 circuit with a ceramic
capacitor of X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. A 4.7μF to 22μF ceramic capacitor
is adequate to bypass the LT3694 and will easily handle
the ripple current. Use a 22μF capacitor with fSW between
250kHz and 800kHz. Use a 10μF capacitor with fSW between 800kHz and 1.6MHz. Use a 4.7μF capacitor above
1.6MHz. Always check for sufficient margin by reducing
the capacitor value until the dropout increases by >500mV.
If the input power source has high impedance, or there
is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This
can be provided with a lower performance electrolytic
capacitor.
Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage
ripple at the LT3694 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 10μF capacitor is capable of this task, but only if it is
placed close to the LT3694 and the catch diode (see the
PCB Layout section). A second precaution regarding the
ceramic input capacitor concerns the maximum input
voltage rating of the LT3694. A ceramic input capacitor
combined with trace or cable inductance forms a high
36941fa
12
LT3694/LT3694-1
APPLICATIONS INFORMATION
quality (under damped) tank circuit. If the LT3694 circuit
is plugged into a live supply, the input voltage can ring to
twice its nominal value, possibly exceeding the LT3694’s
maximum input voltage rating. See Linear Technology
Application Note 88 for more details.
Output Capacitor Selection
The output capacitor filters the inductor current to generate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3694’s
control loop. Because the LT3694 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
Output ripple can be estimated with the following
equations:
ΔIL
VRIPPLE =
; Ceramic
8 • f • COUT
VRIPPLE = ΔIL • ESR
; Electrolytic
where ΔIL is the peak-to-peak ripple current in the inductor.
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
IC(RMS) =
ΔIL
12
Another constraint on the output capacitor is that it must
have greater energy storage than the inductor; if the stored
energy in the inductor transfers to the output, the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
⎛ I
⎞
COUT > 10 • L • ⎜ LIM ⎟
⎝ VOUT ⎠
2
The low ESR and small size of ceramic capacitors make
them the preferred type for LT3694 applications. Not all
ceramic capacitors are the same, however. Many of the
higher value capacitors use poor dielectrics with high
temperature and voltage coefficients. In particular, Y5V
and Z5U types lose a large fraction of their capacitance
with applied voltage and at temperature extremes. Because
loop stability and transient response depend on the value
of COUT , this loss may be unacceptable. Use X7R and X5R
types instead.
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Surge rated tantalum capacitors
or low ESR, organic, electrolytic capacitors intended for
power supply use are suitable. Choose a capacitor with a
sufficiently low ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 3 lists
several capacitor vendors.
Table 3. Low ESR Surface Mount Capacitors
SERIES
TYPE
Ceramic
TPM, TPS
Ceramic, Tantalum
MANUFACTURER
Taiyo Yuden
www.t-yuden.com
AVX
www.avx.com
T494, T495,
T510, T520,
T525, T530,
A700
Ceramic, Tantalum,
Tantalum Organic Polymer,
Aluminum Organic Polymer
Kemet
www.kemet.com
POSCAP,
OS-CON
Tantalum Organic Polymer,
Aluminum Organic Polymer
Sanyo
www.sanyo.com
SP-CAP
Ceramic,
Aluminum Organic Polymer
Panasonic
www.panasonic.com
Ceramic
TDK
www.tdk.com
36941fa
13
LT3694/LT3694-1
APPLICATIONS INFORMATION
ID(AVG) =IOUT •
VIN − VOUT
VIN
Consider a diode with a larger current rating than ID(AVG)
when the part must survive a shorted output. The DA pin
monitors the current in the diode and prevents the switch
from turning on at the beginning of a charge cycle if the
diode current is above the DA limit. Therefore, under
overload conditions, the average diode current will increase to the average of the switch current limit and the
DA current limit.
Peak reverse voltage is equal to the regulator input voltage,
so use a diode with a reverse voltage rating greater than
the maximum input voltage. The internal OVLO can protect
the diode from excessive reverse voltage by shutting down
the regulator if the input voltage exceeds 38V. Table 4 lists
several Schottky diodes and their manufacturers.
LT3694
CURRENT MODE
POWER STAGE
gm = 7.5S
SW
ERROR
AMPLIFIER
OUTPUT
R1
FB
+
The catch diode (D1 from Figure 1) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
VC pin, as shown in Figure 2. Generally a capacitor (CC)
and a resistor (RC) in series to ground are used. In addition, there may be lower value capacitor in parallel. This
capacitor (CF) is not part of the loop compensation but
is used to filter noise at the switching frequency, and is
required only if a phase-lead capacitor (CPL) is used or if
the output capacitor (C1) has high ESR.
–
Diode Selection
0.75V
gm =
350μS
CPL
ESR
+
3M
C1
C1
VC
CF
POLYMER
OR
TANTALUM
GND
RC
CERAMIC
R2
CC
36941 F02
Figure 2. Model for Loop Response
Table 4. Schottky Diodes (40V, 3A)
PART NUMBER
Vf at 3A (V)
OUTLINE
MBRS340
MBRD340
0.5
0.6
SMC
D-PAK
B340
SMB340
0.5
0.5
SMC
Powermite 3
CMSH3-40
CSHD3-40
0.5
0.65
SMC
D-PAK
MANUFACTURER
ON Semiconductor
www.onsemi.com
Diodes, Inc.
www.diodes.com
Central Semiconductor
www.centralsemi.com
Frequency Compensation
The LT3694 uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3694 does not require the ESR of the output capacitor for
stability, so the user is free to employ ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
Loop compensation determines the stability and transient
performance. The best values for the compensation network depend on the application and in particular the type
of output capacitor. A practical approach is to start with
one of the circuits in this data sheet that is similar to your
application and tune the compensation network to optimize
the performance. Stability should then be checked across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Figure 2
shows an equivalent circuit for the LT3694 control loop.
The error amplifier is a transconductance amplifier with
finite output impedance.
36941fa
14
LT3694/LT3694-1
APPLICATIONS INFORMATION
The power section, consisting of the modulator, power
switch and inductor, is modeled as a transconductance
amplifier generating an output current proportional to
the voltage at the VC1 pin. Note that the output capacitor
integrates this current, and that the capacitor on the VC1
pin (CC) integrates the error amplifier output current,
resulting in two poles in the loop. In most cases a zero
is required and comes from either the output capacitor
ESR or from a resistor RC in series with CC. This simple
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. A phase lead capacitor (CPL) across the feedback divider may improve the
transient response.
Figure 3 shows the transient response when the load
current steps from 1A to 2.6A and back to 1A.
capacitor. A 2.5V output presents a special case because it
is marginally adequate to support the boosted drive stage
while using the internal boost diode. For reliable BST pin
operation with 2.5V outputs, use a good external Schottky
diode (such as the ON Semi MBR0540), and a 1μF boost
capacitor (see Figure 4b). For lower output voltages, the
BIAS pin can be tied to the input (Figure 4c), or to another
supply greater than 2.8V. Tying BIAS to VIN reduces the
maximum input voltage to 7V. The circuit in Figure 4a is
more efficient because the BST pin current and BIAS pin
quiescent current comes from a lower voltage source.
One must also ensure that the maximum voltage ratings
of the BST and BIAS pins are not exceeded. The minimum
VOUT
BIAS
VIN
VIN
GND
4.7μF
BST
LT3694
C3
SW
VOUT
100mV/DIV
(4a) For VOUT > 2.8V
VOUT
D2
IL
1A/DIV
BIAS
VIN
100μs/DIV
36941 F03
VIN
Figure 3. Transient Load Response of the LT3694
Front Page Application as the Load Current Is
Stepped from 1A to 2.6A. VOUT = 3.3V
LT3694
GND
4.7μF
BST
C3
SW
(4b) For 2.5V < VOUT < 2.8V
BST and BIAS Pin Considerations
Capacitor C3 and the internal boost Schottky diode (see the
Block Diagram in Figure 1) are used to generate a boost
voltage that is higher than the input voltage. In most cases
a 0.22μF capacitor will work well. Figure 4 shows three
ways to arrange the boost circuit. The BST pin must be
more than 2.3V above the SW pin for best efficiency. For
outputs of 3V and above, the standard circuit (Figure 4a)
is best. For outputs between 2.8V and 3V, use a 1μF boost
VOUT
BIAS
VIN
4.7μF
VIN
BST
LT3694
GND
C3
SW
36941 FO4
(4c) For VOUT < 2.5V; VIN(MAX) = 7V
Figure 4. Three Circuits for Generating the Boost Voltage
36941fa
15
LT3694/LT3694-1
APPLICATIONS INFORMATION
At light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. This
reduces the minimum input voltage to approximately
300mV above VOUT. At higher load currents, the inductor
current is continuous and the duty cycle is limited by the
maximum duty cycle of the LT3694, requiring a higher
input voltage to maintain regulation.
Internal Undervoltage Lockout
The LT3694 features an internal undervoltage lockout that
will shut off all three regulators if the input voltage drops
too low to maintain regulation of the internal circuitry. This
lockout trips when VIN drops below 3.8V (typ).
5.0
VOUT = 3.3V
fSW = 800kHz
4.8 TO START
INPUT VOLTAGE (V)
4.6
4.4
4.2
4.0
TO RUN
3.8
3.6
3.4
3.2
3.0
0.001
7.0
0.01
0.1
LOAD CURRENT (A)
1
VOUT = 5V
fSW = 800kHz
6.5
TO START
INPUT VOLTAGE (V)
operating voltage of an LT3694 application is limited by
the minimum input voltage (4V) and by the maximum
duty cycle as outlined in a previous section. For proper
start-up, the minimum input voltage is also limited by the
boost circuit. If the input voltage is ramped slowly, or the
LT3694 is turned on with its EN/UVLO or TRK/SS pin when
the output is already in regulation, then the boost capacitor
may not be fully charged. Because the boost capacitor is
charged with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly. This minimum load will depend
on input and output voltages, and on the arrangement of
the boost circuit. The minimum load generally goes to
zero once the circuit has started. Figure 5 shows a plot
of input voltage to start and to run as a function of load
current. In many cases the discharged output capacitor
will present a load to the switcher, which will allow it to
start. The plots show the worst-case situation in which
VIN is ramping very slowly. For lower start-up voltage, the
boost diode can be tied to VIN, however, this restricts the
input range to one-half of the absolute maximum rating
of the BST pin.
6.0
5.5
TO RUN
5.0
4.5
4.0
0.001
0.01
0.1
LOAD CURRENT (A)
1
36941 F05
Figure 5. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
Enable and Programmable Undervoltage Lockout
The EN/UVLO pin provides both logic enable and programmable undervoltage lockout functions. There are
two thresholds on the EN/UVLO pin. The first threshold is
at 500mV (typ). When EN/UVLO is below this threshold,
the LT3694 is in complete shutdown and the quiescent
current drops below 2μA.
36941fa
16
LT3694/LT3694-1
APPLICATIONS INFORMATION
Once EN/UVLO climbs above the first threshold, the internal circuitry of the LT3694 is turned on but the switching
regulator and LDOs remain shut off. A 2μA current sink
on the EN/UVLO pin is activated to provide hysteresis for
the programmable undervoltage function.
+
EN/UVLO
INTERNAL
CIRCUITRY
0.5V
2μA
The second threshold is an accurate 1.2V derived from the
internal reference. When EN/UVLO is above the second
threshold, the regulators turn on and the 2μA current sink
turns off. This allows an accurate programmable UVLO
function by placing a resistor divider between VIN, EN/UVLO
and ground. Figure 6a shows the EN/UVLO block diagram
and Figure 6b shows connections for the programmable
UVLO function.
The trip level is set by the resistor ratio:
–
+
SHUTDOWN
REGULATORS
1.2V
–
(6a) EN/UVLO Block Diagram
VIN
UNDERVOLTAGE TRIP LEVEL
VIN
⎛ R1+ R2 ⎞
VIN(UVTRIP) = 1.2V ⎜
⎝ R2 ⎟⎠
R1
1.2V •
LT3694
EN/UVLO
(R1 + R2)
R2
UVLO HYSTERESIS
2μA • R1
R2
36941 FO4
The hysteresis is set by R1:
VIN(UVHYS) = 2µA • R1
The EN/UVLO pin may be driven with a logic output if the
programmable UVLO is not needed. The requirements for
the logic output are a low output voltage less than 0.35V
(to insure low current shutdown) and a high output voltage greater than 1.25V.
Low Dropout Regulator
Each low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same
0.75V reference as the switching regulators. It requires
an external NPN pass transistor and 2.2μF of output capacitance for stability.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 5 lists some suitable
NPN transistors with their saturation specifications.
(6b) Programmable UVLO Application
Figure 6. Programmable UVLO Application
The base drive voltage has a maximum voltage of 6V.
This will limit the maximum output of the regulator to
6V – VBE(SAT) where VBE(SAT) is the base-emitter saturation
voltage of the pass transistor.
Table 5. Low VCESAT Transistors
PART NUMBER
VCESAT at
IC = 1A
OUTLINE
ZXTN25012EZ
ZXTN25020DG
0.06
0.075
SOT-89
SOT-223
Zetex
www.diodes.com
NSS20201JT1G
NSS12201LT1G
0.22
0.08
SC-89
SOT-23
ON Semiconductor
www.onsemi.com
CTLT3410-M621
0.28
MANUFACTURER
1mm × 2mm Central Semiconductor
www.central-semi.com
TLM621
36941fa
17
LT3694/LT3694-1
APPLICATIONS INFORMATION
The LDO may be shut down if it is unused by pulling the
FB pin up with a resistor that will source at least 30μA. The
FB pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3694 outputs provided that channel is
always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 1.8V above the LDO DRIVE
voltage, otherwise the NPN base current comes from VIN.
The base drive current is limited to 15mA.
LDO FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (refer to the Block Diagram in
Figure 7) between the emitter of the external NPN pass
resistor and the feedback pin, FB2 or FB3. Choose the
resistors according to:
⎛V
⎞
R1= R2 ⎜ OUT − 1⎟
⎝ 0.75 ⎠
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
OUT1
LT3694
BIAS
60mV
RSENSE
+
LIM2
–
DRV2
+
OUT2
0.75V
R1
–
FB2
R2
36941 FO7
Figure 7. LDO with Current Limit
LDO Current Limit
The LDO has a current limit available to reduce the power
consumption of the NPN transistor under overload conditions. The current limit requires the NPN transistor collector
to be connected to the BIAS pin through a low resistance
sense resistor. The current limit circuit senses the voltage
drop across this resistor and reduces the base drive current when the limit voltage exceeds 60mV. This will limit
the output current to 60mV/RSENSE.
If the overload causes the output voltage to drop, the limit
voltage is folded back to reduce power in the NPN transistor. The limit circuit monitors the FB voltage and ramps
the limit voltage down once VFB drops to 0.6V. The limit
voltage will fold back to 26mV when VFB has dropped to
0V. The current foldback is disabled until the associated
TRK/SS pin rises above 0.68V. This insures proper start-up
under full load conditions. Figure 7 shows the LDO circuit
with current limit.
Properly routing the current limit sense resistors is critical
to minimize errors in the current limit. The sense connections are the BIAS pin (both channels) on the high
side and LIM2 or LIM3 on the bottom side. These sense
leads must be routed separately from all current carrying
traces. Figure 9 shows a layout that minimizes trace resistance errors. The current limit sense resistors (RLIM2
and RLIM3) are placed close together and the BIAS pin
trace is connected to VOUT1 at their junction. The bottom
sides of these resistors have a separate via and trace to
the LIM2 and LIM3 pins.
The foldback can dramatically reduce the power dissipation
of the NPN pass transistor under short-circuit conditions.
For example, an application that has VOUT1 = 3.3V and
VOUT2 = 2.5V will nominally have 0.8V across the pass
transistor VCE. Under short-circuit conditions, the pass
transistor VCE will increase to 3.3V. Without foldback the
power dissipation in the pass transistor will increase by
more than 4x, but with foldback the power dissipation
only increases by 78%.
36941fa
18
LT3694/LT3694-1
APPLICATIONS INFORMATION
If the current feeding the collector of the NPN through the
sense resistor comes from a supply that is not connected
to BIAS, the current limit cannot be used and the LIM pin
must be connected to BIAS to disable the current limit.
Tracking and Soft-Start
The output of the LT3694 regulates to the lowest voltage
present at either the TRK/SS pin or an internal 0.75V
reference. A capacitor from the TRK/SS pin to ground is
charged by an internal 3μA current source resulting in a
linear output ramp from 0V to the regulated output whose
duration is given by:
t RAMP =
CTRKSS • 0.75V
3µA
At power-up or at any shutdown event, the TRK/SS pins
are internally pulled to ground through 100Ω to insure
the soft-start capacitors are discharged. The pins clamp
at 1.3V.
Ratiometric tracking is achieved by tying the TRK/SS pins
tied together and connecting to a single capacitor. The
charge current is multiplied by the number of TRK/SS
pins connected.
Coincident tracking is accomplished by adding an additional resistor divider to the master regulator output and
connecting it to the TRK/SS pin of the slave regulator. The
resistor divider should be equal to the slave’s feedback
divider. Keep in mind that the LDO pass transistor VCE(SAT)
will limit how well the LDO output can coincidentally track
the switching regulator output.
The TRK/SS pin has a low voltage detect that insures
the regulator is shut off when TRK/SS is pulled low. The
threshold low voltage is nominally 50mV. This allows
independent on/off control of the LDOs using the TRK/SS
pins. The logic drive should be open collector or have
series resistance because the TRK/SS pins are internally
pulled to ground during any shutdown event.
Shorted and Reversed Input Protection
If an inductor is chosen that will not saturate excessively,
an LT3694 buck regulator will tolerate a shorted output.
There is another situation to consider in systems where
the output will be held high when the input to the LT3694
is absent. This may occur in battery charging applications
or in battery backup systems where a battery or some
other supply is diode ORed with the LT3694’s output. If
the VIN pin is allowed to float and the EN/UVLO pin is held
high (either by a logic signal or because it is tied to VIN),
then the LT3694’s internal circuitry will pull its quiescent
current through its SW pin. This is fine if the system
can tolerate a few mA in this state. If the EN/UVLO pin
is grounded, the SW pin current will drop to essentially
zero. However, if the VIN pin is grounded while the output
is held high, then parasitic diodes inside the LT3694 can
pull large currents from the output through the SW pin
and the VIN pin. The circuit in Figure 8 runs only when the
input voltage is present—and protects against a shorted
or reversed input.
D4
VIN
VIN
BST
LT3694
EN/UVLO
VOUT
SW
VC
GND FB
BACKUP
36941 F08
Figure 8. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also
Protects the Circuit from a Reversed Input. The LT3694
Runs Only When the Input Is Present
36941fa
19
LT3694/LT3694-1
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 9 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT3694’s VIN, DA, and SW pins, the
catch diode (D1) and the input capacitor (CIN). The loop
formed by these components should be as small as possible. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The SW and BST nodes should be as
small as possible. Finally, keep the FB and VC nodes small
so that the ground traces will shield them from the SW
and BST nodes.
The exposed pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the top side ground
plane as much as possible, and add thermal vias under
and near the LT3694 to additional ground planes within
the circuit board and on the bottom side.
High Temperature Considerations
The PCB must provide heat sinking to keep the LT3694
cool. The Exposed Pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3694. Place
additional vias to reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
to ambient can be reduced to θJA = 34°C/W (UFD) or
θJA = 38°C/W (FE20). With 100 LFPM airflow, this resistance can fall by another 25%. Further increases in airflow
will lead to lower thermal resistance.
Because of the large output current capability of the LT3694,
it is possible to dissipate enough heat to raise the junction temperature beyond the absolute maximum. When
operating at high ambient temperatures, the maximum
load current should be derated as the ambient temperature
approaches TJ(MAX).
Power dissipation within the LT3694 can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the catch diode loss
and inductor loss. The die temperature is calculated by
multiplying the LT3694 power dissipation by the thermal
resistance from junction-to-ambient. Keep in mind other
heat sources—such as the catch diode, inductor and LDO
pass transistors.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
36941fa
20
LT3694/LT3694-1
APPLICATIONS INFORMATION
VIN
GND
L1
VOUT1
COUT1
CIN
D1
RLIM2
RLIM3
Q3
Q2
VOUT2
VOUT3
36941 F09
PCB BOTTOM SIDE IS A SOLID GROUND PLANE
THERMAL VIAS TO GROUND PLANE
VIAS TO LIM2/LIM3
SIGNAL VIAS TO INNER LAYERS
VIAS TO Q2 COLLECTOR
VIAS TO BIAS
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
36941fa
21
LT3694/LT3694-1
TYPICAL APPLICATIONS
Automotive Input Range (6V to 16V) to 3.3V, 2.5V, 1.8V
VIN
6V TO 16V
TRANSIENT TO 70V
UVLO 5.8V
4.7μF
100k
26.7k
EN/UVLO
VIN BIAS
BST
0.1μF
TRK/SS1
TRK/SS2
1nF
FB1
LIM2
OUT2
2.5V
450mA
DRV2
34k
DA
0.1Ω
ZXTN25012EZ
OUT1
3.3V
1.7A
B340A
TRK/SS3
OUT1
1.2μH
SW
100pF
34k
LT3694
10k
VC1
10μF
0.1Ω
2.2μF
DRV3
FB2
10.7k
OUT1
LIM3
24.9k
SYNC
ZXTN25012EZ
14k
PGOOD
OUT3
1.8V
450mA
2.2μF
FB3
16k
10k
RT
GND
fSW = 2MHz
36941 TA02
36941fa
22
LT3694/LT3694-1
TYPICAL APPLICATIONS
Wide Input Range to (6.3V to 36V) to 5V, 3.3V, 2.5V With Independent On/Off Control of the LDOs
VIN
6.3V TO 36V
TRANSIENT TO 70V
10μF
VIN BIAS
EN/UVLO
ENABLE
0.22μF 5.4μH
TRK/SS1
ENLD02
TRK/SS2
ENLD03
TRK/SS3
1nF
1nF
BST
B340A
57.6k
DA
1nF
FB1
10.2k
1000pF
0.1Ω
22μF
20k
LIM2
OUT1
OUT2
2.5V
450mA
OUT1
5V
1.7A
SW
ZXTN25020DG
LT3694
VC1
DRV2
0.1Ω
2.2μF
24.9k
LIM3
OUT1
DRV3
ZXTN25020DG
OUT3
3.3V
450mA
FB2
SYNC
10.7k
PGOOD
34k
2.2μF
FB3
66.5k
10k
RT
SYNC GND
CLKIN
36941 TA03
fSW = 800kHz
36941fa
23
LT3694/LT3694-1
TYPICAL APPLICATIONS
Wide Input Range (6V to 36V) to 1.8V, 2.5V and 3.3V
VIN
6V TO 36V
TRANSIENT TO 70V
UVLO 5.8V
22μF
OUT2
100k
26.7k
EN/UVLO
VIN BIAS
BST
0.22μF
TRK/SS1
4.7nF
3.3μH
OUT1
1.8V
2.6A
SW
TRK/SS2
B340A
TRK/SS3
14k
DA
FB1
470pF
LT3694
LIM2
ZXTN25020DG
10k
25.5k
47μF
VC1
DRV2
LIM3
OUT2
3.3V
VIN
OUT2
DRV3
2.2μF
ZXTN25020DG
OUT3
2.5V
34k
FB2
10k
90.2k
24.9k
PGOOD
2.2μF
FB3
10.7k
RT
SYNC GND
fSW = 500kHz
36941 TA04
THE LDO OUTPUT CURRENT CAPABILITY IS LIMITED BY THE POWER DISSIPATION OF THE NPN PASS TRANSISTORS
36941fa
24
LT3694/LT3694-1
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 p 0.05
4.50 p 0.05
3.10 p 0.05
2.50 REF
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
3.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p 0.10
(2 SIDES)
0.75 p 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45o CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
3.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
36941fa
25
LT3694/LT3694-1
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV H 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
36941fa
26
LT3694/LT3694-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/11
Corrected the Pin Configuration drawing and Package Description for the TSSOP package.
2
36941fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3694/LT3694-1
TYPICAL APPLICATION
6V to 28V Input Range with Cascaded Step Down — 3.3V, 2.5V and 1.8V Outputs
Plus Independently Enabled 1.8V, 1.5V and 1.2V Outputs
VIN
6V TO 28V
TRANSIENT TO 70V
10μF
200k
52.3k
VIN BIAS
EN/UVLO
BST
0.1μF
TRK/SS1
1nF
TRK/SS2
B340A
TRK/SS3
DA
FB1
LT3694-1
30.9k
0.1Ω
OUT2
2.5V
450mA
10k
ZXTN25012EZ
24.9k
FB2
14k
CLKOUT
10.7k
10k
fSW = 1MHz
40.2k
10μF
10μF
GNDA
EN4
EN5
EN6
1.5μH
2.2μF
PGND
VIN PVIN
RUN1
PGOOD1
RUN2
PGOOD2
LTC3545
RUN3
SYNC/MODE
SW2
SW1
SW3
1.5μH
20pF
226k
226k
1.5μH
20pF
10μF
OUT6
1.5V, 800mA
10μF
VFB1
511k
OUT5
1.2V
800mA
VFB2
20pF
2.2μF
OUT3
1.8V
200mA
FB3
PGOOD RT GND
OUT4
1.8V, 800mA
22μF
OUT1
LIM3
DRV3
2.2μF
270pF
0.2Ω
DRV2
ZXTN25012EZ
OUT1
3.3V
500mA
34k
VC1
LIM2
OUT1
2.2μH
SW
GNDA
PGND
255k
VFB3
200k
301k
36941 TA05
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3480
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation
VIN: 3.6V to 38V, VOUT(MIN) = 0.78V, IQ = 70μA, ISD < 1μA,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3500
36V, 40VMAX, 2A, 2.5MHz High Efficiency Step-Down DC/DC
Converter and LDO Controller
VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 2.5mA, ISD < 10μA,
3mm × 3mm DFN-10 Package
LT3507
36V, 2.5MHz, Triple (2.4A + 1.5A + 1.5A (IOUT)) with LDO Controller
High Efficiency Step-Down DC/DC Converter
VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD < 1μA,
5mm × 7mm QFN-38 Package
LT3685
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter
VIN: 3.6V to 38V, VOUT(MIN) = 0.78V, IQ = 70μA, ISD < 1μA,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3970
40V, 350mA, 2MHz High Efficiency Micropower Step-Down
DC/DC Converter
VIN: 4V to 40V, Transient to 60V, VOUT(MIN) = 1.21V, IQ = 2μA,
ISD < 1μA, 3mm × 2mm DFN-10 and MSOP-10 Packages
LT3980
58V with Transient Protection to 80V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
VIN: 3.6V to 58V, Transient to 80V, VOUT(MIN) = 0.8V, IQ = 85μA,
ISD < 1μA, 3mm × 4mm DFN-16 and MSOP-16E Packages
36941fa
28 Linear Technology Corporation
LT 0111 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
Similar pages