Catalyst CAT24FC64XITE13 64k-bit i2c serial cmos eeprom Datasheet

CAT24FC64
64K-Bit I2C Serial CMOS EEPROM
FEATURES
■ Industrial and extended
■ Fast mode I2C bus compatible*
temperature ranges
■ Max clock frequency:
■ 5 ms max write cycle time
- 400KHz for VCC=2.5V to 5.5V
t
r
■ Write protect feature
■ Schmitt trigger filtered inputs for noise suppression
– entire array protected when WP at VIH
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 64-byte page write buffer
■ 100 year data retention
■ Self-timed write cycle with auto-clear
■ 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
a
P
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC64 is a 64K-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC64
A0
A1
A2
VSS
it
n
TDFN Package (RD2, ZD2)
1
2
8
7
VCC
WP
A0 1
3
4
6
5
SCL
SDA
A2 3
8 VCC
7 WP
A1 2
6 SCL
VSS 4
5 SDA
o
c
(Top View)
SOIC Package
(J, W, K, X, GW, GX)
A0
A1
A2
VSS
1
8
2
3
4
7
6
5
EXTERNAL LOAD
VCC
A0
WP
A1
SCL
A2
SDA VSS
s
i
D
1
2
3
4
8
7
6
5
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SDA
START/STOP
LOGIC
VCC
WP
SCL
SDA
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
TSSOP Package (U, Y, GY)
PIN FUNCTIONS
Pin Name
u
n
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L, GL)
d
e
features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8pin DIP, SOIC, TSSOP and TDFN packages.
XDEC
128
EEPROM
128X512
CONTROL
LOGIC
WP
Function
DATA IN STORAGE
A0, A1, A2
Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+2.5V to +5.5V Power Supply
A0
A1
VSS
Ground
A2
NC
No Connect
HIGH VOLTAGE/
TIMING CONTROL
SCL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1046, Rev. K
CAT24FC64
ABSOLUTE MAXIMUM RATINGS*
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Temperature Under Bias ................. –55°C to +125°C
Lead Soldering Temperature (10 secs) ............ 300°C
Storage Temperature ....................... –65°C to +150°C
Output Short Circuit Current(2) ........................ 100mA
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............... –2.0V to +7.0V
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
Min
NEND
Endurance
1,000,000
TDR
Data Retention
100
VZAP
ESD Susceptibility
4000
Latch-up
100
ILTH
(4)
Symbol
u
n
Parameter
Test Conditions
ICC1
Power Supply Current - Read
fSCL = 400 KHz
VCC=5V
ICC2
Power Supply Current - Write
ISB(5)
Standby Current
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
VOL
s
i
D
Input High Voltage
Output Low Voltage (VCC = +3.0V)
CIN
(3)
Typ
Volts
mA
1
mA
3
mA
VIN = GND or VCC
VCC=5V
1
µA
VIN = GND to VCC
1
µA
VOUT = GND to VCC
1
µA
-0.5
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
0.4
V
Max
Units
IOL = 3.0 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(3)
Years
Units
it
n
o
c
ILI
Units
Max
fSCL = 400KHz
VCC=5V
Min
t
r
a
P
Max
Cycles/Byte
d
e
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified.
Typ
Conditions
Min
Typ
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
Input Capacitance (SCL, WP, A0, A1)
VIN = 0V
6
pF
70
kΩ
ZWPL
WP Input Impedance
VIN ≤ 0.5V
5
ZWPH
WP Input Impedance
VIN>0.7VxVCC
500
kΩ
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parametesr are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range.
Doc. No. 1046, Rev. K
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
A.C. CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=2.5V - 5.5V
Min
FSCL
tAA
Clock Frequency
SCL Low to SDA Data Out and ACK Out
50
Time the Bus Must be Free Before a New Transmission Can
Start
1300
tHD:STA
Start Condition Hold Time
600
tLOW
Clock Low Period
1300
tHIGH
Clock High Period
d
e
600
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
tSU:DAT
Data In Setup Time
tR(2)
SDA and SCL Rise Time
tF(2)
SDA and SCL Fall Time
it
n
Stop Condition Setup Time
tDH
Data Out Hold Time
tWR
Write Cycle Time
tSP
Input Suppresssion (SDA, SCL)
o
c
tSU;WP
WP Setup Time
tHD;WP
WP Hold Time
s
i
D
Power-Up Timing (2)(3)
Symbol
Parameter
Units
t
r
400
tBUF(2)
tSU:STO
Max
u
n
600
0
kHz
900
ns
a
P
100
ns
ns
ns
ns
ns
ns
ns
300
ns
300
ns
600
ns
50
ns
5
ms
50
ns
600
ns
1300
ns
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
100
µs
tPUW
Power-Up to Write Operation
100
µs
Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 VCC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc No. 1046, Rev. K
CAT24FC64
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
The CAT24FC64 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC64 operates as
a Slave device. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC64's may be addressed
on a single bus system. When the pins are left
unconnected, the default values are zero.
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
d
e
Figure 1. Bus Timing
tF
tHIGH
tR
tLOW
tSU:STA
it
n
tHD:STA
SDA IN
tHD:DAT
tAA
SDA OUT
o
c
Figure 2. Write Cycle Timing
is
SCL
SDA
D
8TH BIT
u
n
tLOW
SCL
t
r
a
P
A0, A1, A2: Device Address Inputs
PIN DESCRIPTIONS
tSU:DAT
tSU:STO
tBUF
tDH
ACK
BYTE n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1046, Rev. K
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
I2C BUS PROTOCOL
as many as eight devices on the same bus. These bits
must compare to their hardwired input pins. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC64 monitors the
SDA and SCL lines and will not respond until this
condition is met.
DEVICE ADDRESSING
it
n
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC64 uses the next three bits
as address bits. The address bits A2, A1 and A0 allow
o
c
Figure 4. Acknowledge Timing
s
i
D
SCL FROM
MASTER
a
P
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
d
e
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
t
r
After the Master sends a START condition and the slave
address byte, the CAT24FC64 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC64 then performs a Read or Write operation
depending on the state of the R/W bit.
The CAT24FC64 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
u
n
When the CAT24FC64 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC64 will continue to transmit
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 5. Slave Address Bits
1
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
0
1
0
A2
5
A1
A0
R/W
Doc No. 1046, Rev. K
CAT24FC64
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC64 in a single write cycle.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC64. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24FC64 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24FC64 writes up to 64 bytes of data, in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24FC64 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain unchanged.
it
n
o
c
Figure 6. Byte Write Timing
s
i
D
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
A
C
K
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC64 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24FC64 is still busy with the write
operation, no ACK will be returned. If
CAT24FC64 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
a
P
d
e
WRITE PROTECTION
u
n
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24FC64 will
accept both slave and byte addresses, but the memory
location accessed is protected from programming by the
device’s failure to send an acknowledge after the first
byte of data is received.
BYTE ADDRESS
A15–A8
A7–A0
* **
t
r
Acknowledge Polling
S
T
O
P
DATA
P
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
DATA
DATA n
S
T
O
P
DATA n+63
P
***
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Doc. No. 1046, Rev. K
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
The READ operation for the CAT24FC64 is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
slave address and byte addresses of the location it
wishes to read. After CAT24FC64 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24FC64 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Immediate/Current Address Read
Sequential Read
The CAT24FC64’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address
N, the READ immediately following would access data
from address N+1. If N=E (where E=8,191), then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24FC64 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8 bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC64 sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC64 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
READ OPERATIONS
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
it
n
Figure 8. Immediate Address Read Timing
o
c
s
i
D
BUS ACTIVITY:
MASTER
SCL
SDA
SDA LINE
S
T
A
R
T
d
e
a
P
The data being transmitted from CAT24FC64 is outputted
sequentially with data from address N followed by data
from address N+1. The READ operation address counter
increments all of the CAT24FC64 address bits so that
the entire memory array can be read during one operation.
If more than E (where E=8,191) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
u
n
SLAVE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
8
N
O
A
C
K
9
8TH BIT
DATA OUT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
t
r
NO ACK
7
STOP
Doc No. 1046, Rev. K
CAT24FC64
Figure 9. Selective Read Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
S
T
A
R
T
BYTE ADDRESS
A15–A8
A7–A0
***
S
SLAVE
ADDRESS
DATA
S
A
C
K
A
C
K
P
A
C
K
A
C
K
*=Don't Care Bit
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
SDA LINE
A
C
K
A
C
K
it
n
o
c
s
i
D
Doc. No. 1046, Rev. K
S
T
O
P
d
e
DATA n+2
u
n
A
C
K
8
A
C
K
t
r
N
O
A
C
K
a
P
S
T
O
P
DATA n+x
P
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
Suffix
24FC64
J
Product
Number
I
TE13
Temperature Range
I = Industrial (-40˚C to 85˚C)
E = Extended (-40˚C to 125˚C)
Tape & Reel
REV-D
t
r
Die Revision
Package
P: PDIP
K: SOIC, EIAJ
J: SOIC, JEDEC
U: TSSOP
RD2: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
ZD2: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
it
n
d
e
u
n
a
P
Notes:
(1) The device used in the above example is a 24FC64JI-TE13 REV-D (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
o
c
s
i
D
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1046, Rev. K
REVISION HISTORY
Date
Revision Comments
03/03/04
C
Added 8-pin TSSOP package (updated in all areas)
Updated DC Operating Characteristics
Updated Power-Up Timing
03/26/04
D
Changed Advance designation to Preliminary
04/02/04
E
Eliminated data sheet designation
05/15/04
F
Update
Update
Update
Update
Update
Update
06/07/04
G
Update AC Characteristics (Write Cycle Time)
Features
D.C. Operating Characteristics
Read & Write Cycle Limits
Ordering Information
Revision History
Rev Number
7/27/04
H
Update notes on page 2
8/25/04
I
Update notes in Ordering Information section
03/24/05
J
Update
Update
Update
Update
Update
Update
Update
08/03/05
K
Update Pin Configuration
Update Ordering Information
Features
Description
Pin Functions
Reliability Characteristics
D.C. Operating Characteristics
A.C. Characteristics
Ordering Information
it
n
u
n
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
o
c
d
e
t
r
a
P
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
s
i
D
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1046
K
08/03/05
Similar pages