Microsemi NX2113CMTR 300khz & 600khz synchronous pwm controller with programmable bus uvlo Datasheet

Evaluation board available.
NX2113/2113A
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER WITH
PROGRAMMABLE BUS UVLO
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
Synchronous Controller in 10 Pin Package
The NX2113 controller IC is a synchronous Buck conBus voltage operation from 2V to 25V
troller IC designed for step down DC to DC converter
Enable pin allows programmable BUS UVLO
applications. Synchronous control operation replaces the
Less than 50 nS adaptive deadband
traditional catch diode with an Nch MOSFET resulting
Internal
300kHz for 2113 and 600kHz for 2113A
in improved converter efficiency. The NX2113 controller
Internal
Digital Soft Start Function
is optimized to convert bus voltages from 2V to 25V to
Separated
power ground and analog ground for
outputs as low as 0.8V voltage using Enable pin to
extra
noise
filtering
program the BUS voltage start up threshold. The NX2113
n
Pb-free
and
RoHS compliant
operates at 300kHz while 2113A is set at 600kHz
operation which together with less than 50 nS of dead
band provides an efficient and cost effective solution. n Graphic Card on board converters
Other features of the device are:
n Memory Vcore or Vddq supply
Internal digital soft start; Vcc undervoltage lock out; n On board DC to DC such as
Output undervoltage protection with digital filter and shut12V, 5V to 3.3V, 2.5V or 1.8V
down capability via the enable pin.
n Hard Disk Drive
APPLICATIONS
TYPICAL APPLICATION
L2 1uH
Vin
+12V
C5
1uF
C3
47uF
C6
1uF
R3
10
Vin
+5V
C4
1uF
R5
68k
6
ON
R7
10k
C9
5
1
R6
12.4k
9
1uF
C1
47pF
C2
2.7nF
R4
11k
8
EN
Comp
Fb
PGnd Gnd
3
R2
10k 1%
NX2113A
R8 10k 2N3904
D1
C7
0.1uF
Vcc PVcc BST
7
OFF
Cin
270uF,18mohm
Hdrv
M1
2
L1 1.5uH
SW
Ldrv
10
M2
4
Vout
+1.6V,10A
Co
3x (220uF,12mohm)
11
R1 10k 1%
R9 1.2k
C8 2.2nF
Figure1 - Typical application of 2113A
ORDERING INFORMATION
Device
NX2113CMTR
NX2113CUTR
NX2113ACMTR
NX2113ACUTR
Rev. 2.0
11/18/05
Temperature
0 to 70oC
0 to 70o C
0 to 70oC
0 to 70o C
Package
MLPD-10L
MSOP-10L
MLPD-10L
MSOP-10L
Frequency
300kHz
300kHz
600kHz
600kHz
Pb-Free
Yes
Yes
Yes
Yes
1
NX2113/2113A
ABSOLUTE MAXIMUM RATINGS
Vcc to GND & BST to SW voltage ................... 6.5V
BST to GND Voltage ...................................... 35V
Storage Temperature Range ............................. -65oC to 150oC
Operating Junction Temperature Range ............. -40oC to 125oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
10-LEAD PLASTIC MLPD
θ JA ≈ 52o C /W
θJA ≈ 200o C/W
BST 1
HDrv 2
BST 1
10 SW
9 Comp
10 SW
HDrv 2
9 Comp
PAD
(Gnd)
PGnd/Gnd 3
8 Fb
PGnd 3
LDrv 4
7 EN
LDrv 4
7 EN
PVcc 5
6 Vcc
PVcc 5
6 Vcc
8 Fb
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
PARAMETER
Reference Voltage
Ref Voltage
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
VCC Supply Current (Static)
VCC Supply Current
(Dynamic)
VCC
ICC (Static) Outputs not switching
ICC
CLOAD=3300pF FS=300kHz
(Dynamic)
Supply Voltage(VBST)
VBST Supply Current (Static)
IBST (Static) Outputs not switching
VBST Supply Current
(Dynamic)
IBST
CLOAD=3300pF
(Dynamic)
Under Voltage Lockout
VCC-Threshold
VCC-Hysteresis
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
SS
Soft Start time
Rev. 2.0
11/18/05
SYM
VREF
Tss
Test Condition
Min
4.5V<Vcc<5.5V
TYP
MAX
0.8
0.4
FS=300kHz
Fsw=300Khz, 2113
Fsw=600Khz, 2113A
4.5
5
2.1
5
Units
V
%
5.5
V
mA
mA
0.15
mA
5
mA
4.1
0.22
V
V
3.4
1.7
mS
2
NX2113/2113A
PARAMETER
Oscillator (Rt)
Frequency
SYM
Ramp-Amplitude Voltage
Max Duty Cycle
Min Duty Cycle
Error Amplifiers
Transconductance
Input Bias Current
FB Under Voltage Protection
FB Under voltage threshold
EN
Enable Threshold Voltage
Enable Hysterises
High Side Driver(CL=3300pF)
VRAMP
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time
Fall Time
Deadband Time
FS
Test Condition
2113
2113A
Min
TYP
MAX
Units
0
kHz
kHz
V
%
%
300
600
2.1
93
Ib
Enable ramp up
2100
10
umho
nA
0.4
V
1.25
0.2
V
V
Rsource(Hdrv)
I=200mA
1.1
ohm
Rsink(Hdrv)
I=200mA
0.8
ohm
THdrv(Rise)
THdrv(Fall)
Tdead(L to
H)
VBST-VSW =4.5V
VBST-VSW =4.5V
Ldrv going Low to Hdrv
going High, 10%-10%
50
50
30
ns
ns
ns
Rsource(Ldrv)
I=200mA
1.1
ohm
Rsink(Ldrv)
I=200mA
0.5
ohm
50
50
30
ns
ns
ns
Low Side Driver (CL=3300pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time
Fall Time
Deadband Time
Rev. 2.0
11/18/05
TLdrv(Rise)
10% to 90%
TLdrv(Fall)
90% to 10%
Tdead(H to SW going Low to Ldrv
L)
going High, 10% to 10%
3
NX2113/2113A
PIN DESCRIPTIONS
PIN #
PIN SYMBOL
1
BST
PIN DESCRIPTION
This pin supplies voltage to the high side driver. A high frequency
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.
2
HDRV
High side MOSFET gate driver.
3
PGND/Gnd
Power and analog ground pin. For MLPD package, analog ground and power ground
are separated, additional pad pin(11) is available for analog ground.
4
LDRV
Low side MOSFET gate driver.
5
PVcc
Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to
GND directly.
6
Vcc
Voltage supply for the internal circuit as well as the low side MOSFET gate driver. A
1uF high frequency ceramic capacitor must be connected from this pin to GND pin.
Pull up this pin to Vcc for normal operation. Pulling this pin down below 1.25V
7
EN
shuts down the controller and resets the soft start. This pin can also be used as
a UVLO detector for the bus voltage via a resistor divider.
8
FB
This pin is the error amplifier inverting input. This pin is also connected to the output
UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs
are latched off.
9
COMP
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop.
SW
This pin is connected to the source of the high side MOSFET and provides return
path for the high side driver.
10
Rev. 2.0
11/18/05
4
NX2113/2113A
BLOCK DIAGRAM
VCC
Bias
Generator
1.25V
0.8V
UVLO
POR
BST
START
EN
DRVH
1.25/1.15
FB
SW
0.4
PVCC
START
Digital
start Up
OSC
DRVL
S
R
Q
FB
COMP
START
GND
Rev. 2.0
11/18/05
5
NX2113/2113A
Demo Board Schematic
JP2
L2
1
2
BUS
BUS1
D O 1608C -102
C 12
47u
C7
JP3
VCC
C 13
47u
R4
10
D1
D 1N 5819
R 12
68k
C 14
1u
VCC1
C 24
1u
C9
1u
VCC2
Q1
IR F R 3706
8
7
6
5
1
2
C8
OP
16S P 270M
R 10
OP
6
5
PVC C
R6
open
Hdrv
SW
10
L d rv 4
11
Fb
PG N D
1
2
C1
OP
R2
0
8
JP 5
OUT2
D O 5010P-781H C
Ldrv
R5
11k
0
L1
OUT1
3
4
(G N D
PAD)
D2
D 1N 5819
R3
OP
1
2
3
Q2
IR F R 3706
C 18
C 21
C 22
2R 5T P E 220M C
C 15
2.7n
C 11
47p
1
2
3
7
COMP
2R 5T P E 220M C
10k
2
C 20
.1u
2R 5T P E 220M C
R 14
H d rv
R1
0
8
7
6
5
10k
C 17
open
C 16
open
1
BST
N X 2113A
Q3
R 13
EN
9
2N 3904
TP1
4
U1
VC C
R 11
12.4k
G N D
C 25
1uF
R 15
2k
GND
C 19
J1
R7
1
C2
.1u
5
2
3
4
1.2k
2.2n
R8
R9
10k
10k
Figure 2 - Demoboard design on NX2113A
Rev. 2.0
11/18/05
6
NX2113/2113A
Bill of Materials
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Rev. 2.0
11/18/05
Quantity
6
2
1
3
1
2
1
3
3
1
1
2
3
2
1
1
2
1
2
1
1
2
1
1
1
1
1
Reference
C1,R3,C8,R10,C23,D2
C2,C20
C7
C9,C14,C24
C11
C12,C13
C15
R6,C16,C17
C18,C21,C22
C19
C25
D1
JP2,JP3,JP5
J1
L1
L2
Q1,Q2
Q3
R1,R2
R4
R5
R8,R9,R13,R14
R7
R11
R12
R15
U1
Part
OPEN
.1uF
16SP270M
1uF
47pF
47uF
2.7nF
OPEN
220uF 2R5TPE220MC
2.2nF
1uF
D1N5819
CON2
SCOPE TP
DO5010P-781HC
DO1608C-102
IRFR3706
2N3904
0
10
11k
10k
1.2k
12.4k
68k
2k
NX2113
Manufacture
SANYO
SANYO
Tektronics
Coilcraft
Coilcraft
International Rectifier
NEXSEM INC.
7
NX2113/2113A
DEMO BOARD WAVEFORM
Figure 3: Output efficiency
Figure 5: Output voltage transient response
for load curent 0A-9A
Figure 7: ENABLE function.(Ch1-enable, Ch2-Ldrv,
Ch3-output voltage)
Rev. 2.0
11/18/05
Figure 4: Voltage ripple @1.6 V output voltage.
(Ch2-ripple, Ch3-Hdrv)
Figure 6: Start up time(Ch1-input volatge,
Ch2-output voltage)
Figure 8: Startup operation waveform
8
NX2113/2113A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN
- Input voltage
VOUT
- Output voltage
IOUT
- Output current
=
...(2)
12V-1.6V 1.6v
1
×
×
= 3A
0.78uH
12v 600kHz
Output Capacitor Selection
DVRIPPLE - Output voltage ripple
FS
VIN -VOUT VOUT
1
×
×
L OUT
VIN
FS
∆IRIPPLE =
Output capacitor is basically decided by the
- Working frequency
amount of the output voltage ripple allowed during steady
DIRIPPLE - Inductor current ripple
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
the schematic is figure 2.
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
VIN = 12V
condition is determined by equation(3).
Design Example
The following is typical application for NX2113A,
VOUT=1.6V
∆VRIPPLE = ESR × ∆IRIPPLE +
IOUT=10A
DVRIPPLE <=20mV
Where ESR is the output capacitors' equivalent
DVDROOP<=80mV @ 10A step
series resistance,COUT is the value of output capacitors.
FS=600kHz
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
Output Inductor Selection
types are used, the amount of the output voltage ripple
The selection of inductor value is based on inductor ripple current, power rating, switching frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu-
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
ESR desire =
decided by design engineer according to various application requirements. The inductor value can be calcu-
IRIPPLE =k × IOUTPUT
If low ESR is required, for most applications, mul-
2R5TPE220MC with 12mΩ are chosen.
...(1)
12V-1.6V 1.6V
1
×
×
0.3 × 10A 12V 600kHz
LOUT =0.8uH
LOUT =
Choose inductor from COILCRAFT DO5010P781HC with L=0.78uH is a good choice.
Rev. 2.0
11/18/05
...(4)
tor. For example, for 20mV output ripple, POSCAP
where k is between 0.2 to 0.4.
Select k=0.3, then
Current Ripple is recalculated as
∆VRIPPLE 20mV
=
= 6.7m Ω
∆IRIPPLE
3A
tiple capacitors in parallel are better than a big capaci-
lated by using the following equations:
V -V
V
1
L OUT = IN OUT × OUT ×
∆IRIPPLE
VIN
FS
∆IRIPPLE
8 × FS × COUT ...(3)
N =
E S R E × ∆ IR I P P L E
∆ VR IPPLE
...(5)
Number of Capacitor is calculated as
N=
12m Ω × 3A
20m V
N =1.8
The number of capacitor has to be round up to a
integer. Choose N =2.
If ceramic capacitors are chosen as output ca9
NX2113/2113A
pacitors, both terms in equation (3) need to be evaluated
of output capacitor. For low frequency capacitor such
to determine the overall ripple. Usually when this type of
as electrolytic capacitor, the product of ESR and ca-
capacitors are selected, the amount of capacitance per
pacitance is high and L ≤ L crit is true. In that case, the
single unit is not sufficient to meet the transient specifi-
transient spec is dependent on the ESR of capacitor.
cation, which results in parallel configuration of multiple
In most cases, the output capacitors are multiple
capacitors .
capacitors in parallel. The number of capacitors can be
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
calculated by the following
∆VRIPPLE
N=
3A
= 2mΩ × 3A +
8 × 600kHz × 100uF
= 6mV + 6.2mV = 12.2mV
Based On Transient Requirement
Typically, the output voltage droop during transient
∆VDROOP <∆VTRAN @ step load DISTEP
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DISTEP
transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the following equation.
VOUT
× τ2
2 × L × COUT
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR E × CE
 V
 OUT
...(9)
if
L ≥ L crit
...(10)
For example, assume voltage droop during tranIf the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is
used, the critical inductance is given as:
L crit =
The selected inductor is 0.78uH which is bigger
than critical inductance. In that case, the output voltage
transient not only dependent on the ESR, but also capacitance.
number of capacitors is
τ=
=
if
L ≥ L crit
L × ∆Istep
VOUT
− ESR E × CE
0.78µH ×10A
− 12mΩ× 220µF = 2.24us
1.6V
...(7)
N=
where
ESR × COUT × VOUT ESR E × C E × VOUT
=
=
∆Istep
∆I step
ESR E × C E × VOUT
=
∆Istep
12mΩ × 220µF × 1.6V
= 0.42µH
10A
...(6)
where τ is the a function of capacitor, etc.
L crit
VOUT
× τ2
2 × L × C E × ∆Vtran
sient is 100mV for 10A load step.
is specified as:
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR × COUT
 V
 OUT
∆Vtran
+
where
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
∆Vovershoot = ESR × ∆Istep +
ESR E × ∆Istep
...(8)
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
ESR E × ∆Istep
∆Vtran
+
VOUT
× τ2
2 × L × CE × ∆Vtran
12mΩ ×10A
+
80mV
1.6V
× (2.24us) 2
2 ×1.5µH × 220µF × 80mV
≈ 1.7
=
The above equation shows that if the selected out-
The number of capacitors has to satisfy both ripple
put inductor is smaller than the critical inductance, the
and transient requirement. Overall, we can choose N=3.
voltage droop or overshoot is only dependent on the ESR
Rev. 2.0
11/18/05
10
NX2113/2113A
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equa-
FZ1 =
1
2 × π × R 4 × C2
...(11)
FZ2 =
1
2 × π × (R 2 + R3 ) × C3
...(12)
FP1 =
1
2 × π × R3 × C3
...(13)
tion gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
1
FP2 =
2 × π × R4 ×
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
...(14)
C1 × C2
C1 + C2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
Compensator Design
Due to the double pole generated by LC filter of the
the compensator. Their locations are shown in figure 10.
The transfer function of type III compensator for
power stage, the power system has 180o phase shift ,
transconductance amplifier is given by:
and therefore, is unstable by itself. In order to achieve
Ve
1 − gm × Z f
=
VOUT
1 + gm × Zin + Z in / R1
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than cross-
For the voltage amplifier, the transfer function of
compensator is
Ve
−Z f
=
VOUT
Zin
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm
is desirable.
over frequency. Otherwise type III compensator should
be chosen.
Zin
Zf
C1
Vout
A. Type III compensator design
For low ESR output capacitors, typically such as
R3
R2
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross-
C3
ing figures and equations show how to realize the type III
compensator by transconductance amplifier.
R4
Fb
over frequency. In this case, it is necessary to compensate the system with type III compensator. The follow-
C2
gm
Ve
R1
Vref
Figure 9 - Type III compensator using
transconductance amplifier
Rev. 2.0
11/18/05
11
NX2113/2113A
smaller than 1/10~ 1/5 of the switching frequency. Set
Gain(db)
FO=45kHz.
C3 =
power stage
FLC
40dB/decade
1
1 1
×(
)
2 × π × R2
Fz2 Fp1
1
1
1
×(
)
2 × π × 10kΩ 7kHz 60kHz
=2nF
=
R4 =
loop gain
FESR
VOSC 2 × π × FO × L
×
× Cout
Vin
C3
2V 2 × π × 45kHz × 0.78uH
×
× 660uF
12V
2.2nF
=11kΩ
=
20dB/decade
Choose C3=2.2nF, R 4=11kΩ.
compensator
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
C2 =
FZ1 FZ2
FO FP1
FP2
1
2 × π × FZ1 × R 4
1
2 × π × 0.75 × 7kHz × 11k Ω
= 2.75nF
Choose C2=2.7nF.
6. Calculate C 1 by equation (14) with pole F p2 at
half the swithing frequency.
=
Figure 10 - Bode plot of Type III compensator
Design example for type III compensator are in
order. Use the same power stage requirement as demo
board. The crossover frequency has to be selected as
FLC<FO<FESR, and FO<=1/10~1/5Fs.
1.Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
1
2 × π × R 4 × FP2
1
2 × π × 11k Ω × 300kHz
= 48pF
=
1
2 × π × LOUT × COUT
=
1
2 × π × 0.78uH × 660uF
= 7kHz
FESR
C1 =
1
=
2 × π × ESR × C OUT
1
2 × π × 4m Ω × 660uF
= 60kHz
=
Choose C1=47pF.
7. Calculate R 3 by equation (13).
R3 =
1
2 × π × FP1 × C3
1
2 × π × 60kHz × 2.2nF
= 1.2k Ω
=
Choose R3=1.2kΩ.
2.Set R2 equal to10kΩ, then R1= 10kΩ.
3. Set zero FZ2 = FLC and Fp1 =FESR .
4. Calculate R4 and C3 with the crossover frequency
Rev. 2.0
11/18/05
12
NX2113/2113A
B. Type II compensator design
noise. The following equations show the compensator
If the electrolytic capacitors are chosen as power
pole zero location and constant gain.
stage output capacitors, usually the Type II compensa-
Gain=gm ×
tor can be used to compensate the system.
Vout
Fz =
R2
1
2 × π × R3 × C1
Fp ≈
Fb
Ve
gm
R1
... (15)
... (16)
1
2 × π × R3 × C2
... (17)
For this type of compensator, FO has to satisfy
R3
Vref
R1
× R3
R1+R2
C2
C1
FLC<FESR<<FO<=1/10~1/5Fs.
The following uses typical design in figure 18 as
an example for type II compensator design, two 680uF
with 36mΩ electrolytic capacitors are used.
1.Calculate the location of LC double pole F LC
Figure 11 - Type II compensator with
transconductance amplifier
and ESR zero FESR.
FLC =
1
2 × π × L OUT × COUT
1
=
2 × π × 4.7uH × 1360uF
= 2.0kHz
Gain(db)
power stage
40dB/decade
FESR =
loop gain
1
2 × π × ESR × C OUT
1
2 × π × 18m Ω × 1360uF
= 6.5kHz
=
20dB/decade
2.Set R2 equal to10kΩ. Using equation 18.
R1 =
compensator
Gain
10kΩ × 0.8V
= 4.7k Ω
2.5V-0.8V
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
FZ FLC FESR FO FP
4.Calculate R3 value by the following equation.
R3 =
Figure 12 - Bode plot of Type II compensator
Type II compensator can be realized by simple
RC circuit without feedback as shown in figure 11. R3
and C1 introduce a zero to cancel the double pole
effect. C2 introduces a pole to suppress the switching
Rev. 2.0
11/18/05
VOSC 2 × π × FO × L 1 R1+R2
×
×
×
Vin
RESR
gm
R1
2V 2 × π × 30kHz × 4.7uH
1
×
×
12V
18mΩ
2.5mA/V
10kΩ+4.7kΩ
×
4.7kΩ
=10.3kΩ
=
Choose R 3 =10kΩ.
13
NX2113/2113A
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
including the resistor divider should be less than 5kΩ to
prevent overcharge the output voltage by leakage cur-
1
2 × π × R 3 × Fz
C1 =
rent (e.g. Error Amplifier feedback pin bias current). A
1
2 × π × 10k Ω × 0.75 × 6.5kHz
=10.7nF
=
minimum load for 5kΩ less (<1/16w for most of application) is recommended to put at the output. For example,
in this application,
Vout=1.6V
Choose C1=10nF.
The power loss is 1/16W less
6. Calculate C2 by setting compensator pole Fp at
half the swithing frequency.
RLOAD = 1.6V × 1.6V /(1/16W) = 40Ω
Select minimum load is 1kΩ should be good
enough.
1
π × R 3 × Fs
C2=
In general, the minimum output load impedance
1
π × 10kΩ × 300kH z
=106pF
=
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk ca-
Choose C2=100pF.
pacitors supply current to the MOSFETs. Usually 1uF
ceramic capacitor is chosen to decouple the high fre-
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
quency noise. The bulk input capacitors are decided by
voltage rating and RMS current rating. The RMS current
in the input capacitors can be calculated as:
so that the output voltage applied at the Fb pin is 0.8V
IRMS = IOUT × D × 1- D
when the output voltage is at the desired value. The
D=
following equation and picture show the relationship
VOUT , VREF and voltage divider..
between
R 1=
R 2 × VR E F
V O U T -V R E F
VOUT
VIN
...(19)
VIN = 12V, VOUT=1.6V, IOUT=10A, using equation
(19), the result of input RMS current is 3.4A.
...(18)
where R2 is part of the compensator, and the
value of R1 value can be set by voltage divider.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON SP series
16SP270M 16V 270uF with 4.4A is chosen as input
bulk capacitor.
Choose R2=10kΩ, to set the output voltage at
1.6V, the result of R1 is 10kΩ.
Power MOSFETs Selection
The NX2113 requires two N-Channel power
Vout
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
R2
Fb
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
R1
Vref
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
Voltage divider
used. They have the following parameters: V DS=30V, ID
=75A,RDSON =9mΩ,QGATE =23nC.
Figure 13 - Voltage divider load
Rev. 2.0
11/18/05
14
NX2113/2113A
There are three factors causing the MOSFET power
Vbus
+
loss: conduction loss, switching loss and gate driver loss.
Gate driver loss is the loss generated by discharg-
POR
ing the gate capacitor and is dissipated in driver circuits.
OFF
It is proportional to frequency and is defined as:
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS
R1
EN
ON
R2
...(20)
1.25/1.15
Digital
start
up
10k
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is
the low side gate source voltage.
According to equation (20), PGATE =0.14W. This
power dissipation should not exceed maximum power
dissipation of the driver device.
Conduction loss is simply defined as:
PTOTAL =PHCON + PLCON
The start up of NX2113/2113A can be programmed
through resistor divider at Enable pin. For example, if
the input bus voltage is 12V and we want NX2113 starts
PHCON =IOUT 2 × D × RDS(ON) × K
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K
Figure 14 - Enable and Shut down NX2113 by
pulling down EN pin.
when Vbus is above 8V. We can select
R2=1.24k
...(21)
R1 =
where the RDS(ON) will increases as MOSFET junc-
(8V − 1.25V) × R 2
= 6.8k Ω
1.25V
tion temperature increases, K is RDS(ON) temperature
The NX2113 can be turned off by pulling down the
dependency. As a result, RDS(ON) should be selected for
ENable pin by extra signal MOSFET or NPN transistor
the worst case, in which K equals to 1.4 at 125oC ac-
such as 2N3904 as shown in the above Figure. When
cording to IRFR3706 datasheet. Using equation (21),
Enable pin is below 1.15V, the digital soft start is reset
the result of PTOTAL is 0.54W. Conduction loss should
to zero. In addition, all the high side is off and output
not exceed package rating or overall system thermal
voltage is turned off.
A resistor should be added as preload to prevent
budget.
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
leakage current from FB pin charging the output capacitors.
loss can be approximated.
1
× VIN × IOUT × TSW × FS
...(22)
2
where IOUT is output current, TSW is the sum of TR and TF
which can be found in mosfet datasheet, and FS is switching frequency. The result of PSW is 3W. Swithing loss
PSW is frequency dependent.
PSW =
Feedback Under Voltage Shut Down
NX2113 relies on the Feedback Under Voltage Lock
Out (FB UVLO ) to provide short circuit protection. Basically, NX2113 has a comparator compares the feedback voltage with the FB UVLO threshold 0.4V.
During the normal operation, if the output is short,
the feedback voltage will be lower than 0.4V and comparator will change the state. After certain internal delay,
Soft Start, Enable and shut Down
The NX2113 has a digital start up. It is based on
digital counter with 1024 cycles. For NX2113 with 300kHz
both high side and low side driver will be turned off. The
output will be latched. The normal operation should be
achieved by removing the short and recycle the VCC.
operation, the start up time is about 3.5ms. For NX2113A
During the start up, the output voltage is dis-
with 600kHz operation, the start up time is about half of
charged to zero by the synchronous FET. FB voltage
NX2113, 1.75mS.
starts increase from zero when digital start block
Rev. 2.0
11/18/05
15
NX2113/2113A
operates. Before half of the start up time, the Feedback
The Feedback UVLO can provide certain short cir-
Under Voltage Lock Out comparator is disabled. After
cuit protection. However, since feedback does not have
half of start up time, the Feedback UVLO comparator is
accurate information of current, this protection only pro-
enabled. The FB UVLO threshold is set to be half of
vides certain level of over current protection. MOSFET
voltage at the positive input of error amplifier. With this
should design such that it can survive with high pulse
set up, if the output is short before soft start, the
current for a short period of time.
Feedback UVLO comparator can catch it and turn off
The value of the capacitor on enable pin to ground
the driver. The short circuit operation waveform during
and the resistor value of voltage divider on enable pin
normal operation and during the soft start are shown as
should be big enough to keep enable pin high during
follows.
short. Otherwise, once output shorts, the input bus voltage drops, the chip is disabled before Feedback UVLO
takes effect, and the system goes into hiccup status.
This phenomena is easy to be found during system
startup, if related resistor and capacitor value is not big
CH3-FB voltage
0.5V/DIV
enough.
CH1-SW voltage
10V/DIV
CH4-load current
10A/DIV
CH2-Output voltage
1V/DIV
Figure 15 - Operation waveforms during short condition.
CH4-load current
10A/DIV
Figure 17 -Hiccup with start up at short.
CH2-output voltage
1V/DIV
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
CH4-load current
10A/DIV
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the
connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
Figure 16 - Feedback UVLO with start up at
short.
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to
Rev. 2.0
11/18/05
16
NX2113/2113A
reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more sensitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.
Rev. 2.0
11/18/05
17
NX2113/2113A
TYPICAL APPLICATION
Dual power supply (+5V BIAS,+12V BUS)
L2 1uH
Vin
C5
1uF
C4
47uF
C6
1uF
R5
10
Vin
+5V
C5
1uF
R5
1k
6
1
5
C7
0.1uF
Vcc PVcc BST
7
R6
1k
EN
9
C1
100pF
C2
10nF
Comp
8
Hdrv
M1
2
L1 4.7uH
SW
Ldrv
Fb
PGnd/Gnd
R4
10k
Cin
39uF,31mohm
D1
NX2113
+12V
10
Co
2 x (680uF,36mohm)
M2
4
Vout
+2.5V,4A
3
R1 10k 1%
R2
4.7k 1%
Figure 18 -Application of NX2113 for 5V bias and 12V input bus
Single power supply (+11V to +24V BUS)
L2 1uH
Vin
C4
47uF
R5
3k
C5
1uF
R8
76.8k
2N3904
R6
12.7k
R9
10k
TL431
6
5
1
C7
0.1uF
Vcc PVcc BST
7
9
C2
10nF
C1
100pF
D1
C8
1uF
R7
10k
R4
10k
8
EN
Comp
Hdrv
2
M1
L1 4.7uH
SW
Ldrv
Fb
10
4
M2
Vout
+1.6V,5A
Co
2 x (680uF,36mohm)
PGnd Gnd
3
R2
4.7k 1%
Cin
2 x (47uF,60mohm)
C6
1uF
R5
10
NX2113
+11~25V
11
R1 10k 1%
Figure 19 -Application of NX2113 for high input bus application
Rev. 2.0
11/18/05
18
NX2113/2113A
TYPICAL APPLICATION
Single Supply 5V Input
L2 1uH
Vin
+5V
C4
10uF
X7R
R5
10
D1
C6
1uF
C8
1uF
6
C5
1uF
1
5
C7
0.1uF
Vcc PVcc BST
9
R4
120k
C1
4.7pF
C2
330pF
8
EN
Hdrv
NX2113A
7
Comp
Fb
Cin
3 x 22uF
X7R
2
M1
L1 3.3uH
SW
Ldrv
10
4
M2
Co
10 x 22uF
X7R
Vout
+1.2V,4A
PGnd Gnd
11
3
R2
20k 1%
R1 10k 1%
R3
787
C3
820pF
Figure 20 - Application of NX2113 A for 5V input and 1.6V output with ceramic output capacitors
Rev. 2.0
11/18/05
19
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