Renesas HD74ALVC2G14 Triple schmitt-trigger inverter buffer Datasheet

HD74ALVC2G14
Triple Schmitt-trigger Inverter Buffers
REJ03D0165–0300Z
(Previous ADE-205-634B (Z))
Rev.3.00
Dec.17.2003
Description
The HD74ALVC2G14 has triple inverters with schmitt-trigger input in an 8 pin package. Low voltage and
high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low
power consumption extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Supply voltage range : 1.2 to 3.6 V
Operating temperature range: −40 to +85°C
• All inputs VIH (Max.) = 3.6 V (@VCC = 0 V to 3.6 V)
All outputs VO (Max.) = 3.6 V (@VCC = 0 V)
• Output current
±2 mA (@VCC = 1.2 V)
±4 mA (@VCC = 1.4 V to 1.6 V)
±6 mA (@VCC = 1.65 V to 1.95 V)
±18 mA (@VCC = 2.3 V to 2.7 V)
±24 mA (@VCC = 3.0 V to 3.6 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74ALVC2G14USE
SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)
Rev.3.00, Dec.18.2003, page 1 of 9
HD74ALVC2G14
Outline and Article Indication
• HD74ALVC2G14
Index band
Lot No.
Y M W
A 1 4
SSOP-8
Marking
Function Table
Input A
Output Y
H
L
L
H
H:
L:
High level
Low level
Rev.3.00, Dec.18.2003, page 2 of 9
Y : Year code
(the last digit of year)
M : Month code
W : Week code
HD74ALVC2G14
Pin Arrangement
1A
1
8
VCC
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
VCC
−0.5 to 4.6
V
Input voltage range *1
VI
−0.5 to 4.6
V
VO
−0.5 to VCC+0.5
V
Output voltage range
*1, 2
−0.5 to 4.6
Conditions
Output : H or L
VCC : OFF
Input clamp current
IIK
−50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
Continuous current through
VCC or GND
ICC or IGND
±100
mA
Maximum power dissipation
*3
at Ta = 25°C (in still air)
PT
200
mW
Storage temperature
Tstg
−65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.3.00, Dec.18.2003, page 3 of 9
HD74ALVC2G14
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
1.2
3.6
V
Input voltage range
VI
0
3.6
V
Output voltage range
VO
0
VCC
V
Output current
IOH

−2
mA

−4
VCC = 1.4 V

−6
VCC = 1.65 V

−18
VCC = 2.3 V

−24
VCC = 3.0 V

2
VCC = 1.2 V

4
VCC = 1.4 V

6
VCC = 1.65 V

18
VCC = 2.3 V

24
−40
85
IOL
Operating free-air temperature
Ta
Note: Unused or floating inputs must be held high or low.
Rev.3.00, Dec.18.2003, page 4 of 9
Conditions
VCC = 1.2 V
VCC = 3.0 V
°C
HD74ALVC2G14
Electrical Characteristics
(Ta = −40 to 85°C)
Item
Threshold voltage
Symbol
VT
VT
+
−
∆VT
Output voltage
VOH
VOL
VCC (V) *
Min
Typ
Max
Unit
1.2


VCC×0.8
V
1.4 to 1.6


VCC×0.75
1.65 to 1.95


VCC×0.7
2.3 to 2.7


1.7
3.0 to 3.6


2.0
1.2
VCC×0.2


1.4 to 1.6
VCC×0.25 

1.65 to 1.95
VCC×0.3


2.3 to 2.7
0.7


3.0 to 3.6
0.8


1.2
0.1

0.4
1.4 to 1.6
0.1

0.6
1.65 to 1.95
0.15

0.8
2.3 to 2.7
0.25

1.0
3.0 to 3.6
0.25

1.2
Min to Max
VCC−0.2


1.2
0.9


IOH = −2 mA
1.4
1.1


IOH = −4 mA
1.65
1.2


IOH = −6 mA
2.3
1.7


IOH = −18 mA
3.0
2.2


IOH = −24 mA
Min to Max


0.2
IOL = 100 µA
1.2


0.3
IOL = 2 mA
1.4


0.3
IOL = 4 mA
1.65


0.3
IOL = 6 mA
2.3


0.55
IOL = 18 mA
V
Test conditions
IOH = −100 µA
3.0


0.55
Input current
IIN
3.6


±5
µA
VIN = 3.6 V or GND
Quiescent supply
current
ICC
3.6


10
µA
VIN = VCC or GND,
IO = 0
Output leakage
current
IOFF
0


5
µA
VIN or VO =
0 to 3.6 V
Input capacitance
CIN
3.3

5.0

pF
VIN = VCC or GND
IOL = 24 mA
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
Rev.3.00, Dec.18.2003, page 5 of 9
HD74ALVC2G14
Switching Characteristics
(Ta = −40 to 85°C)
VCC = 1.2 V
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
FROM
(Input)
TO
(Output)
Propagation
delay time
tPLH
tPHL

7.0

ns
CL = 15 pF
A
Y
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
FROM
(Input)
TO
(Output)
Propagation
delay time
tPLH
tPHL
2.0

8.0
ns
CL = 15 pF
A
Y
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
FROM
(Input)
TO
(Output)
Propagation
delay time
tPLH
tPHL
1.5

6.0
ns
CL = 30 pF
A
Y
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
FROM
(Input)
TO
(Output)
Propagation
delay time
tPLH
tPHL
1.0

4.5
ns
CL = 30 pF
A
Y
Item
Symbol
Min
Typ
Max
Unit
Test
conditions
FROM
(Input)
TO
(Output)
Propagation
delay time
tPLH
tPHL
1.0

3.5
ns
CL = 30 pF
A
Y
VCC = 1.5±0.1 V
VCC = 1.8±0.15 V
VCC = 2.5±0.2 V
VCC = 3.3±0.3 V
Rev.3.00, Dec.18.2003, page 6 of 9
HD74ALVC2G14
Operating Characteristics
(Ta = 25°C)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test conditions
Power dissipation
CPD
1.5

10.5

pF
f = 10 MHz
1.8

10.5

2.5

12.0

3.3

13.0

capacitance
Test Circuit
VCC
Pulse
Generator
Input
Output
Z out = 50 Ω
CL
Symbol
RL
V CC = 1.2 V,
V = 2.5±0.2 V,
V = 1.8±0.15 V CC
1.5±0.1 V CC
3.3±0.3 V
RL
2.0 kΩ
1.0 kΩ
500 Ω
CL
15 pF
30 pF
30 pF
Note: CL includes probe and jig capacitance.
Rev.3.00, Dec.18.2003, page 7 of 9
HD74ALVC2G14
Waveforms
tr
tf
Input
VIH
90%
90%
V ref
V ref
10%
10%
t PHL
GND
t PLH
VOH
Output
V ref
V ref
VOL
Symbol
V CC = 1.2 V,
1.5±0.1 V, V CC = 2.5±0.2 V
1.8±0.15 V
V CC = 3.3±0.3 V
tr / t f
2.0 ns
2.5 ns
2.5 ns
V IH
VCC
VCC
2.7 V
V ref
50%
50%
1.5 V
Note: Input waveform : PRR = 10 MHz, duty cycle 50%
Rev.3.00, Dec.18.2003, page 8 of 9
HD74ALVC2G14
Package Dimensions
2.0 ± 0.2
1.5 ± 0.2
+ 0.1
(0.17)
8 − 0.2 − 0.05
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.3.00, Dec.18.2003, page 9 of 9
+ 0.1
0.13 − 0.05
0 − 0.1
0.7 ± 0.1 (0.4)
2.3 ± 0.1
(0.5) (0.5) (0.5)
3.1 ± 0.3
(0.4)
Unit: mm
TTP–8DBV


0.010 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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