PHILIPS HEF4514BP 1-of-16 decoder/demultiplexer with input latch Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4514B
MSI
1-of-16 decoder/demultiplexer with
input latches
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4514B
MSI
1-of-16 decoder/demultiplexer with input latches
last data present at An are stored in the latches and the
outputs remain stable. When E is LOW, the selected
output, determined by the contents of the latch, is HIGH.
At E HIGH, all outputs are LOW. The enable input (E) does
not affect the state of the latch. When the HEF4514B is
used as a demultiplexer, E is the data input and A0 to
A3 are the address inputs.
DESCRIPTION
The HEF4514B is a 1-of-16 decoder/demultiplexer, having
four binary weighted address inputs (A0 to A3), a latch
enable input (EL), and an active LOW enable input (E).
The 16 outputs (O0 to O15) are mutually exclusive active
HIGH. When EL is HIGH, the selected output is
determined by the data on An. When EL goes LOW, the
Fig.1 Functional diagram.
HEF4514BP(N):
24-lead DIL; plastic
HEF4514BD(F):
24-lead DIL; ceramic (cerdip)
(SOT101-1)
(SOT94)
HEF4514BT(D):
24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
APPLICATION INFORMATION
Some examples of applications for the HEF4514B are:
• Digital multiplexing.
PINNING
A0 to A3
address inputs
E
enable input (active LOW)
EL
latch enable input
O0 to O15
outputs (active HIGH)
• Address decoding.
• Hexadecimal/BCD decoding.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
1-of-16 decoder/demultiplexer with input latches
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
January 1995
3
HEF4514B
MSI
Philips Semiconductors
Product specification
HEF4514B
MSI
1-of-16 decoder/demultiplexer with input latches
TRUTH TABLE
INPUTS
OUTPUTS
E
A0
A1
A2
A3
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10 O11 O12 O13
O14
O15
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Notes
1. EL = HIGH; H = HIGH state (the more positive voltage);
L = LOW state (the less positive voltage); X = state is immaterial
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
An, EL → On
HIGH to LOW
LOW to HIGH
E → On
HIGH to LOW
LOW to HIGH
5
520
ns
233 ns
+
(0,55 ns/pF) CL
95
190
ns
84 ns
+
(0,23 ns/pF) CL
15
65
130
ns
57 ns
+
(0,16 ns/pF) CL
5
270
550
ns
243 ns
+
(0,55 ns/pF) CL
95
190
ns
84 ns
+
(0,23 ns/pF) CL
10
10
tPHL
tPLH
15
65
130
ns
57 ns
+
(0,16 ns/pF) CL
5
175
350
ns
148 ns
+
(0,55 ns/pF) CL
65
130
ns
54 ns
+
(0,23 ns/pF) CL
10
tPHL
15
45
90
ns
37 ns
+
(0,16 ns/pF) CL
5
200
400
ns
173 ns
+
(0,55 ns/pF) CL
70
140
ns
59 ns
+
(0,23 ns/pF) CL
50
100
ns
42 ns
+
(0,16 ns/pF) CL
10
tPLH
15
January 1995
260
4
Philips Semiconductors
Product specification
HEF4514B
MSI
1-of-16 decoder/demultiplexer with input latches
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Output transition
times
HIGH to LOW
LOW to HIGH
SYMBOL
5
ns
14 ns + (0,42 ns/pF) CL
50
ns
11 ns + (0,28 ns/pF) CL
5
85
170
ns
35 ns + (1,0 ns/pF) CL
35
70
ns
14 ns + (0,42 ns/pF) CL
25
50
ns
11 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
package (P)
ns
20
ns
30
15
ns
5
0
60
ns
0
20
ns
15
0
15
ns
5
120
60
ns
40
20
ns
30
15
ns
10
VDD
V
dissipation per
60
40
10
tsu
120
15
15
Dynamic power
40 ns + (1,0 ns/pF) CL
65
An → EL
width; HIGH
ns
25
5
Minimum EL pulse
180
35
Set-up time
An → EL
90
15
10
15
Hold time
TYPICAL EXTRAPOLATION
FORMULA
MIN. TYP. MAX.
thold
tWELH
see also waveforms
Fig.5
TYPICAL FORMULA FOR P (µW)
5
1100 fi + ∑ (foCL) × VDD2
where
10
5500 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
16 000 fi + ∑ (foCL) ×
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
1-of-16 decoder/demultiplexer with input latches
Fig.5
HEF4514B
MSI
Waveforms showing minimum pulse width for EL, set-up and hold times for An to EL. Set-up and hold
times are shown as positive values but may be specified as negative values.
January 1995
6
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