FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Features Description On Resistance Typically 4Ω, VDDH=2.7V Ftoggle: > 120MHz Low On Capacitance: 9pF Typical Low Power Consumption: 1µA Maximum Conforms to Secure Digital (SD), Secure Digital I/O The FSSD06 is a two-port multiplexer that allows Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to be expanded out to multiple cards or peripherals. This configuration enables the CMD, CLK, and D[3:0] signals to be multiplexed to dual-card peripherals. It is optimized for 1-bit / 4-bit SD / MMC applications. (SDIO), and Multimedia Card (MMC) Specifications Supports 1-Bit / 4-Bit Host Controllers (VDDH=1.65V to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V) - VDDH=1.65 to 3.6V, VDDC1/C2=VDDH to 3.6V The architecture includes the necessary bi-directional data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock path for the FSSD06 is a uni-directional buffer with an integrated pull-up for high-impedance mode. Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, portable GPS units, and printers. 24-Lead MLP (3.5 x 4.5mm) and UMLP Packages Applications IMPORTANT NOTE: Cell Phone, PDA, Digital Camera, Portable GPS LCD Monitor, Home Theater PC/TV, All-in-One For additional performance information, please contact [email protected]. Printer Analog Symbol Diagram VDDC1 /OE S Control VDDC2 VDDH 5 DAT[0:3], CMD 5 CLK 1DAT[0:3], 1CMD 5 V DD C1 V DD C 2 RP U RPU 2DAT[0:3], 2CMD 1CLK 2CLK GND Figure 1. Analog Symbol Diagram Ordering Information Part Number Operating Temperature Range Eco Status FSSD06BQX -40°C to +85°C Green 24-Lead Molded Leadless Package (MLP), JEDEC MO-220, 3.5 x 4.5mm Tape & Reel FSSD06UMX -40°C to +85°C Green 24-Lead Ultrathin Molded Leadless Package (UMLP) Tape & Reel Package Description Packing Method For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com FSSD06 — SD/SDIO and MMC Two-Port Multiplexer September 2008 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE DAT[2] 3 22 VDDC1 DAT[3] 4 21 1CLK CMD 5 20 1DAT[0] VDDH 6 19 GND 7 CLK 1DAT[3] 1CMD VDDC1 23 1DAT[2] 1DAT[3] 1CMD 24 /OE 1DAT[2] 1 DAT[2] /OE 2 24 23 22 21 20 19 DAT[3] 1 18 1CLK CMD 2 17 1DAT[0] 1DAT[1] VDDH 3 16 1DAT[1] 18 2DAT[2] GND 4 15 2DAT[2] 8 17 2DAT[3] CLK 5 14 2DAT[3] DAT[0] 9 16 2CMD DAT[0] 6 13 2CMD DAT[1] 10 15 VDDC2 2DAT[0] 2CLK Figure 3. 9 10 11 12 VDDC2 2DAT[1] MLP Pin Assignments 8 2CLK S Figure 2. 7 2DAT[0] 14 2DAT[1] 13 S 12 DAT[1] 11 UMLP Pin Assignments FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Pin Configuration Pin Definitions Name Description VDDH Power Supply (Host ASIC) VDDC1, VDDC2 Power Supply (SDIO Peripheral Card Ports) /OE Output Enable (Active Low) S Select Pin 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD SDIO Card Ports DAT[3:0], CMD SDIO Common Ports CLK, 1CLK, 2CLK Clock Path Ports Truth Table /OE S Function LOW LOW CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via RPU LOW HIGH CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via RPU HIGH X All Ports High Impedance; 1CLK, 2CLK pulled HIGH via RPU © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 2 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE VDDH 1.65 – 3.60V VDDC1 FSSD06 VDD H to 3.6V RT GND CMD, DAT[3:0] 1CMD, 1DAT[3:0] 5 5 Processor 1CLK Secure Data / Multimedia Card 2:1 Peripheral Expander CLK WiFi, Bluetooth, MMC or SD Module VDDC2 VDD H to 3.6V RT Note: External resistors (R T) are recommended if card supplies are allowed to float in the application. The resistors should be >500K to minimize power consumption. GND 2CMD, 2DAT[3:0] 5 2CLK /OE S GND Figure 4. WiFi,, Bluetooth, MMC or SD Module Typical Application Diagram Functional Description The FSSD06 enables sharing the ASIC/baseband processor SDIO port(s) to two peripheral cards, providing bi-directional support for dual-voltage SD/SDIO or MMC cards available in the marketplace. Each SDIO port of the FSSD06 has its own supply rail, allowing peripheral cards with different supplies to be interfaced to the host. The peripheral card supplies must be equal or greater than the host to minimize power consumption. The independent VDDH, VDDC1, and VDDC2 are defined by the supplies connected from the application Power Management ICs (PMICs) to the FSSD06. The clock path is a uni-directional buffered path rather than a bi-directional switch port. CLK Bus The 1CLK and 2CLK outputs are bi-state buffer architectures, rather than a switch I/O, to ensure 52MHz incident wave switching. When there is no communication on the bus (IDLE), the FSSD06 can be disabled with the /OE pin. When this pin is pulled HIGH, the nCLK outputs are also pulled HIGH. Along with nCMD, nDAT[3:0] goes high-impedance to ensure that the CLK path between the FSSD06 and the peripheral does not float. IDLE State CMD/DAT Bus “Parking” The SD and MMC card specifications were written for a direct point-to-point communication between host controller and card. The introduction of the FSSD06 in that path, as an expander, requires that the functional operation and system latency not be impacted by the FSSD06 switch characteristics. Since there are various card formats, protocols, and configurable controllers, a /OE pin is available to facilitate a fast IDLE transition for the nCMD/nDAT[3:0] outputs. Some controllers, rather than simply placing CMD/DAT into high-impedance mode, may pull their outputs HIGH for a clock cycle prior to going into high-impedance mode (referred to as “parking” the output). Some legacy controllers pull their outputs HIGH versus high impedance. CMD, DAT Bus Pull-ups The 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] ports do not have, internally, the system pull-up resistors as defined in the MMC or SD card system bus specifications. The system bus pull-up must be added external to the FSSD06. The value, within the specific specification limits, is a function of the individual application and type of card or peripheral connected. For SD card applications, the RCMD and RDAT pull-ups should be between 10kΩ and 100kΩ. For MMC applications, the RCMD pull-ups should be between 4.7kΩ and 100kΩ and the RDAT pull-ups between 50kΩ and 100kΩ. The card-side 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistors ensure retention of the output high level. If the /OE pin is left LOW and the controller places the CMD/DAT[3:0] outputs into high impedance, the nCMD/nDAT[3:0] output rise time is a function of the RC time constant through the switch path. It is recommended that the host controller pull CMD and DAT[3:0] HIGH for one cycle before pulling /OE HIGH. This facilitates parking all nCMD/nDAT[3:0] outputs HIGH before putting the switch I/Os in high impedance. The /OE pin can be used to place the 1CMD, 2CMD, 1DAT[3:0] and 2DAT[3:0] into high-impedance mode when the system enters IDLE state (see IDLE State CMD/DAT Bus “Parking”). © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Typical Application Diagram www.fairchildsemi.com 3 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VDDH Supply Voltage VDDC1,VDDC2 Supply Voltage VSW (1) (1) VCNTRL (1) VCLKI Conditions Min. Max. Unit -0.5 4.6 V V -0.5 4.6 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins -0.5 VDDx + 0.3V (4.6V maximum) DAT[3:0], CMD Pins -0.5 VDDx + 0.3V (4.6V maximum) V Control Input Voltage S, /OE -0.5 4.6 V CLK Input Voltage CLK -0.5 4.6 V -0.5 VDDx + 0.3V (4.6V maximum) Switch I/O Voltage (2) (2) (1) VCLKO V (2) CLK Output Voltage 1CLK, 2CLK V IINDC Input Clamp Diode Current -50 mA ISW Switch I/O Current SDIO Continuous 50 mA Peak Switch Current SDIO Pulsed at 1ms Duration, <10% Duty Cycle 100 mA +150 °C ISWPEAK TSTG Storage Temperature Range TJ Max Junction Temperature TL Lead Temperature ESD Human Body Model (JEDEC: JESD22-A114) -65 Soldering, 10 Seconds +150 °C +260C °C I/O to GND 8 Supply to GND 9 All Other Pins 5 Charged Device Model (JEDEC: JESD22-C101) FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Absolute Maximum Ratings kV 2 kV Notes: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 2. VDDx references the specific SDIO port VDD rail (i.e. VDDC1, VDDC2, VDDH). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Minimum Maximum Unit Supply Voltage - Host Side 1.65 3.6V V VDDC1, VDDC2 Supply Voltage - SDIO Cards VDDH 3.6V V VCNTRL Control Input Voltage - VS,V/OE 0 VDDH V Clock Input Voltage - VCLKI 0 VDDH V Switch I/O Voltage - CMD, DAT[3:0] 0 VDDH V Switch I/O Voltage - 1CMD, 1DAT[3:0] 0 VDDC1 V Switch I/O Voltage - 2CMD, 2DAT[3:0] 0 VDDC2 V -40 +85 °C 50 °C/W VDDH VCLKI VSW Parameter °C Operating Temperature θJA Thermal Resistance (free air), MLP24 © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 4 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE All typical values are for VDDH=1.8V at 25°C unless otherwise specified. Symbol VDDC1 / VDDC2 (V) Parameter TA=- 40°C to +85°C Conditions Min. Typ. Unit Max. Common Pins VIK Clamp Diode Voltage 2.7 IIK=-18mA VIH Control Input Voltage High 2.7 VIL Control Input Voltage Low 2.7 IIN S, /OE Input High Current 3.6 VDDH=1.95V, VCNTRL=0V to VDDH IOZ Off Leakage, Current of all ports 3.6 VDDH=1.95V, VSW =0V to VDDX IPU CLK Pull-up Current 3.6 VCLKI=VDDH VCLKO=0V, /OE=VDDH VOHC CLK Output Voltage High 2.7 IOH=-2mA VOLC CLK Output Voltage Low 3.6 IOL=-2mA RPU CLK Pull-up (3) Resistance RON Switch On Resistance ∆RON Delta On Resistance -1.2 1.3 V VDDH=1.65V 0.5 -1 -1.0 0.5 1 µA 1.0 µA 35 µA V 2.4 90 50 100 (4) 2.7 VCMD, DAT[3:0]=0V, ION=-2mA, See Figure 5 4 (4, 5) 2.7 VCMD, DAT[3:0]=0V, ION=- 2mA 0.8 mV FSSD06 — SD/SDIO and MMC Two-Port Multiplexer DC Electrical Characteristics at 1.8V VDDH kΩ 6 Ω Ω Power Supply ICC(VDDH) ICC(VDDC1, VDDC2) ∆ICARD Quiescent Supply Current (Host) Quiescent Supply Current (SDIO Cards) Delta ICC(VDDC1, VDDC2) for One Card Powered Off VDDH=1.95V, VSW=0 or VDDH, IOUT=0 1 µA 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA 3.6V / 0V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA 0 Notes: 3. Guaranteed by characterization, not production tested. 4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 5. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 5 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE All typical values are for VDDH=2.7V at 25°C unless otherwise specified. Symbol VDDC1 / VDDC2 (V) Parameter TA=- 40°C to +85°C Conditions Min. Typ. Unit Max. Common Pins VIK Clamp Diode Voltage 2.7 VIH Control Input Voltage High 2.7 VIL Control Input Voltage Low 2.7 IIN S, /OE Input High Current 3.6 IOZ Off Leakage Current of all ports 3.6 IPU CLK Pull-up Current VOHC IIK=-18mA -1.2 1.8 V VDDH=2.7V 0.8 VDDH=3.6V, VCNTRL=0V to VDDH VDDH=3.6V, VSW =0V to VDDX 3.6 VCLKI=VDDH, VCLKO=0V, /OE=VDDH CLK Output Voltage High 2.7 IOH=-2mA VOLC CLK Output Voltage Low 3.6 IOL=-2mA RPU CLK Pull-up (6) Resistance RON Switch On Resistance ∆RON Delta On Resistance -1 -1.0 0.5 1 µA 1.0 µA 50 µA V 2.4 90 50 100 mV FSSD06 — SD/SDIO and MMC Two-Port Multiplexer DC Electrical Characteristics at 2.7V VDDH kΩ (7) 2.7 VCMD, DAT[3:0]=0V, ION=-2mA See Figure 5 2.5 (7,8) 2.7 VCMD, DAT[3:0]=0V, ION=- 2mA 0.8 0 VDDH=3.6V, VSW=0 or VDDH, IOUT=0 1 µA 3.6 VSW=0 or VDDx, IOUT=0, VCLKI=VDDH , VCLKO=Open, /OE=0V 1 µA 3.6V/0V 0V/3.6V VSW=0 or VDDx, IOUT=0, VCLKI=VDDH, VCLKO=Open, /OE=0V 1 µA 6.0 Ω Ω Power Supply ICC(VDDH) ICC(VDDC1, VDDC2) ∆ICARD Quiescent Supply Current (Host) Quiescent Supply Current (SDIO Cards) Delta ICC(VDDC1, VDDC2) for One Card Powered Off Notes: 6. Guaranteed by characterization, not production tested. 7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch. 8. ∆RON=RON max – RON min measured at identical VCC, temperature, and voltage. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 6 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE All typical values are for VDDH=1.8V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) Conditions TA=- 40°C to +85°C Min. Unit Typ. Max. tON1 Turn-On Time, S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 24 ns tOFF1 Turn-Off Time, S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 7 22 ns Switch Propagation (9) Delay 2.7 to 3.6 See Figure 9 1 ns Switch Skew CMD, DAT[3:0] 2.7 to 3.6 RL=1kΩ, CL=30pF 2 ns tON2 Turn-On Time, S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 17 35 ns tOFF2 Turn-Off Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 28 ns tPDCLK Clock Propagation Delay 2.7 to 3.6 RL=1kΩ, CL=30pF See Figure 11 3.0 5.5 ns OIRR Off Isolation 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF, See Figure 12 -60 dB Xtalk Non-Adjacent Channel (9) Crosstalk 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF, See Figure 13 -60 dB ftoggle Clock Frequency 2.7 to 3.6 CL=30pF 120 MHz tPD (9, 10) tSKEW (9) (9) FSSD06 — SD/SDIO and MMC Two-Port Multiplexer AC Electrical Characteristics at 1.8V VDDH Notes: 9. Guaranteed by characterization, not production tested. 10. Skew is determined by |TPLH - TPHL | for worst-case temperature and VDDX. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 7 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE All typical values are for VDDH=2.7V at 25°C unless otherwise specified. Symbol Parameter VDDC1 / VDDC2 (V) TA=- 40°C to +85°C Conditions Unit Min. Typ. Max. tON1 Turn-On Time S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 8 17 ns tOFF1 Turn-Off Time S, /OE to CMD, DAT[3:0] 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 6 13 ns Switch Propagation (11) Delay 2.7 to 3.6 See Figure 9 1 ns Switch Skew CMD, DAT[3:0] 2.7 to 3.6 RL=1kΩ, CL=30pF 1.5 ns tON2 Turn-On Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 15 25 ns tOFF2 Turn-Off Time S, /OE to 1CLK, 2CLK 2.7 to 3.6 VSW =0V, RL=1kΩ, CL=30pF See Figure 7, Figure 8 10 25 ns tPDCLK Clock Propagation Delay 2.7 to 3.6 RL=1kΩ, CL=30pF See Figure 11 1.5 3.0 ns OIRR Off Isolation 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF See Figure 12 -60 dB Xtalk Non-Adjacent Channel (11) Crosstalk 2.7 to 3.6 f=10MHz, RT=50Ω, CL=30pF See Figure 13 -60 dB 2.7 to 3.6 CL=30pF 120 MHz tPD (12) tSKEW ftoggle (11) (11) Clock Frequency FSSD06 — SD/SDIO and MMC Two-Port Multiplexer AC Electrical Characteristics at 2.7V VDDH Notes: 11. Guaranteed by characterization, not production tested. 12. Skew is determined by |TPLH - TPHL | for worst-case temperature and VDDX. Capacitance Symbol Parameter Conditions TA=- 40°C to +85°C Min. Typ. Control and CLK Pin Input Capacitance VDDH=0V 2.5 CON Common Port On Capacitance (CDAT[3:0], CMD) VDDH=1.8V,VDDC1=VDDC2=2.7V, V/OE=0V, Vbias=0V, f=1MHz See Figure 15 9.0 COFF Input Source Off Capacitance VDDH=1.8V,VDDC1=VDDLH2=2.7V, V/OE=3.3V, Vbias=0V, f=1MHz See Figure 14 4.0 CIN (S, /OE, CLK) © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 Unit Max. pF www.fairchildsemi.com 8 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE V ON nDAT[3:0],nCMD I OZ NC DAT[3:0],CMD A V IN GND RON = Select Figure 5. Select GND VS = V ddl 0 orV VS = VON / ION V IN I ON On Resistance Figure 6. GND 0 orV V ddl Off Leakage (Each Switch Port is Tested Separately) V DDx tRISE = 2.5ns DAT[3:0], CMD nDAT[3:0],nCMD RL VSW Vddx V OUT CL RS GND tFALL = 2.5ns Input - VCNTRL 10% GND GND 90% 90% V ddx /2 V ddx /2 10% VOH VS Output - VOUT GND VOL RL , RS , and C L are function of application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance Figure 7. FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Test Diagrams 50% Vol + 0.15V tON t OFF AC Test Circuit Load Figure 8. Turn On/Off Time Waveforms V DDx tRISE = 2.5ns tFALL = 2.5ns CLK 1CLK, 2CLK Vddx Input - VSW 10% GND 90% Vddx /2 90% V ddx/2 10% GND VOL Figure 9. V OUT CL RS GND VOH Output-- VOUT RL VCLKI tpLH VS 50% 50% GND tpHL RL , RS , and CL are function of application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance Switch Propagation Delay Waveform © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 Figure 10. AC Test Circuit Load (CLK) www.fairchildsemi.com 9 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE tRISE = 2.5ns t FALL = 2.5ns Network Analyzer RS Vddx 90% Input - VCLKI V ddx /2 10% GND 90% V ddx /2 10% VS VOHC VOLC tpLH VS GND V OUT GND RT RS and R T are function of application environment (see AC Tables for specific values) 50% 50% V IN GND GND Output - VCLKO Figure 11. GND RT tpHL GND Off -Isolation = 20 Log (VOUT / VIN ) CLK Propagation Delay Waveforms Figure 12. Channel Off Isolation Network Analyzer NC RS V IN GND VS VS FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Test Diagrams (Continued) GND GND RT GND GND RT VOUT RS and RT are function of application environment GND (see AC Tables for specific values) CROSSTALK = 20 Log (VOUT / VIN ) Figure 13. Channel-to-Channel Crosstalk nDAT[3:0], nCMD, nCLK Capacitance Meter S Capacitance Meter VS = 0 orVddh f = 1MHz, Vbias = 0V S VS = 0 or Vddh f = 1MHz,Vbias = 0V nDAT[3:0], nCMD, nCLK nDAT[3:0], nCMD, nCLK Figure 14. Channel Off Capacitance © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 Figure 15. Channel On Capacitance www.fairchildsemi.com 10 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE Package Designator Tape Selection Number Cavities Cavity Status Cover Tape Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed MPX Tape Dimensions Dimensions are in millimeters unless otherwise noted. FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Tape and Reel Specifications Reel Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Tape Size A 13.000 0.059 0.512 0.795 2.165 0.488 0.724 (12.00mm) (330.00) (1.50) (13.00) (20.00) (55.00) (12.40) (18.40) © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 B C D N W1 W2 www.fairchildsemi.com 11 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Physical Dimensions Figure 16. 24-Lead Molded Leadless Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 12 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE 2.80 2.23 0.66 0.10 C A 2.50 2X 24 B 0.56 19 1 0.40 2.23 PIN #1 IDENT 3.70 3.40 13 0.10 C 7 0.23 2X TOP VIEW RECOMMENDED LAND PATTERN 0.55 MAX. 0.10 C 0.15 SEATING PLANE 0.08 C C 0.05 0.00 SIDE VIEW FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Physical Dimensions 7 23X 0.35 0.45 13 0.40 1 0.45 0.55 24 19 BOTTOM VIEW Figure 17. 0.15 24X 0.25 0.10 C A B 0.05 C 24-Lead Ultrathin Molded Leadless Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 13 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE FSSD06 — SD/SDIO and MMC Two-Port Multiplexer © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 14