MOTOROLA MCM72F6ADG12 512kb and 1mb synchronous fast static ram module Datasheet

MOTOROLA
Order this document
by MCM72F6A/D
SEMICONDUCTOR TECHNICAL DATA
512KB and 1MB Synchronous
Fast Static RAM Module
The MCM72F6A (512KB) is configured as 64K x 72 bits and the MCM72F7A
(1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual–
in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit
flow–through BurstRAMs.
Address (A), data inputs (DQ, DP), and all control signals except output enable
(G) are clock (K) controlled through positive–edge–triggered noninverting registers.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W) allows writes to either individual bytes or to
both bytes.
MCM72F6A
MCM72F7A
168–LEAD DIMM
CASE 1115J–01
TOP VIEW
1
11
•
•
•
•
•
•
•
•
Single 3.3 V + 10%, – 5% Power Supply
Plug and Pin Compatibility with 2MB and 4MB
Multiple Clock Pins for Reduced Loading
All Inputs and Outputs are LVTTL Compatible
Byte Write Capability
Fast SRAM Access Times: 9/10/12 ns
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground
Planes
• Amp Connector, Part Number: 390064–4
• 5 V Tolerant on All Pins (Inputs and I/Os)
• 168–Pin DIMM Module
40
41
84
1/29/98

Motorola, Inc. 1998
MOTOROLA
FAST SRAM
MCM72F6A•MCM72F7A
1
MCM72F6A BLOCK DIAGRAM
E0
G0
A0 – A15
ADSP
W0
W1
K0
VDD
VSS
DQ0 – DQ7
DP0
DQ8 – DQ15
DP1
MCM72F6A•MCM72F7A
2
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ16 – DQ23
DP2
DQ24 – DQ31
DP3
W2
W3
K1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ32 – DQ39
DP4
DQ40 – DQ47
DP5
W4
W5
K2
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
W6
W7
K3
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ48 – DQ55
DP6
DQ56 – DQ63
DP7
MOTOROLA FAST SRAM
MCM72F7A BLOCK DIAGRAM
VSS
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ0 – DQ7
DP0
DQ8 – DQ15
DP1
DQ16 – DQ23
DP2
DQ24 – DQ31
DP3
E0
G0
A0 – A15
ADSP
W0
W1
K0
VDD
VDD
VSS
E1
G1
MOTOROLA FAST SRAM
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
W2
W3
K1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ32 – DQ39
DP4
DQ40 – DQ47
DP5
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
W4
W5
K2
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
W6
W7
K3
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ48 – DQ55
DP6
DQ56 – DQ63
DP7
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
MCM72F6A•MCM72F7A
3
PIN ASSIGNMENT
168–LEAD DIMM
TOP VIEW
VSS
DQ63
DQ62
VDD
DQ60
DQ58
VSS
DQ56
DQ55
VSS
1
2
3
4
5
6
7
8
9
10
85
86
87
88
89
90
91
92
93
94
VSS
DP7
DQ61
VSS
DQ59
DQ57
VSS
DP6
DQ54
VDD
DQ53
DQ51
VSS
DQ49
DP5
VDD
DQ46
DQ44
VSS
DQ42
DQ40
VSS
DQ39
DQ37
VSS
DQ35
DQ33
VSS
K3
VSS
DP3
DQ30
VDD
DQ28
DQ26
VSS
DQ24
DQ23
VSS
DQ21
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ52
DQ50
VSS
DQ48
DQ47
VSS
DQ45
DQ43
VSS
DQ41
DP4
VDD
DQ38
DQ36
VSS
DQ34
DQ32
VSS
K2
VSS
DQ31
DQ29
VSS
DQ27
DQ25
VSS
DP2
DQ22
VDD
DQ20
MCM72F6A•MCM72F7A
4
DQ19
VSS
DQ17
DP1
VDD
DQ14
DQ12
VSS
DQ10
DQ8
VSS
DQ7
DQ5
VSS
DQ3
DQ1
VDD
NC
NC
VSS
NC
A14
VSS
A12
A10
VSS
A8
A6
VDD
A4
A2
A0
VSS
K1
VSS
W7
W5
VSS
W3
W1
VSS
G1
E1
VSS
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ18
VSS
DQ16
DQ15
VSS
DQ13
DQ11
VSS
DQ9
DP0
VDD
DQ6
DQ4
VSS
DQ2
DQ0
VSS
NC
NC
VSS
A15
A13
VDD
A11
A9
VSS
A7
A5
VSS
A3
A1
ADSP
VSS
K0
VSS
W6
W4
VSS
W2
W0
VDD
G0
E0
VSS
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
72, 155, 71, 154, 70, 152,
68, 151, 67, 149, 65, 148,
64, 146, 62, 145
A0 – A15
Input
Synchronous Address Inputs: These inputs are registered and must meet
setup and hold times.
156
ADSP
Input
Synchronous Addresss Status Controller: Initiates read, write, or chip
deselect cycle.
134, 44, 121, 31,
105, 15, 92, 86
DP0 – DP7
140, 56, 139, 55, 137, 53,
136, 52, 50, 133, 49, 131,
47, 130, 46, 128, 127, 43,
125, 41, 124, 40, 122, 38,
37, 119, 35, 118, 34, 116,
32, 115, 111, 27, 110, 26,
108, 24, 107, 23, 21, 104,
20, 102, 18, 101, 17, 99,
98, 14, 96, 12, 95, 11, 93,
9, 8, 90, 6, 89, 5, 87, 3, 2
DQ0 – DQ63
I/O
167, 83
E0, E1
Input
Synchronous Chip Enable: Active low to enable chip. Negated high —
deselects chip when ADSP is asserted. E1 is only used on 1MB module.
166, 82
G0, G1
Input
Asynchronous Output Enable Input:
Low — enables output buffer.
High — DQx pins are high impedance.
G1 is only used on 1MB module.
158, 74, 113, 29
K0 – K3
Input
Clock: This signal registers the address, data in, and all control signals
except G0 and G1.
164, 80, 163, 79, 161,
77, 160, 76
W0 – W7
Input
Synchronous Byte Write Inputs.
4, 16, 33, 45, 57, 69, 94,
106, 123, 135, 147, 165
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.
1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,
88, 91, 97, 100, 103, 109,
112, 114, 117, 120, 126, 129,
132, 138, 141, 144, 150, 153,
157, 159, 162, 168
VSS
Supply
Ground.
58, 59, 61, 142, 143
NC
Description
Synchronous Parity Data Inputs/Outputs.
Synchronous Data Inputs/Outputs.
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
Next Cycle
Address Used
Ex
ADSP
Gx
DQx
WRITE
Deselect
None
1
0
X
High–Z
X
Begin Read
External Address
0
0
0
DQ
Read
Read
Current
X
1
1
High–Z
Read
Read
Current
X
1
0
DQ
Read
Begin Write
External
0
0
X
High–Z
Write
Write
Current
X
1
X
High–Z
Write
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. Write is defined as any Wx low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
MOTOROLA FAST SRAM
MCM72F6A•MCM72F7A
5
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
Voltage Relative to VSS
Vin, Vout
– 0.5 to + 6.0
V
Output Current (per I/O)
Iout
± 20
mA
PD
4.6
9.2
W
Tbias
– 10 to + 85
°C
Tstg
– 55 to + 125
°C
Power Supply Voltage
Power Dissipation
MCM72F6A
MCM72F7A
Temperature Under Bias
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VDD
3.135
3.6
V
Input High Voltage
VIH
2.0
5.5**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Parameter
* VIL ≥ – 2.0 V for t ≤ tKHKH/2.
** VIH ≤ 6 V for tKHKH/2.
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Parameter
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(O)
—
± 1.0
µA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
POWER SUPPLY CURRENTS
Parameter
AC Supply Current (Device Selected, All Outputs Open,
Cycle Time ≥ tKHKH min)
CMOS Standby Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at
CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
Clock Running Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH, All Other Inputs
Held to Static CMOS Levels Vin ≤ VSS + 0.2 V
or ≥ VDD – 0.2 V)
Symbol
Min
Max
Unit
MCM72F6ADG9
MCM72F6ADG10
MCM72F6ADG12
MCM72F7ADG9
MCM72F7ADG10
MCM72F7ADG12
IDDA
—
900
860
840
1800
1720
1680
mA
MCM72F6ADG9
MCM72F6ADG10
MCM72F6ADG12
MCM72F7ADG9
MCM72F7ADG10
MCM72F7ADG912
ISB1
—
440
400
380
880
800
760
mA
MCM72F6ADG9
MCM72F6ADG10/12
MCM72F7ADG9
MCM72F7ADG10/12
ISB2
—
160
140
320
280
mA
MCM72F6A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
I/O Capacitance
MCM72F6A•MCM72F7A
6
W, K
Other Inputs
Symbol
Typ
Max
Unit
Cin
—
—
16
36
pF
CI/O
—
19
pF
MOTOROLA FAST SRAM
MCM72F7A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
W, K
E, G
Other Inputs
I/O Capacitance
Symbol
Typ
Max
Unit
Cin
—
—
—
22
36
60
pF
CI/O
—
28
pF
MASS (Periodically Sampled Rather Than 100% Tested)
Max
Unit
MCM72F6A
Parameter
16
g
MCM72F7A
20
g
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM72F6A–9
MCM72F7A–9
MCM72F6A–10
MCM72F7A–10
MCM72F6A–12
MCM72F7A–12
Symbol
S b l
Min
Max
Min
Max
Min
Max
Unit
U i
Cycle Time
tKHKH
12
—
15
—
16.6
—
ns
Clock High Pulse Width
tKHKL
4
—
5
—
6
—
ns
Clock Low Pulse Width
tKLKH
4
—
5
—
6
—
ns
Clock Access Time
tKHQV
—
9
—
10
—
12
ns
Output Enable to Output Valid
tGLQV
—
5
—
5
—
6
ns
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
ns
5
Clock High to Output Change
tKHQX2
3
—
3
—
3
—
ns
5
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
5
Output Disable to Q–High–Z
tGHQZ
—
5
—
5
—
6
ns
5, 6
Clock High to Q–High–Z
5, 6
Parameter
P
tKHQZ
3
5
3
5
3
6
ns
Setup Times
Address
ADSP
Data In
Write
Chip Enable
tAVKH
tADKH
tDVKH
tWVKH
tEVKH
2.5
—
2.5
—
2.5
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
ns
Notes
N
NOTES:
1. In setup and hold times, write refers to any Wx low.
2. Chip Enable is defined as Ex low, whenever ADSP is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
MOTOROLA FAST SRAM
MCM72F6A•MCM72F7A
7
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.
Z0 = 50 Ω
OUTPUT
50 Ω
VL = 1.5 V
Figure 1. AC Test Load
READ/WRITE CYCLES
t KHKH
t KHKL
t KLKH
K
Ax
A
B
C
D
E
F
G
ADSP
E
W
G
t KHQV
Q(n)
DQx
Q(A)
t KHQZ
t KHQX2
Q(B)
Q(C)
t GHQZ
t GLQV
D(D)
D(E)
D(F)
t KHQX1
DESELECTED
Q(G)
t GLQX
READ
WRITES
READ
ORDERING INFORMATION
(Order by Full Part Number)
MCM
72F
X
A
XX
XX
Motorola Memory Prefix
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Part Number
Package (DG = Gold Pad DIMM)
Module Revision
Memory Size (6A = 512KB, 7A = 1 MB)
Full Part Numbers — MCM72F6ADG9
MCM72F7ADG9
MCM72F6A•MCM72F7A
8
MCM72F6ADG10
MCM72F7ADG10
MCM72F6ADG12
MCM72F7ADG12
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
168–LEAD DIMM
CASE 1115J–01
D1
0.15 (0.006)
A B C
M
E
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉ
CL
D5
(DATUM PLANE C)
A1
COMPONENT
AREA
A
1
NOTE 4
84
10
11
40
VIEW C
D4
A
41
E2
VIEW B
D6
D4
NOTE 5
E1
D3
VIEW C
D2 /2
VIEW D
0.016 (0.4)
M
B
D2
FRONT VIEW
SIDE VIEW
É
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ É
É
ÉÉ
94
NOTE 6
95
85
168
COMPONENT
AREA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS E AND A1 DEFINE A
DOUBLE–SIDED MODULE.
5. DIMENSION E2 DEFINES OPTIONAL
SINGLE–SIDED MODULE
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
7. D5 DIMENSION DEFINES SLOT END AND EDGE
OF COMPONENT AREA.
BACK VIEW
R
R
A5
A5
K
0.004 (0.1)
C
A B C
M
K
0.004 (0.1)
VIEW A
A B C
M
VIEW B
b
0.004 (0.1)
ÉÉÉ
ÉÉ
ÉÉ
É
168X
162X
VIEW D
M
L1
1
168X
e
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
R
168X
L
A B C
2X
0.004 (0.1)
2X
A3
M
2X
A B C
A2
84
2X
VIEW C
MOTOROLA FAST SRAM
A4
P
0.004 (0.1)
M
DIM
A
A1
A2
A3
A4
A5
b
D1
D2
D3
D4
D5
D6
e
E
E1
E2
K
L
L1
P
INCHES
MIN
MAX
1.095
1.105
0.390
–––
0.118 BSC
0.700 BSC
0.154
0.161
0.118
0.128
0.037
0.041
5.245
5.255
5.014 BSC
1.700 BSC
0.250 BSC
0.118
–––
0.125 BSC
0.050 BSC
–––
0.200
0.046
0.054
–––
0.148
0.075
0.083
0.100
–––
–––
0.010
0.114
0.122
MILLIMETERS
MIN
MAX
27.81
28.07
9.90
–––
3.00 BSC
17.78 BSC
3.90
4.10
3.00
3.25
0.95
1.05
133.22 133.48
127.35 BSC
43.18 BSC
6.35 BSC
3.00
–––
3.175 BSC
1.27 BSC
–––
4.00
1.17
1.37
–––
2.70
1.90
2.10
2.54
–––
–––
0.25
2.90
3.10
A B C
MCM72F6A•MCM72F7A
9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax : [email protected] – TOUCHTONE 1-602-244-6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
– US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
– http://sps.motorola.com /mfax /
HOME PAGE : http://motorola.com/sps /
CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM72F6A•MCM72F7A
10
◊
MCM72F6A/D
MOTOROLA FAST
SRAM
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