PHILIPS HEF4068BN 8-input nand gate Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4068B
gates
8-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4068B
gates
8-input NAND gate
DESCRIPTION
The HEF4068B provides the 8-input NAND function. The
outputs are fully buffered for highest noise immunity and
pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4068BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4068BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4068BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram.
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4068B
gates
8-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
95
195
ns
68 ns + (0,55 ns/pF) CL
40
85
ns
29 ns + (0,23 ns/pF) CL
30
65
ns
22 ns + (0,16 ns/pF) CL
Propagation delays
In → O
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition times
HIGH to LOW
5
10
tTHL
15
5
LOW to HIGH
10
15
VDD
V
Dynamic power
5
tTLH
80
165
ns
53 ns + (0,55 ns/pF) CL
35
70
ns
24 ns + (0,23 ns/pF) CL
30
60
ns
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
TYPICAL FORMULA FOR P (µW)
700 fi + ∑(foCL) × VDD2
dissipation per
10
2900 fi + ∑(foCL) ×
package (P)
15
7200 fi + ∑(foCL) ×
VDD2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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