WED9LC6416V 128Kx32 SSRAM/4Mx32 SDRAM Advanced* External Memory Solution for Texas Instruments TMS320C6000 DSP FEATURES DESCRIPTION ■ Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz The WED9LC6416VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. ■ DSP Memory Solution • Texas Instruments TMS320C6201 The WED9LC6416VxxBC provides a total memory solution for the Texas Instruments TMS320C6201 and the TMS320C6701 DSPs • Texas Instruments TMS320C6701 ■ Packaging: The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . • 153 pin BGA, JEDEC MO-163 ■ 3.3V Operating supply voltage The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port . ■ Direct control interface to both the SSRAM and SDRAM ports on the “C6x” ■ Common address and databus The WED9LC6416V is available in both commercial and industrial temperature ranges. ■ 65% space savings vs. monolithic solution ■ Reduced system inductance and capacitance FIG. 1 * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. PIN CONFIGURATION TOP VIEW PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 A DQ19 DQ23 VCC VSS VSS VSS VCC DQ24 DQ28 A B DQ18 DQ22 VCC VSS SDCE VSS VCC DQ25 DQ29 B C VCCQ VCCQ VCC NC VCC VCCQ VCCQ C D DQ17 DQ21 VCC VSS VSS VSS VCC DQ26 DQ30 D E DQ16 DQ20 VCC VSS SDCLK VSS VCC DQ27 DQ31 E F VCCQ VCCQ VCC G NC NC NC SDWE SDA10 A0-16 VSS VSS SDRAS SDCAS VSS VCC VCCQ VCCQ F VSS A2 A4 A5 G Address Bus DQ0-31 Data Bus SSCLK SSRAM Clock SSADC SSRAM Address Status Control SSWE SSRAM Write Enable SSOE SSRAM Output Enable SDCLK SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe H NC NC A8 VSS VSS NC A1 A3 A10 H SDRAS J A6 A7 A9 VSS VSS NC A0 A11 A12 J SDCAS K SDWE SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 K NC / A17 NC / A18 NC / A19 VSS VSS NC NC A13 A14 L NC NC NC BWE2 BWE3 NC NC A15 A16 L SDA10 M VCCQ VCCQ VCC BWE0 BWE1 NC VCC VCCQ VCCQ M BWE0-3 N DQ12 DQ11 VCC VSS VSS VSS VCC DQ4 DQ0 N P DQ13 DQ10 VCC VSS SSCLK VSS VCC DQ5 DQ1 P R VCCQ VCCQ VCC T DQ14 DQ9 VCC U VSS VSS SSADC SSWE Chip Enable SSRAM Device Chip Enable SDRAM Device VSS VCC VCCQ VCCQ R NC VCC DQ6 DQ2 T VCC Power Supply pins, 3.3V U VCCQ Data Bus Power Supply pins, 3.3V (2.5V future) DQ15 DQ8 VCC SSOE SSCE NC VCC DQ7 DQ3 1 2 3 4 5 6 7 8 9 January 20001 SSCE SDCE 1 VSS Ground NC No Connect White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 2 BLOCK DIAGRAM A0-16 A0 A1 SSWE BWE0 BWE1 BWE2 BWE3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ9-16 DQ17-24 DQ25-32 DQ0-7 DQ8-15 DQ16-23 DQ24-31 BWE BW1 BW2 BW3 BW4 SSCE SSOE SSADC CE2 OE ADSC SSCLK CLK SDA10 DQ1-8 A12 A13 SDCE SDRAS SDCAS SDWE SDCLK A12 A13 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com DQ0-31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK DQ0-7 DQ8-15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM UDQM CS RAS CAS WE CLK DQ0-7 DQ8-15 2 DQ0-7 DQ8-15 DQ16-23 DQ24-31 January 2001 WED9LC6416V OUTPUT FUNCTIONAL DESCRIPTIONS Symbol Type Signal SSCLK Input Pulse SSADS SSOE SSWE Input Pulse Polarity Function Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Active Low When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation to be executed by the SSRAM. Active Low SSCE disable or enable SSRAM device operation. SSCE Input Pulse SDCLK Input Pulse SDCE Input Pulse Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3. SDRAS SDCAS SDWE Input Pulse Active Low When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation to be executed by the SDRAM. Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge. A0-16, SDA10 Input Level — During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to precharge. DQ0-31 Input Output Level BWE0-3 Input Pulse — Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Vcc, Vss Supply Power and ground for the input buffers and the core logic. VCCQ Supply Data base power supply pins, 3.3V (2.5V future). January 20001 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V ABSOLUTE MAXIMUM RATINGS Voltage on Vcc Relative to Vss RECOMMENDED DC OPERATING CONDITIONS (VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial) -0.5V to +4.6V Vin (DQx) -0.5V to Vcc +0.5V Storage Temperature (BGA) Parameter Supply Voltage (1) Input High Voltage (1,2) Input Low Voltage (1,2) Input Leakage Current 0 ≤ VIN ≤ Vcc Output Leakage (Output Disabled) 0 ≤ VIN ≤ Vcc Output High (IOH = -4mA) (1) Output Low (IOL = 8mA) (1) -55°C to +125°C Junction Temperature +175°C Short Circuit Output Current 100 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol VCC VIH VIL ILI Min 3.135 2.0 -0.3 -10 Max 3.6 VCC +0.3 0.8 10 Units V V V µA ILo -10 10 µA VOH VOL 2.4 — — 0.4 V V NOTES: 1. All voltages referenced to Vss (GND). 2. Overshoot: VIH ≤ +6.0V for t ≤ t KC/2 Underershoot: VIL ≥ -2.0V for t ≤ t KC/2 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial) Description Conditions Symbol Power Supply Current: Operating (1,2,3) SSRAM Active / DRAM Auto Refresh Icc1 Power Supply Current Operating (1,2,3) SSRAM Active / DRAM Idle Icc2 Power Supply Current Operating (1,2,3) SDRAM Active / SSRAM Idle Icc3 CMOS Standby TTL Standby SSCE and SDCE ≤ Vcc -0.2V, All other inputs at Vss +0.2 ≤ VIN or VIN ≤ VCC -0.2V, Clk frequency = 0 SSCE and SDCE ≤ VIH min All other inputs at VIL max ≤ VIN or VIN ≤ VCC -0.2V, Clk frequency = 0 Auto Refresh Frequency 133MHz 150MHz 166MHz 200MHz 133MHz 150MHz 166MHz 200MHz 83MHz 100MHz 125MHz Typ 400 450 500 550 300 350 400 450 220 235 255 Max 550 580 625 700 450 480 525 585 240 250 280 Units ISB1 20.0 40.0 mA ISB2 30.0 55.0 mA Icc5 190 250 mA mA mA mA NOTES: 1. I CC (operating) is specified with no output current. I CC (operating) increases with faster cycle times and greater output loading. 2. "Device idle" means device is deselected (CE ≥ VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency. BGA CAPACITANCE Description Conditions Symbol Typ Max Address Input Capacitance (1) T A = 25°C; f = 1MHz CI 5 8 pF Input/Output Capacitance (DQ) (1) T A = 25°C; f = 1MHz CO 8 10 pF Control Input Capacitance (1) T A = 25°C; f = 1MHz CA 5 8 pF T A = 25°C; f = 1MHz CCK 4 6 pF Clock Input Capacitance (1) NOTE: 1. This parameter is sampled. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 Units January 2001 WED9LC6416V SSRAM AC CHARACTERISTICS (VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial) Symbol Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output on Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock January 20001 t KHKH t KLKH t KHKL t KHQV t KHQX t KQLZ t KQHZ t OELQV t OELZ t OEHZ tS tH 200MHz Min Max 5 1.6 1.6 2.5 1.5 0 1.5 3 2.5 0 3.0 1.5 0.5 5 166MHz Min Max 6 2.4 2.4 3.5 1.5 0 1.5 3.5 3.5 0 3.5 1.5 0.5 150MHz Min Max 7 2.6 2.6 3.8 1.5 0 1.5 3.8 3.8 0 3.5 1.5 0.5 133MHz Min Max 8 2.8 2.8 4.0 1.5 0 1.5 4.0 4.0 0 3.8 1.5 0.5 Units ns ns ns ns ns ns ns ns ns ns ns ns White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V SSRAM OPERATION TRUTH TABLE Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None External External External Current Current Current Current Current Current SSCE H L L L X X H H X H SSADS L L L L H H H H H H SSWE X L H H H H H H L L SSOE X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D NOTE: 1. X means “don’t care”, H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. SSRAM PARTIAL TRUTH TABLE Function SSWE BWE0 READ H X BWE1 BWE2 X X X WRITE one Byte (DQ0-7) L L H H H WRITE all Bytes L L L L L White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com BWE3 6 January 2001 WED9LC6416V FIG. 3 SSRAM READ TIMING tKHKL t KHKH tKLKH SSCLK tH tS SSADS tS SSCE tH tS ADDR A1 A2 A3 A4 A5 tH SSOE t OEHQZ t OELQV SSWE t KHQX t KQLZ DQ FIG. 4 Q(A1) t KHQV Q(A2) Q(A3) Q(A4) Q(A5) SSRAM WRITE TIMING t KHKH tKHKL tKLKH SSCLK tH tS SSADS tH SSCE tH tS A2 A1 ADDR A3 A4 A5 tH SSOE tS KHG WX tH SSWE tS DQ January 20001 D(A1) tH D(A2) D(A3) 7 D (A4) D(A5) White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V SDRAM AC CHARACTERISTICS (VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial) Symbol Parameter Clock Cycle Time (1) CL = 3 CL = 2 Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CLK to Output Low-Z (2) CLK to Output High-Z Row Active to Row Active Delay (4) RAS\ to CAS\ Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,8) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) Number of Valid Output Data (7) t CC t CC t SAC t OH t CH t CL t SS t SH t SLZ t SHZ t RRD tRCD t RP t RAS t RC t RFC t CDL t RDL t BDL t CCD 125MHz Min 8 10 100MHz Max 1000 1000 6 3 3 3 2 1 2 Min 10 12 83MHz Max 1000 1000 7 3 3 3 2 1 2 7 20 20 20 50 70 70 1 1 1 1.5 2 1 10,000 Min 12 15 3 3 3 2 1 2 7 20 20 20 50 80 80 1 1 1 1.5 2 2 Max 1000 1000 8 10,000 8 24 24 24 60 90 90 1 1 1 1.5 2 1 10,000 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ea NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of t fall are longer than 1ns. [(trise = tfall )/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 8 January 2001 WED9LC6416V CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM (Unit = number of clock) Frequency CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 125MHz (8.0ns) 3 9 6 3 2 3 1 1 1 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 4 2 2 2 1 1 1 CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHz SDRAM (Unit = number of clock) Frequency CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (12.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 REFRESH CYCLE PARAMETERS -10 Parameter Refresh Period (1,2) -12 Symbol Min Max Min Max Units t REF — 64 — 64 ms NOTES: 1. 4096 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. SDRAM COMMAND TRUTH TABLE SDCE SDRAS Mode Register Set L L Auto Refresh (CBR) L L Single Bank L Precharge all Banks L Function Precharge SDCAS SDWE BWE A12, A13 SDA10 A11-0 L L X L H X X L H L X BA L L H L X X H Notes OP CODE X 2 Bank Activate L L H H X BA Row Address Write L H L L X BA L 2 2 Write with Auto Precharge L H L L X BA H 2 Read L H L L X BA L 2 Read with Auto Precharge L H L H X BA H 2 Burst Termination L H H L X X X 3 No Operation L H H H X X X Device Deselect H X X X X X X Data Write/Output Disable X X X X L X X 4 Data Mask/Output Disable X X X X H X X 4 NOTES: 1. All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE0-3 at the positive rising edge of the clock. 2. Bank Select (BA), if A12 (BA 0) and A 13 (BA 1 ) select between different banks. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). January 20001 9 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V MODE REGISTER SET TABLE A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11 10 9 8 7 6 5 4 Reserved* WB Op Mode CAS Latency 3 2 1 0 Address Bus Mode Register (Mx) BT Burst Length Burst Length *Should program M11, M10 = "0, 0" to ensure compatibility with future devices. M2 M1 M0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 Burst Type 0 Sequential 1 Interleaved M2 M1 M0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation --- --- --- All other states reserved M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 10 January 2001 WED9LC6416V SDRAM CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write Read with Auto Precharge January 20001 Command A12 & A13 (BA) SDWE A11-A0 Action Notes SDCE SDRAS SDCAS L L L L Mode Register Set Set the Mode Register 1 L L L H X X Auto or Self Refresh Start Auto 1 L L H L X X Precharge No Operation L L H H BA Row Address Bank Activate Activate the specified bank and row L H L L BA Column Write w/o Precharge ILLEGAL 2 L H L H BA Column Read w/o Precharge ILLEGAL 1 L H H L X X Burst Termination No Operation 1 L H H H X X No Operation No Operation H X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Precharge 3 L L H H BA Row Address Bank Activate ILLEGAL 1 L H L L BA Column Write Start Write; Determine if Auto Precharge 4,5 L H L H BA Column Read Start Read; Determine if Auto Precharge 4,5 L H H L X X Burst Termination No Operation L H H H X X No Operation No Operation H X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Terminate Burst; Start the Precharge OP Code X OP Code X OP Code Description L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Terminate Burst; Start the Write cycle 5,6 L H L H BA Column Read Terminate Burst; Start a new Read cycle 5,6 L H H L X X Burst Termination Terminate the Burst L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge Terminate Burst; Start the Precharge OP Code L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Terminate Burst; Start a new Write cycle 5,6 L H L H BA Column Read Terminate Burst; Start the Read cycle 5,6 L H H L X X Burst Termination Terminate the Burst L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst OP Code 11 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V SDRAM CURRENT STATE TRUTH TABLE (cont.) Current State Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge Command A12 & A13 (BA) SDWE A11-A0 Action Notes SDCE SDRAS SDCAS L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 ILLEGAL OP Code Description L H L L BA Column Write L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X Auto or Self Refresh ILLEGAL L L H L X X Precharge No Operation; Bank(s) idle after tRP L L H H BA Row Address Bank Activate ILLEGAL L H L L BA Column Write w/o Precharge ILLEGAL 2 L H L H BA Column Read w/o Precharge ILLEGAL 20 L H H L X X Burst Termination No Operation; Bank(s) idle after tRP L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X L L L L L L L H X L L H L L L H L H L H L OP Code X X 2 Device Deselect No Operation; Bank(s) idle after tRP Mode Register Set ILLEGAL X Auto or Self Refresh ILLEGAL X X Precharge ILLEGAL 2 H BA Row Address Bank Activate ILLEGAL 2 L L BA Column Write ILLEGAL 2 L H BA Column Read ILLEGAL 2 H H L X X Burst Termination No Operation; Row active after tRCD OP Code L H H H X X No Operation No Operation; Row active after tRCD H X X X X X Device Deselect No Operation; Row active after tRCD L L L L Mode Register Set ILLEGAL L L L H X X Auto orSelf Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write Start Write; Determine if Auto Precharge 6 L H L H BA Column Read Start Read; Determine if Auto Precharge 6 L H H L X X Burst Termination No Operation; Row active after tDPL OP Code L H H H X X No Operation No Operation; Row active after tDPL H X X X X X Device Deselect No Operation; Row active after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto orSelf Refresh ILLEGAL L L H L X X Precharge ILLEGAL 2 L L H H BA Row Address Bank Activate ILLEGAL 2 L H L L BA Column Write ILLEGAL 2,6 L H L H BA Column Read ILLEGAL 2,6 L H H L X X Burst Termination No Operation; Precharge after tDPL L H H H X X No Operation No Operation; Precharge after tDPL H X X X X X Device Deselect No Operation; Precharge after tDPL OP Code White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 12 January 2001 WED9LC6416V SDRAM CURRENT STATE TRUTH TABLE (cont.) Current State Refreshing Mode Register Accessing SDCE SDRAS SDCAS L L L Command A12 & A13 A11-A0 (BA) L OP Code Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL L H L L BA Column Write ILLEGAL L H L H BA Column Read ILLEGAL L H H L X X Burst Termination No Operation; Idle after tRC SDWE Description Action L H H H X X No Operation No Operation; Idle after tRC H X X X X X Device Deselect No Operation; Idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L X X Precharge ILLEGAL L L H H BA Row Address Bank Activate ILLEGAL ILLEGAL OP Code L H L L BA Column Write L H L H BA Column Read ILLEGAL L H H L X X Burst Termination ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles Notes NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (t RAS) must be satisfied. 4. The RAS to CAS Delay (t RCD) must occur before the command is given. 5. Address SDA 10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied. January 20001 13 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK t CH t CC t CL t RCD t RAS SDCE t SS t RCD t SS t SH t RP t SH SDRAS t SS t CCD t SH SDCAS t SS t SS t SH ADDR Ra BA BS SDA10 Ra t SH Ca Cb Note 2, 3 Note 2, 3 BS BS BS BS BS Note 3 Note 3 Note 3 Note 4 Rb t RAC t SS t SAC Qa DQ t SLZ t OH Cc Rb Note 2, 3 Note 4 Note 2 t SH Db Qc t SS t SH t SS t SH SDWE BWE Row Active Read Write Read Precharge White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 14 Row Active DON’T CARE January 2001 WED9LC6416V FIG. 6 SDRAM POWER UP SEQUENCE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK SDCE t RFC t RP t RFC SDRAS SDCAS ADDR Key RAa BA RAa SDA10 HIGH-Z DQ SDWE BWE High level is necessary Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Row Active (A-Bank) DON’T CARE January 20001 15 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK Note 1 t RC SDCE t RCD SDRAS SDCAS ADDR Ra Ca0 Rb Cb0 BA SDA10 Ra Rb t SHZ t RAC Note 3 Qa0 CL = 2 Qa1 t RAC DQ Note 3 Qa2 t RDL Qa3 t SHZ t OH t SAC Qa0 CL = 3 Note 4 t OH t SAC Qa1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 Note 4 Qa3 t RDL SDWE BWE Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ ) after the clock. 3. Access time from Row active command. t CC *(t RCD + CAS Latency - 1) + tSAC . 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 16 January 2001 WED9LC6416V FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK SDCE t RCD SDRAS Note 2 SDCAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA SDA10 Ra t RDL Qa0 CL = 2 Qa1 Qb0 Qb1 Qb2 Dc0 DQ Dc1 Dd0 Dd1 t CDL Qa0 CL = 3 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 SDWE Note 1 Note 3 BWE Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. January 20001 17 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK Note 1 SDCE SDRAS Note 2 SDCAS ADDR RAa CAa RBb CBb CAc CBd CAe BA SDA10 RAa RBb QAa0 CL = 2 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 DQ CL = 3 QBb2 QAe1 SDWE BWE Row Active (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Read (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 18 January 2001 WED9LC6416V FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK SDCE SDRAS Note 2 SDCAS ADDR RAa CAa RBb CBb CAc CBd BA SDA10 RAa RBb t CDL DAa0 DQ DAa1 DAa2 DAa3 DBb0 t RDL DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 SDWE Note 1 BWE Row Active (A-Bank) Row Active (B-Bank) Write (B-Bank) Write (A-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. January 20001 19 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QAc0 QAc1 QAc2 QAc0 QAc1 SDCLK SDCE SDRAS SDCAS ADDR RAa RBb CAa CBb RAc CAc BA SDA10 RAa RBb RAc t CDL QAa0 CL = 2 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Note 1 DQ CL = 3 QAa3 SDWE BWE Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (B-Bank) Row Active (B-Bank) Row Active (A-Bank) Read (A-Bank) DON’T CARE NOTES: 1. tCDL should be met to complete write. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 20 January 2001 WED9LC6416V FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK SDCE SDRAS SDCAS ADDR Ra Rb Ra Rb Ca Cb BA SDA10 Qa0 CL = 2 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 DQ CL = 3 Qa3 SDWE BWE Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) DON’T CARE NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode) January 20001 21 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 19 SDCLK SDCE SDRAS SDCAS ADDR RAa CAa CAb BA SDA10 RAa Note 2 QAa0 CL = 2 1 QAa1 QAa2 QAa3 QAa4 QAa0 QAa1 QAa2 QAa3 1 DQ 2 CL = 3 QAa4 2 QAb5 SDWE BWE Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”. 3. Burst stop is valid at every burst length. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 22 January 2001 WED9LC6416V FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDCLK SDCE SDRAS SDCAS ADDR RAa CAa CAb BA SDA10 RAa t BDL t RDL Note 2 DAa0 DQ DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 SDWE BWE Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL . BWE at write interrupt by precharge command is needed to prevent invalid write. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. January 20001 23 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAd0 QAd1 19 SDCLK SDCE SDRAS Note 2 SDCAS ADDR RAa CAa RBb CAb RAc CBc CAd BA SDA10 RAa RBb DAa0 CL = 2 RAc QAb0 QAb1 DBc0 DQ DAa0 CL = 3 QAb0 QAb1 DBc0 QAd0 QAd1 SDWE BWE Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Row Active (A-Bank) Read with Auto Precharge (A-Bank) Read (A-Bank) Write with Auto Precharge (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 24 January 2001 WED9LC6416V FIG. 16 SDRAM MODE REGISTER SET CYCLE 0 1 2 3 4 5 6 SDRAM AUTO REFRESH CYCLE 0 1 2 3 4 5 6 7 8 9 10 SDCLK HIGH SDCE Note 2 t RFC SDRAS Note 1 SDCAS Note 3 Key ADDR DQ Ra HI-Z HI-Z SDWE BWE MRS New Command Auto Refresh New Command DON'T CARE *Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle. NOTES: MODE REGISTER SET CYCLE 1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new SDRAS activation. 3. Please refer to Mode Register Set Table. January 20001 25 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V PACKAGE DESCRIPTION: 153 LEAD BGA (17 x 9 BALL ARRAY) JEDEC MO-163 3.50 (0.138) MAX 14.00 (0.551) BSC A B PIN 1 INDEX C D E F G H 22.00 (0.866) BSC J K L M N P R T U 1.27 (0.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION COMMERCIAL (0°C ≤ TA ≤ 70°C) INDUSTRIAL (-40°C ≤ TA ≤ 85°C) Part Number WED9LC6416V2012BC SSRAM Access 200MHz SDRAM Access 125MHz Part Number WED9LC6416V2012BI SSRAM Access 200MHz SDRAM Access 125MHz WED9LC6416V2010BC 200MHz 100MHz WED9LC6416V2010BI 200MHz 100MHz WED9LC6416V1612BC 166MHz 125MHz WED9LC6416V1612BI 166MHz 125MHz WED9LC6416V1610BC 166MHz 100MHz WED9LC6416V1610BI 166MHz 100MHz WED9LC6416V1512BC 150MHz 125MHz WED9LC6416V1512BI 150MHz 125MHz WED9LC6416V1510BC 150MHz 100MHz WED9LC6416V1510BI 150MHz 100MHz WED9LC6416V1312BC 133MHz 125MHz WED9LC6416V1312BI 133MHz 125MHz WED9LC6416V1310BC 133MHz 100MHz WED9LC6416V1310BI 133MHz 100MHz White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 26 January 2001 WED9LC6416V FIG. 17 INTERFACING THE TEXAS INSTRUMENTS TMS320C6x WITH THE WED9LC6416V (128Kx32 SSRAM/4Mx32 SDRAM) Address Bus EA2-21 EA2 A0 EA3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Texas Instruments TMS320C6x DSP SSWE\ CE2\ SSOE\ SSADS\ SSCLK BE0\ BE1\ BE2\ BE3\ Data Bus ED0-31 January 20001 SDA10 CE0\ SDRAS\ SDCAS\ SDWE\ SDCLK 27 WED9LC6416V 128K x 32 SSRAM 4M x 32 SDRAM DQ0-7 DQ8-15 DQ16-23 DQ24-31 SSWE\ SSCE\ SSOE\ SSADC\ SSCLK SSRAM Control BWE0\ BWE1\ BWE2\ BWE3\ Shared Controls SDA10 SDCE\ SDRAS\ SDCAS\ SDWE\ SDCLK SDRAM Control White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com